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757 lines
16 KiB
757 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/interrupt.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/sort.h> |
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#include <soc/tegra/fuse.h> |
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#include "mc.h" |
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static const struct of_device_id tegra_mc_of_match[] = { |
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC |
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{ .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc }, |
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#endif |
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC |
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{ .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc }, |
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#endif |
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#ifdef CONFIG_ARCH_TEGRA_114_SOC |
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{ .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc }, |
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#endif |
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#ifdef CONFIG_ARCH_TEGRA_124_SOC |
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{ .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc }, |
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#endif |
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#ifdef CONFIG_ARCH_TEGRA_132_SOC |
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{ .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc }, |
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#endif |
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#ifdef CONFIG_ARCH_TEGRA_210_SOC |
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{ .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc }, |
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#endif |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, tegra_mc_of_match); |
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static int tegra_mc_block_dma_common(struct tegra_mc *mc, |
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const struct tegra_mc_reset *rst) |
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{ |
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unsigned long flags; |
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u32 value; |
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spin_lock_irqsave(&mc->lock, flags); |
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value = mc_readl(mc, rst->control) | BIT(rst->bit); |
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mc_writel(mc, value, rst->control); |
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spin_unlock_irqrestore(&mc->lock, flags); |
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return 0; |
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} |
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static bool tegra_mc_dma_idling_common(struct tegra_mc *mc, |
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const struct tegra_mc_reset *rst) |
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{ |
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return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0; |
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} |
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static int tegra_mc_unblock_dma_common(struct tegra_mc *mc, |
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const struct tegra_mc_reset *rst) |
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{ |
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unsigned long flags; |
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u32 value; |
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spin_lock_irqsave(&mc->lock, flags); |
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value = mc_readl(mc, rst->control) & ~BIT(rst->bit); |
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mc_writel(mc, value, rst->control); |
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spin_unlock_irqrestore(&mc->lock, flags); |
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return 0; |
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} |
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static int tegra_mc_reset_status_common(struct tegra_mc *mc, |
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const struct tegra_mc_reset *rst) |
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{ |
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return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0; |
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} |
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const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = { |
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.block_dma = tegra_mc_block_dma_common, |
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.dma_idling = tegra_mc_dma_idling_common, |
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.unblock_dma = tegra_mc_unblock_dma_common, |
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.reset_status = tegra_mc_reset_status_common, |
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}; |
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static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev) |
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{ |
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return container_of(rcdev, struct tegra_mc, reset); |
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} |
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static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc, |
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unsigned long id) |
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{ |
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unsigned int i; |
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for (i = 0; i < mc->soc->num_resets; i++) |
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if (mc->soc->resets[i].id == id) |
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return &mc->soc->resets[i]; |
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return NULL; |
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} |
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static int tegra_mc_hotreset_assert(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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struct tegra_mc *mc = reset_to_mc(rcdev); |
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const struct tegra_mc_reset_ops *rst_ops; |
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const struct tegra_mc_reset *rst; |
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int retries = 500; |
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int err; |
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rst = tegra_mc_reset_find(mc, id); |
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if (!rst) |
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return -ENODEV; |
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rst_ops = mc->soc->reset_ops; |
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if (!rst_ops) |
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return -ENODEV; |
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if (rst_ops->block_dma) { |
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/* block clients DMA requests */ |
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err = rst_ops->block_dma(mc, rst); |
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if (err) { |
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dev_err(mc->dev, "failed to block %s DMA: %d\n", |
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rst->name, err); |
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return err; |
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} |
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} |
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if (rst_ops->dma_idling) { |
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/* wait for completion of the outstanding DMA requests */ |
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while (!rst_ops->dma_idling(mc, rst)) { |
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if (!retries--) { |
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dev_err(mc->dev, "failed to flush %s DMA\n", |
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rst->name); |
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return -EBUSY; |
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} |
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usleep_range(10, 100); |
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} |
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} |
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if (rst_ops->hotreset_assert) { |
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/* clear clients DMA requests sitting before arbitration */ |
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err = rst_ops->hotreset_assert(mc, rst); |
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if (err) { |
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dev_err(mc->dev, "failed to hot reset %s: %d\n", |
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rst->name, err); |
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return err; |
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} |
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} |
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return 0; |
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} |
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static int tegra_mc_hotreset_deassert(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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struct tegra_mc *mc = reset_to_mc(rcdev); |
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const struct tegra_mc_reset_ops *rst_ops; |
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const struct tegra_mc_reset *rst; |
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int err; |
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rst = tegra_mc_reset_find(mc, id); |
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if (!rst) |
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return -ENODEV; |
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rst_ops = mc->soc->reset_ops; |
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if (!rst_ops) |
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return -ENODEV; |
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if (rst_ops->hotreset_deassert) { |
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/* take out client from hot reset */ |
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err = rst_ops->hotreset_deassert(mc, rst); |
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if (err) { |
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dev_err(mc->dev, "failed to deassert hot reset %s: %d\n", |
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rst->name, err); |
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return err; |
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} |
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} |
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if (rst_ops->unblock_dma) { |
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/* allow new DMA requests to proceed to arbitration */ |
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err = rst_ops->unblock_dma(mc, rst); |
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if (err) { |
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dev_err(mc->dev, "failed to unblock %s DMA : %d\n", |
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rst->name, err); |
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return err; |
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} |
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} |
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return 0; |
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} |
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static int tegra_mc_hotreset_status(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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struct tegra_mc *mc = reset_to_mc(rcdev); |
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const struct tegra_mc_reset_ops *rst_ops; |
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const struct tegra_mc_reset *rst; |
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rst = tegra_mc_reset_find(mc, id); |
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if (!rst) |
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return -ENODEV; |
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rst_ops = mc->soc->reset_ops; |
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if (!rst_ops) |
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return -ENODEV; |
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return rst_ops->reset_status(mc, rst); |
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} |
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static const struct reset_control_ops tegra_mc_reset_ops = { |
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.assert = tegra_mc_hotreset_assert, |
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.deassert = tegra_mc_hotreset_deassert, |
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.status = tegra_mc_hotreset_status, |
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}; |
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static int tegra_mc_reset_setup(struct tegra_mc *mc) |
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{ |
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int err; |
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mc->reset.ops = &tegra_mc_reset_ops; |
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mc->reset.owner = THIS_MODULE; |
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mc->reset.of_node = mc->dev->of_node; |
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mc->reset.of_reset_n_cells = 1; |
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mc->reset.nr_resets = mc->soc->num_resets; |
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err = reset_controller_register(&mc->reset); |
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if (err < 0) |
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return err; |
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return 0; |
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} |
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static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc) |
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{ |
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unsigned long long tick; |
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unsigned int i; |
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u32 value; |
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/* compute the number of MC clock cycles per tick */ |
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tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk); |
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do_div(tick, NSEC_PER_SEC); |
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value = mc_readl(mc, MC_EMEM_ARB_CFG); |
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value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK; |
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value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick); |
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mc_writel(mc, value, MC_EMEM_ARB_CFG); |
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/* write latency allowance defaults */ |
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for (i = 0; i < mc->soc->num_clients; i++) { |
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const struct tegra_mc_la *la = &mc->soc->clients[i].la; |
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u32 value; |
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value = mc_readl(mc, la->reg); |
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value &= ~(la->mask << la->shift); |
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value |= (la->def & la->mask) << la->shift; |
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mc_writel(mc, value, la->reg); |
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} |
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/* latch new values */ |
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mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); |
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return 0; |
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} |
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int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) |
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{ |
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unsigned int i; |
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struct tegra_mc_timing *timing = NULL; |
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for (i = 0; i < mc->num_timings; i++) { |
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if (mc->timings[i].rate == rate) { |
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timing = &mc->timings[i]; |
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break; |
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} |
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} |
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if (!timing) { |
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dev_err(mc->dev, "no memory timing registered for rate %lu\n", |
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rate); |
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return -EINVAL; |
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} |
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for (i = 0; i < mc->soc->num_emem_regs; ++i) |
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mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); |
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return 0; |
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} |
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unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) |
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{ |
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u8 dram_count; |
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dram_count = mc_readl(mc, MC_EMEM_ADR_CFG); |
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dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV; |
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dram_count++; |
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return dram_count; |
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} |
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static int load_one_timing(struct tegra_mc *mc, |
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struct tegra_mc_timing *timing, |
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struct device_node *node) |
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{ |
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int err; |
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u32 tmp; |
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err = of_property_read_u32(node, "clock-frequency", &tmp); |
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if (err) { |
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dev_err(mc->dev, |
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"timing %pOFn: failed to read rate\n", node); |
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return err; |
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} |
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timing->rate = tmp; |
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timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs, |
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sizeof(u32), GFP_KERNEL); |
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if (!timing->emem_data) |
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return -ENOMEM; |
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err = of_property_read_u32_array(node, "nvidia,emem-configuration", |
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timing->emem_data, |
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mc->soc->num_emem_regs); |
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if (err) { |
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dev_err(mc->dev, |
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"timing %pOFn: failed to read EMEM configuration\n", |
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node); |
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return err; |
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} |
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return 0; |
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} |
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static int load_timings(struct tegra_mc *mc, struct device_node *node) |
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{ |
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struct device_node *child; |
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struct tegra_mc_timing *timing; |
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int child_count = of_get_child_count(node); |
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int i = 0, err; |
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mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing), |
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GFP_KERNEL); |
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if (!mc->timings) |
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return -ENOMEM; |
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mc->num_timings = child_count; |
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for_each_child_of_node(node, child) { |
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timing = &mc->timings[i++]; |
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err = load_one_timing(mc, timing, child); |
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if (err) { |
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of_node_put(child); |
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return err; |
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} |
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} |
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return 0; |
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} |
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static int tegra_mc_setup_timings(struct tegra_mc *mc) |
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{ |
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struct device_node *node; |
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u32 ram_code, node_ram_code; |
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int err; |
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ram_code = tegra_read_ram_code(); |
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mc->num_timings = 0; |
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for_each_child_of_node(mc->dev->of_node, node) { |
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err = of_property_read_u32(node, "nvidia,ram-code", |
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&node_ram_code); |
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if (err || (node_ram_code != ram_code)) |
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continue; |
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err = load_timings(mc, node); |
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of_node_put(node); |
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if (err) |
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return err; |
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break; |
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} |
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if (mc->num_timings == 0) |
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dev_warn(mc->dev, |
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"no memory timings for RAM code %u registered\n", |
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ram_code); |
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return 0; |
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} |
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static const char *const status_names[32] = { |
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[ 1] = "External interrupt", |
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[ 6] = "EMEM address decode error", |
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[ 7] = "GART page fault", |
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[ 8] = "Security violation", |
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[ 9] = "EMEM arbitration error", |
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[10] = "Page fault", |
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[11] = "Invalid APB ASID update", |
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[12] = "VPR violation", |
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[13] = "Secure carveout violation", |
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[16] = "MTS carveout violation", |
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}; |
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static const char *const error_names[8] = { |
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[2] = "EMEM decode error", |
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[3] = "TrustZone violation", |
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[4] = "Carveout violation", |
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[6] = "SMMU translation error", |
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}; |
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static irqreturn_t tegra_mc_irq(int irq, void *data) |
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{ |
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struct tegra_mc *mc = data; |
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unsigned long status; |
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unsigned int bit; |
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/* mask all interrupts to avoid flooding */ |
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status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; |
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if (!status) |
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return IRQ_NONE; |
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for_each_set_bit(bit, &status, 32) { |
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const char *error = status_names[bit] ?: "unknown"; |
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const char *client = "unknown", *desc; |
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const char *direction, *secure; |
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phys_addr_t addr = 0; |
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unsigned int i; |
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char perm[7]; |
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u8 id, type; |
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u32 value; |
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value = mc_readl(mc, MC_ERR_STATUS); |
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#ifdef CONFIG_PHYS_ADDR_T_64BIT |
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if (mc->soc->num_address_bits > 32) { |
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addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & |
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MC_ERR_STATUS_ADR_HI_MASK); |
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addr <<= 32; |
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} |
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#endif |
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if (value & MC_ERR_STATUS_RW) |
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direction = "write"; |
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else |
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direction = "read"; |
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if (value & MC_ERR_STATUS_SECURITY) |
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secure = "secure "; |
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else |
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secure = ""; |
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id = value & mc->soc->client_id_mask; |
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for (i = 0; i < mc->soc->num_clients; i++) { |
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if (mc->soc->clients[i].id == id) { |
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client = mc->soc->clients[i].name; |
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break; |
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} |
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} |
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type = (value & MC_ERR_STATUS_TYPE_MASK) >> |
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MC_ERR_STATUS_TYPE_SHIFT; |
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desc = error_names[type]; |
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switch (value & MC_ERR_STATUS_TYPE_MASK) { |
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case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE: |
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perm[0] = ' '; |
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perm[1] = '['; |
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if (value & MC_ERR_STATUS_READABLE) |
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perm[2] = 'R'; |
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else |
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perm[2] = '-'; |
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if (value & MC_ERR_STATUS_WRITABLE) |
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perm[3] = 'W'; |
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else |
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perm[3] = '-'; |
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if (value & MC_ERR_STATUS_NONSECURE) |
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perm[4] = '-'; |
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else |
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perm[4] = 'S'; |
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perm[5] = ']'; |
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perm[6] = '\0'; |
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break; |
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default: |
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perm[0] = '\0'; |
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break; |
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} |
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value = mc_readl(mc, MC_ERR_ADR); |
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addr |= value; |
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dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", |
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client, secure, direction, &addr, error, |
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desc, perm); |
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} |
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/* clear interrupts */ |
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mc_writel(mc, status, MC_INTSTATUS); |
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return IRQ_HANDLED; |
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} |
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static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data) |
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{ |
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struct tegra_mc *mc = data; |
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unsigned long status; |
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unsigned int bit; |
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/* mask all interrupts to avoid flooding */ |
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status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; |
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if (!status) |
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return IRQ_NONE; |
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for_each_set_bit(bit, &status, 32) { |
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const char *direction = "read", *secure = ""; |
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const char *error = status_names[bit]; |
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const char *client, *desc; |
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phys_addr_t addr; |
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u32 value, reg; |
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u8 id, type; |
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|
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switch (BIT(bit)) { |
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case MC_INT_DECERR_EMEM: |
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reg = MC_DECERR_EMEM_OTHERS_STATUS; |
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value = mc_readl(mc, reg); |
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id = value & mc->soc->client_id_mask; |
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desc = error_names[2]; |
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if (value & BIT(31)) |
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direction = "write"; |
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break; |
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case MC_INT_INVALID_GART_PAGE: |
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reg = MC_GART_ERROR_REQ; |
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value = mc_readl(mc, reg); |
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id = (value >> 1) & mc->soc->client_id_mask; |
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desc = error_names[2]; |
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if (value & BIT(0)) |
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direction = "write"; |
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break; |
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case MC_INT_SECURITY_VIOLATION: |
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reg = MC_SECURITY_VIOLATION_STATUS; |
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value = mc_readl(mc, reg); |
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id = value & mc->soc->client_id_mask; |
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type = (value & BIT(30)) ? 4 : 3; |
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desc = error_names[type]; |
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secure = "secure "; |
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if (value & BIT(31)) |
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direction = "write"; |
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break; |
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default: |
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continue; |
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} |
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client = mc->soc->clients[id].name; |
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addr = mc_readl(mc, reg + sizeof(u32)); |
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|
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dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n", |
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client, secure, direction, &addr, error, |
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desc); |
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} |
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|
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/* clear interrupts */ |
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mc_writel(mc, status, MC_INTSTATUS); |
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|
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return IRQ_HANDLED; |
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} |
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|
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static int tegra_mc_probe(struct platform_device *pdev) |
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{ |
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struct resource *res; |
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struct tegra_mc *mc; |
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void *isr; |
|
u64 mask; |
|
int err; |
|
|
|
mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); |
|
if (!mc) |
|
return -ENOMEM; |
|
|
|
platform_set_drvdata(pdev, mc); |
|
spin_lock_init(&mc->lock); |
|
mc->soc = of_device_get_match_data(&pdev->dev); |
|
mc->dev = &pdev->dev; |
|
|
|
mask = DMA_BIT_MASK(mc->soc->num_address_bits); |
|
|
|
err = dma_coerce_mask_and_coherent(&pdev->dev, mask); |
|
if (err < 0) { |
|
dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); |
|
return err; |
|
} |
|
|
|
/* length of MC tick in nanoseconds */ |
|
mc->tick = 30; |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
mc->regs = devm_ioremap_resource(&pdev->dev, res); |
|
if (IS_ERR(mc->regs)) |
|
return PTR_ERR(mc->regs); |
|
|
|
mc->clk = devm_clk_get(&pdev->dev, "mc"); |
|
if (IS_ERR(mc->clk)) { |
|
dev_err(&pdev->dev, "failed to get MC clock: %ld\n", |
|
PTR_ERR(mc->clk)); |
|
return PTR_ERR(mc->clk); |
|
} |
|
|
|
#ifdef CONFIG_ARCH_TEGRA_2x_SOC |
|
if (mc->soc == &tegra20_mc_soc) { |
|
isr = tegra20_mc_irq; |
|
} else |
|
#endif |
|
{ |
|
/* ensure that debug features are disabled */ |
|
mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG); |
|
|
|
err = tegra_mc_setup_latency_allowance(mc); |
|
if (err < 0) { |
|
dev_err(&pdev->dev, |
|
"failed to setup latency allowance: %d\n", |
|
err); |
|
return err; |
|
} |
|
|
|
isr = tegra_mc_irq; |
|
|
|
err = tegra_mc_setup_timings(mc); |
|
if (err < 0) { |
|
dev_err(&pdev->dev, "failed to setup timings: %d\n", |
|
err); |
|
return err; |
|
} |
|
} |
|
|
|
mc->irq = platform_get_irq(pdev, 0); |
|
if (mc->irq < 0) { |
|
dev_err(&pdev->dev, "interrupt not specified\n"); |
|
return mc->irq; |
|
} |
|
|
|
WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); |
|
|
|
mc_writel(mc, mc->soc->intmask, MC_INTMASK); |
|
|
|
err = devm_request_irq(&pdev->dev, mc->irq, isr, 0, |
|
dev_name(&pdev->dev), mc); |
|
if (err < 0) { |
|
dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq, |
|
err); |
|
return err; |
|
} |
|
|
|
err = tegra_mc_reset_setup(mc); |
|
if (err < 0) |
|
dev_err(&pdev->dev, "failed to register reset controller: %d\n", |
|
err); |
|
|
|
if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) { |
|
mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); |
|
if (IS_ERR(mc->smmu)) { |
|
dev_err(&pdev->dev, "failed to probe SMMU: %ld\n", |
|
PTR_ERR(mc->smmu)); |
|
mc->smmu = NULL; |
|
} |
|
} |
|
|
|
if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && !mc->soc->smmu) { |
|
mc->gart = tegra_gart_probe(&pdev->dev, mc); |
|
if (IS_ERR(mc->gart)) { |
|
dev_err(&pdev->dev, "failed to probe GART: %ld\n", |
|
PTR_ERR(mc->gart)); |
|
mc->gart = NULL; |
|
} |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int tegra_mc_suspend(struct device *dev) |
|
{ |
|
struct tegra_mc *mc = dev_get_drvdata(dev); |
|
int err; |
|
|
|
if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) { |
|
err = tegra_gart_suspend(mc->gart); |
|
if (err) |
|
return err; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int tegra_mc_resume(struct device *dev) |
|
{ |
|
struct tegra_mc *mc = dev_get_drvdata(dev); |
|
int err; |
|
|
|
if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) { |
|
err = tegra_gart_resume(mc->gart); |
|
if (err) |
|
return err; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static const struct dev_pm_ops tegra_mc_pm_ops = { |
|
.suspend = tegra_mc_suspend, |
|
.resume = tegra_mc_resume, |
|
}; |
|
|
|
static struct platform_driver tegra_mc_driver = { |
|
.driver = { |
|
.name = "tegra-mc", |
|
.of_match_table = tegra_mc_of_match, |
|
.pm = &tegra_mc_pm_ops, |
|
.suppress_bind_attrs = true, |
|
}, |
|
.prevent_deferred_probe = true, |
|
.probe = tegra_mc_probe, |
|
}; |
|
|
|
static int tegra_mc_init(void) |
|
{ |
|
return platform_driver_register(&tegra_mc_driver); |
|
} |
|
arch_initcall(tegra_mc_init); |
|
|
|
MODULE_AUTHOR("Thierry Reding <[email protected]>"); |
|
MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|