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464 lines
12 KiB
464 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* ARM PL353 SMC driver |
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* |
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* Copyright (C) 2012 - 2018 Xilinx, Inc |
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* Author: Punnaiah Choudary Kalluri <[email protected]> |
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* Author: Naga Sureshkumar Relli <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of_platform.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/pl353-smc.h> |
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#include <linux/amba/bus.h> |
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/* Register definitions */ |
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#define PL353_SMC_MEMC_STATUS_OFFS 0 /* Controller status reg, RO */ |
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#define PL353_SMC_CFG_CLR_OFFS 0xC /* Clear config reg, WO */ |
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#define PL353_SMC_DIRECT_CMD_OFFS 0x10 /* Direct command reg, WO */ |
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#define PL353_SMC_SET_CYCLES_OFFS 0x14 /* Set cycles register, WO */ |
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#define PL353_SMC_SET_OPMODE_OFFS 0x18 /* Set opmode register, WO */ |
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#define PL353_SMC_ECC_STATUS_OFFS 0x400 /* ECC status register */ |
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#define PL353_SMC_ECC_MEMCFG_OFFS 0x404 /* ECC mem config reg */ |
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#define PL353_SMC_ECC_MEMCMD1_OFFS 0x408 /* ECC mem cmd1 reg */ |
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#define PL353_SMC_ECC_MEMCMD2_OFFS 0x40C /* ECC mem cmd2 reg */ |
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#define PL353_SMC_ECC_VALUE0_OFFS 0x418 /* ECC value 0 reg */ |
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|
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/* Controller status register specific constants */ |
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#define PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT 6 |
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/* Clear configuration register specific constants */ |
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#define PL353_SMC_CFG_CLR_INT_CLR_1 0x10 |
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#define PL353_SMC_CFG_CLR_ECC_INT_DIS_1 0x40 |
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#define PL353_SMC_CFG_CLR_INT_DIS_1 0x2 |
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#define PL353_SMC_CFG_CLR_DEFAULT_MASK (PL353_SMC_CFG_CLR_INT_CLR_1 | \ |
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PL353_SMC_CFG_CLR_ECC_INT_DIS_1 | \ |
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PL353_SMC_CFG_CLR_INT_DIS_1) |
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/* Set cycles register specific constants */ |
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#define PL353_SMC_SET_CYCLES_T0_MASK 0xF |
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#define PL353_SMC_SET_CYCLES_T0_SHIFT 0 |
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#define PL353_SMC_SET_CYCLES_T1_MASK 0xF |
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#define PL353_SMC_SET_CYCLES_T1_SHIFT 4 |
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#define PL353_SMC_SET_CYCLES_T2_MASK 0x7 |
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#define PL353_SMC_SET_CYCLES_T2_SHIFT 8 |
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#define PL353_SMC_SET_CYCLES_T3_MASK 0x7 |
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#define PL353_SMC_SET_CYCLES_T3_SHIFT 11 |
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#define PL353_SMC_SET_CYCLES_T4_MASK 0x7 |
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#define PL353_SMC_SET_CYCLES_T4_SHIFT 14 |
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#define PL353_SMC_SET_CYCLES_T5_MASK 0x7 |
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#define PL353_SMC_SET_CYCLES_T5_SHIFT 17 |
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#define PL353_SMC_SET_CYCLES_T6_MASK 0xF |
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#define PL353_SMC_SET_CYCLES_T6_SHIFT 20 |
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/* ECC status register specific constants */ |
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#define PL353_SMC_ECC_STATUS_BUSY BIT(6) |
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#define PL353_SMC_ECC_REG_SIZE_OFFS 4 |
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/* ECC memory config register specific constants */ |
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#define PL353_SMC_ECC_MEMCFG_MODE_MASK 0xC |
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#define PL353_SMC_ECC_MEMCFG_MODE_SHIFT 2 |
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#define PL353_SMC_ECC_MEMCFG_PGSIZE_MASK 0x3 |
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#define PL353_SMC_DC_UPT_NAND_REGS ((4 << 23) | /* CS: NAND chip */ \ |
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(2 << 21)) /* UpdateRegs operation */ |
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#define PL353_NAND_ECC_CMD1 ((0x80) | /* Write command */ \ |
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(0 << 8) | /* Read command */ \ |
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(0x30 << 16) | /* Read End command */ \ |
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(1 << 24)) /* Read End command calid */ |
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#define PL353_NAND_ECC_CMD2 ((0x85) | /* Write col change cmd */ \ |
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(5 << 8) | /* Read col change cmd */ \ |
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(0xE0 << 16) | /* Read col change end cmd */ \ |
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(1 << 24)) /* Read col change end cmd valid */ |
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#define PL353_NAND_ECC_BUSY_TIMEOUT (1 * HZ) |
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/** |
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* struct pl353_smc_data - Private smc driver structure |
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* @memclk: Pointer to the peripheral clock |
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* @aclk: Pointer to the APER clock |
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*/ |
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struct pl353_smc_data { |
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struct clk *memclk; |
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struct clk *aclk; |
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}; |
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/* SMC virtual register base */ |
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static void __iomem *pl353_smc_base; |
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/** |
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* pl353_smc_set_buswidth - Set memory buswidth |
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* @bw: Memory buswidth (8 | 16) |
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* Return: 0 on success or negative errno. |
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*/ |
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int pl353_smc_set_buswidth(unsigned int bw) |
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{ |
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if (bw != PL353_SMC_MEM_WIDTH_8 && bw != PL353_SMC_MEM_WIDTH_16) |
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return -EINVAL; |
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writel(bw, pl353_smc_base + PL353_SMC_SET_OPMODE_OFFS); |
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writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base + |
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PL353_SMC_DIRECT_CMD_OFFS); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(pl353_smc_set_buswidth); |
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/** |
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* pl353_smc_set_cycles - Set memory timing parameters |
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* @timings: NAND controller timing parameters |
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* |
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* Sets NAND chip specific timing parameters. |
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*/ |
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void pl353_smc_set_cycles(u32 timings[]) |
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{ |
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/* |
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* Set write pulse timing. This one is easy to extract: |
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* |
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* NWE_PULSE = tWP |
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*/ |
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timings[0] &= PL353_SMC_SET_CYCLES_T0_MASK; |
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timings[1] = (timings[1] & PL353_SMC_SET_CYCLES_T1_MASK) << |
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PL353_SMC_SET_CYCLES_T1_SHIFT; |
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timings[2] = (timings[2] & PL353_SMC_SET_CYCLES_T2_MASK) << |
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PL353_SMC_SET_CYCLES_T2_SHIFT; |
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timings[3] = (timings[3] & PL353_SMC_SET_CYCLES_T3_MASK) << |
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PL353_SMC_SET_CYCLES_T3_SHIFT; |
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timings[4] = (timings[4] & PL353_SMC_SET_CYCLES_T4_MASK) << |
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PL353_SMC_SET_CYCLES_T4_SHIFT; |
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timings[5] = (timings[5] & PL353_SMC_SET_CYCLES_T5_MASK) << |
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PL353_SMC_SET_CYCLES_T5_SHIFT; |
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timings[6] = (timings[6] & PL353_SMC_SET_CYCLES_T6_MASK) << |
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PL353_SMC_SET_CYCLES_T6_SHIFT; |
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timings[0] |= timings[1] | timings[2] | timings[3] | |
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timings[4] | timings[5] | timings[6]; |
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writel(timings[0], pl353_smc_base + PL353_SMC_SET_CYCLES_OFFS); |
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writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base + |
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PL353_SMC_DIRECT_CMD_OFFS); |
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} |
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EXPORT_SYMBOL_GPL(pl353_smc_set_cycles); |
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/** |
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* pl353_smc_ecc_is_busy - Read ecc busy flag |
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* Return: the ecc_status bit from the ecc_status register. 1 = busy, 0 = idle |
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*/ |
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bool pl353_smc_ecc_is_busy(void) |
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{ |
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return ((readl(pl353_smc_base + PL353_SMC_ECC_STATUS_OFFS) & |
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PL353_SMC_ECC_STATUS_BUSY) == PL353_SMC_ECC_STATUS_BUSY); |
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} |
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EXPORT_SYMBOL_GPL(pl353_smc_ecc_is_busy); |
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/** |
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* pl353_smc_get_ecc_val - Read ecc_valueN registers |
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* @ecc_reg: Index of the ecc_value reg (0..3) |
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* Return: the content of the requested ecc_value register. |
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* |
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* There are four valid ecc_value registers. The argument is truncated to stay |
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* within this valid boundary. |
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*/ |
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u32 pl353_smc_get_ecc_val(int ecc_reg) |
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{ |
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u32 addr, reg; |
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addr = PL353_SMC_ECC_VALUE0_OFFS + |
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(ecc_reg * PL353_SMC_ECC_REG_SIZE_OFFS); |
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reg = readl(pl353_smc_base + addr); |
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return reg; |
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} |
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EXPORT_SYMBOL_GPL(pl353_smc_get_ecc_val); |
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/** |
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* pl353_smc_get_nand_int_status_raw - Get NAND interrupt status bit |
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* Return: the raw_int_status1 bit from the memc_status register |
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*/ |
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int pl353_smc_get_nand_int_status_raw(void) |
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{ |
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u32 reg; |
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reg = readl(pl353_smc_base + PL353_SMC_MEMC_STATUS_OFFS); |
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reg >>= PL353_SMC_MEMC_STATUS_RAW_INT_1_SHIFT; |
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reg &= 1; |
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return reg; |
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} |
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EXPORT_SYMBOL_GPL(pl353_smc_get_nand_int_status_raw); |
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/** |
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* pl353_smc_clr_nand_int - Clear NAND interrupt |
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*/ |
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void pl353_smc_clr_nand_int(void) |
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{ |
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writel(PL353_SMC_CFG_CLR_INT_CLR_1, |
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pl353_smc_base + PL353_SMC_CFG_CLR_OFFS); |
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} |
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EXPORT_SYMBOL_GPL(pl353_smc_clr_nand_int); |
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/** |
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* pl353_smc_set_ecc_mode - Set SMC ECC mode |
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* @mode: ECC mode (BYPASS, APB, MEM) |
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* Return: 0 on success or negative errno. |
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*/ |
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int pl353_smc_set_ecc_mode(enum pl353_smc_ecc_mode mode) |
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{ |
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u32 reg; |
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int ret = 0; |
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switch (mode) { |
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case PL353_SMC_ECCMODE_BYPASS: |
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case PL353_SMC_ECCMODE_APB: |
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case PL353_SMC_ECCMODE_MEM: |
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reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS); |
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reg &= ~PL353_SMC_ECC_MEMCFG_MODE_MASK; |
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reg |= mode << PL353_SMC_ECC_MEMCFG_MODE_SHIFT; |
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writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS); |
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break; |
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default: |
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ret = -EINVAL; |
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} |
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return ret; |
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} |
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EXPORT_SYMBOL_GPL(pl353_smc_set_ecc_mode); |
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/** |
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* pl353_smc_set_ecc_pg_size - Set SMC ECC page size |
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* @pg_sz: ECC page size |
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* Return: 0 on success or negative errno. |
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*/ |
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int pl353_smc_set_ecc_pg_size(unsigned int pg_sz) |
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{ |
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u32 reg, sz; |
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switch (pg_sz) { |
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case 0: |
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sz = 0; |
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break; |
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case SZ_512: |
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sz = 1; |
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break; |
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case SZ_1K: |
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sz = 2; |
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break; |
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case SZ_2K: |
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sz = 3; |
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break; |
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default: |
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return -EINVAL; |
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} |
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reg = readl(pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS); |
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reg &= ~PL353_SMC_ECC_MEMCFG_PGSIZE_MASK; |
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reg |= sz; |
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writel(reg, pl353_smc_base + PL353_SMC_ECC_MEMCFG_OFFS); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(pl353_smc_set_ecc_pg_size); |
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static int __maybe_unused pl353_smc_suspend(struct device *dev) |
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{ |
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struct pl353_smc_data *pl353_smc = dev_get_drvdata(dev); |
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clk_disable(pl353_smc->memclk); |
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clk_disable(pl353_smc->aclk); |
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return 0; |
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} |
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static int __maybe_unused pl353_smc_resume(struct device *dev) |
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{ |
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int ret; |
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struct pl353_smc_data *pl353_smc = dev_get_drvdata(dev); |
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ret = clk_enable(pl353_smc->aclk); |
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if (ret) { |
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dev_err(dev, "Cannot enable axi domain clock.\n"); |
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return ret; |
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} |
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ret = clk_enable(pl353_smc->memclk); |
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if (ret) { |
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dev_err(dev, "Cannot enable memory clock.\n"); |
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clk_disable(pl353_smc->aclk); |
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return ret; |
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} |
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return ret; |
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} |
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static struct amba_driver pl353_smc_driver; |
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static SIMPLE_DEV_PM_OPS(pl353_smc_dev_pm_ops, pl353_smc_suspend, |
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pl353_smc_resume); |
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/** |
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* pl353_smc_init_nand_interface - Initialize the NAND interface |
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* @adev: Pointer to the amba_device struct |
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* @nand_node: Pointer to the pl353_nand device_node struct |
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*/ |
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static void pl353_smc_init_nand_interface(struct amba_device *adev, |
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struct device_node *nand_node) |
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{ |
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unsigned long timeout; |
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pl353_smc_set_buswidth(PL353_SMC_MEM_WIDTH_8); |
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writel(PL353_SMC_CFG_CLR_INT_CLR_1, |
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pl353_smc_base + PL353_SMC_CFG_CLR_OFFS); |
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writel(PL353_SMC_DC_UPT_NAND_REGS, pl353_smc_base + |
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PL353_SMC_DIRECT_CMD_OFFS); |
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timeout = jiffies + PL353_NAND_ECC_BUSY_TIMEOUT; |
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/* Wait till the ECC operation is complete */ |
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do { |
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if (pl353_smc_ecc_is_busy()) |
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cpu_relax(); |
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else |
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break; |
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} while (!time_after_eq(jiffies, timeout)); |
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if (time_after_eq(jiffies, timeout)) |
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return; |
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writel(PL353_NAND_ECC_CMD1, |
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pl353_smc_base + PL353_SMC_ECC_MEMCMD1_OFFS); |
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writel(PL353_NAND_ECC_CMD2, |
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pl353_smc_base + PL353_SMC_ECC_MEMCMD2_OFFS); |
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} |
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static const struct of_device_id pl353_smc_supported_children[] = { |
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{ |
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.compatible = "cfi-flash" |
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}, |
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{ |
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.compatible = "arm,pl353-nand-r2p1", |
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.data = pl353_smc_init_nand_interface |
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}, |
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{} |
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}; |
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static int pl353_smc_probe(struct amba_device *adev, const struct amba_id *id) |
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{ |
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struct pl353_smc_data *pl353_smc; |
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struct device_node *child; |
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struct resource *res; |
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int err; |
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struct device_node *of_node = adev->dev.of_node; |
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static void (*init)(struct amba_device *adev, |
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struct device_node *nand_node); |
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const struct of_device_id *match = NULL; |
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pl353_smc = devm_kzalloc(&adev->dev, sizeof(*pl353_smc), GFP_KERNEL); |
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if (!pl353_smc) |
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return -ENOMEM; |
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/* Get the NAND controller virtual address */ |
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res = &adev->res; |
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pl353_smc_base = devm_ioremap_resource(&adev->dev, res); |
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if (IS_ERR(pl353_smc_base)) |
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return PTR_ERR(pl353_smc_base); |
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pl353_smc->aclk = devm_clk_get(&adev->dev, "apb_pclk"); |
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if (IS_ERR(pl353_smc->aclk)) { |
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dev_err(&adev->dev, "aclk clock not found.\n"); |
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return PTR_ERR(pl353_smc->aclk); |
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} |
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pl353_smc->memclk = devm_clk_get(&adev->dev, "memclk"); |
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if (IS_ERR(pl353_smc->memclk)) { |
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dev_err(&adev->dev, "memclk clock not found.\n"); |
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return PTR_ERR(pl353_smc->memclk); |
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} |
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err = clk_prepare_enable(pl353_smc->aclk); |
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if (err) { |
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dev_err(&adev->dev, "Unable to enable AXI clock.\n"); |
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return err; |
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} |
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err = clk_prepare_enable(pl353_smc->memclk); |
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if (err) { |
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dev_err(&adev->dev, "Unable to enable memory clock.\n"); |
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goto out_clk_dis_aper; |
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} |
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amba_set_drvdata(adev, pl353_smc); |
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/* clear interrupts */ |
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writel(PL353_SMC_CFG_CLR_DEFAULT_MASK, |
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pl353_smc_base + PL353_SMC_CFG_CLR_OFFS); |
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/* Find compatible children. Only a single child is supported */ |
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for_each_available_child_of_node(of_node, child) { |
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match = of_match_node(pl353_smc_supported_children, child); |
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if (!match) { |
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dev_warn(&adev->dev, "unsupported child node\n"); |
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continue; |
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} |
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break; |
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} |
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if (!match) { |
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err = -ENODEV; |
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dev_err(&adev->dev, "no matching children\n"); |
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goto out_clk_disable; |
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} |
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init = match->data; |
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if (init) |
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init(adev, child); |
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of_platform_device_create(child, NULL, &adev->dev); |
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return 0; |
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out_clk_disable: |
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clk_disable_unprepare(pl353_smc->memclk); |
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out_clk_dis_aper: |
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clk_disable_unprepare(pl353_smc->aclk); |
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return err; |
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} |
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static int pl353_smc_remove(struct amba_device *adev) |
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{ |
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struct pl353_smc_data *pl353_smc = amba_get_drvdata(adev); |
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clk_disable_unprepare(pl353_smc->memclk); |
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clk_disable_unprepare(pl353_smc->aclk); |
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return 0; |
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} |
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static const struct amba_id pl353_ids[] = { |
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{ |
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.id = 0x00041353, |
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.mask = 0x000fffff, |
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}, |
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{ 0, 0 }, |
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}; |
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MODULE_DEVICE_TABLE(amba, pl353_ids); |
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static struct amba_driver pl353_smc_driver = { |
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.drv = { |
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.owner = THIS_MODULE, |
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.name = "pl353-smc", |
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.pm = &pl353_smc_dev_pm_ops, |
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}, |
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.id_table = pl353_ids, |
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.probe = pl353_smc_probe, |
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.remove = pl353_smc_remove, |
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}; |
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module_amba_driver(pl353_smc_driver); |
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MODULE_AUTHOR("Xilinx, Inc."); |
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MODULE_DESCRIPTION("ARM PL353 SMC Driver"); |
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MODULE_LICENSE("GPL");
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