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281 lines
6.4 KiB
281 lines
6.4 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/module.h> |
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#include <linux/irqdomain.h> |
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#include <linux/irqchip.h> |
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#include <linux/irq.h> |
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#include <linux/interrupt.h> |
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#include <linux/smp.h> |
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#include <linux/io.h> |
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#include <asm/irq.h> |
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#include <asm/traps.h> |
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#include <asm/reg_ops.h> |
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static struct irq_domain *root_domain; |
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static void __iomem *INTCG_base; |
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static void __iomem *INTCL_base; |
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#define IPI_IRQ 15 |
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#define INTC_IRQS 256 |
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#define COMM_IRQ_BASE 32 |
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#define INTCG_SIZE 0x8000 |
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#define INTCL_SIZE 0x1000 |
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#define INTCG_ICTLR 0x0 |
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#define INTCG_CICFGR 0x100 |
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#define INTCG_CIDSTR 0x1000 |
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#define INTCL_PICTLR 0x0 |
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#define INTCL_CFGR 0x14 |
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#define INTCL_SIGR 0x60 |
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#define INTCL_RDYIR 0x6c |
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#define INTCL_SENR 0xa0 |
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#define INTCL_CENR 0xa4 |
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#define INTCL_CACR 0xb4 |
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static DEFINE_PER_CPU(void __iomem *, intcl_reg); |
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static unsigned long *__trigger; |
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#define IRQ_OFFSET(irq) ((irq < COMM_IRQ_BASE) ? irq : (irq - COMM_IRQ_BASE)) |
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#define TRIG_BYTE_OFFSET(i) ((((i) * 2) / 32) * 4) |
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#define TRIG_BIT_OFFSET(i) (((i) * 2) % 32) |
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#define TRIG_VAL(trigger, irq) (trigger << TRIG_BIT_OFFSET(IRQ_OFFSET(irq))) |
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#define TRIG_VAL_MSK(irq) (~(3 << TRIG_BIT_OFFSET(IRQ_OFFSET(irq)))) |
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#define TRIG_BASE(irq) \ |
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(TRIG_BYTE_OFFSET(IRQ_OFFSET(irq)) + ((irq < COMM_IRQ_BASE) ? \ |
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(this_cpu_read(intcl_reg) + INTCL_CFGR) : (INTCG_base + INTCG_CICFGR))) |
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static DEFINE_SPINLOCK(setup_lock); |
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static void setup_trigger(unsigned long irq, unsigned long trigger) |
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{ |
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unsigned int tmp; |
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spin_lock(&setup_lock); |
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/* setup trigger */ |
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tmp = readl_relaxed(TRIG_BASE(irq)) & TRIG_VAL_MSK(irq); |
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writel_relaxed(tmp | TRIG_VAL(trigger, irq), TRIG_BASE(irq)); |
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spin_unlock(&setup_lock); |
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} |
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static void csky_mpintc_handler(struct pt_regs *regs) |
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{ |
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void __iomem *reg_base = this_cpu_read(intcl_reg); |
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handle_domain_irq(root_domain, |
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readl_relaxed(reg_base + INTCL_RDYIR), regs); |
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} |
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static void csky_mpintc_enable(struct irq_data *d) |
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{ |
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void __iomem *reg_base = this_cpu_read(intcl_reg); |
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setup_trigger(d->hwirq, __trigger[d->hwirq]); |
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writel_relaxed(d->hwirq, reg_base + INTCL_SENR); |
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} |
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static void csky_mpintc_disable(struct irq_data *d) |
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{ |
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void __iomem *reg_base = this_cpu_read(intcl_reg); |
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writel_relaxed(d->hwirq, reg_base + INTCL_CENR); |
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} |
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static void csky_mpintc_eoi(struct irq_data *d) |
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{ |
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void __iomem *reg_base = this_cpu_read(intcl_reg); |
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writel_relaxed(d->hwirq, reg_base + INTCL_CACR); |
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} |
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static int csky_mpintc_set_type(struct irq_data *d, unsigned int type) |
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{ |
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switch (type & IRQ_TYPE_SENSE_MASK) { |
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case IRQ_TYPE_LEVEL_HIGH: |
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__trigger[d->hwirq] = 0; |
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break; |
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case IRQ_TYPE_LEVEL_LOW: |
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__trigger[d->hwirq] = 1; |
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break; |
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case IRQ_TYPE_EDGE_RISING: |
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__trigger[d->hwirq] = 2; |
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break; |
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case IRQ_TYPE_EDGE_FALLING: |
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__trigger[d->hwirq] = 3; |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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#ifdef CONFIG_SMP |
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static int csky_irq_set_affinity(struct irq_data *d, |
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const struct cpumask *mask_val, |
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bool force) |
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{ |
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unsigned int cpu; |
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unsigned int offset = 4 * (d->hwirq - COMM_IRQ_BASE); |
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if (!force) |
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cpu = cpumask_any_and(mask_val, cpu_online_mask); |
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else |
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cpu = cpumask_first(mask_val); |
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if (cpu >= nr_cpu_ids) |
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return -EINVAL; |
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/* |
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* The csky,mpintc could support auto irq deliver, but it only |
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* could deliver external irq to one cpu or all cpus. So it |
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* doesn't support deliver external irq to a group of cpus |
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* with cpu_mask. |
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* SO we only use auto deliver mode when affinity mask_val is |
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* equal to cpu_present_mask. |
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* |
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*/ |
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if (cpumask_equal(mask_val, cpu_present_mask)) |
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cpu = 0; |
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else |
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cpu |= BIT(31); |
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writel_relaxed(cpu, INTCG_base + INTCG_CIDSTR + offset); |
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irq_data_update_effective_affinity(d, cpumask_of(cpu)); |
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return IRQ_SET_MASK_OK_DONE; |
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} |
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#endif |
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static struct irq_chip csky_irq_chip = { |
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.name = "C-SKY SMP Intc", |
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.irq_eoi = csky_mpintc_eoi, |
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.irq_enable = csky_mpintc_enable, |
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.irq_disable = csky_mpintc_disable, |
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.irq_set_type = csky_mpintc_set_type, |
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#ifdef CONFIG_SMP |
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.irq_set_affinity = csky_irq_set_affinity, |
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#endif |
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}; |
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static int csky_irqdomain_map(struct irq_domain *d, unsigned int irq, |
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irq_hw_number_t hwirq) |
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{ |
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if (hwirq < COMM_IRQ_BASE) { |
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irq_set_percpu_devid(irq); |
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irq_set_chip_and_handler(irq, &csky_irq_chip, |
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handle_percpu_irq); |
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} else { |
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irq_set_chip_and_handler(irq, &csky_irq_chip, |
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handle_fasteoi_irq); |
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} |
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return 0; |
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} |
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static int csky_irq_domain_xlate_cells(struct irq_domain *d, |
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struct device_node *ctrlr, const u32 *intspec, |
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unsigned int intsize, unsigned long *out_hwirq, |
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unsigned int *out_type) |
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{ |
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if (WARN_ON(intsize < 1)) |
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return -EINVAL; |
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*out_hwirq = intspec[0]; |
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if (intsize > 1) |
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*out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; |
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else |
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*out_type = IRQ_TYPE_LEVEL_HIGH; |
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return 0; |
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} |
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static const struct irq_domain_ops csky_irqdomain_ops = { |
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.map = csky_irqdomain_map, |
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.xlate = csky_irq_domain_xlate_cells, |
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}; |
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#ifdef CONFIG_SMP |
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static void csky_mpintc_send_ipi(const struct cpumask *mask) |
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{ |
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void __iomem *reg_base = this_cpu_read(intcl_reg); |
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/* |
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* INTCL_SIGR[3:0] INTID |
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* INTCL_SIGR[8:15] CPUMASK |
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*/ |
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writel_relaxed((*cpumask_bits(mask)) << 8 | IPI_IRQ, |
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reg_base + INTCL_SIGR); |
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} |
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#endif |
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/* C-SKY multi processor interrupt controller */ |
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static int __init |
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csky_mpintc_init(struct device_node *node, struct device_node *parent) |
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{ |
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int ret; |
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unsigned int cpu, nr_irq; |
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#ifdef CONFIG_SMP |
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unsigned int ipi_irq; |
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#endif |
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if (parent) |
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return 0; |
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ret = of_property_read_u32(node, "csky,num-irqs", &nr_irq); |
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if (ret < 0) |
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nr_irq = INTC_IRQS; |
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__trigger = kcalloc(nr_irq, sizeof(unsigned long), GFP_KERNEL); |
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if (__trigger == NULL) |
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return -ENXIO; |
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if (INTCG_base == NULL) { |
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INTCG_base = ioremap(mfcr("cr<31, 14>"), |
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INTCL_SIZE*nr_cpu_ids + INTCG_SIZE); |
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if (INTCG_base == NULL) |
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return -EIO; |
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INTCL_base = INTCG_base + INTCG_SIZE; |
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writel_relaxed(BIT(0), INTCG_base + INTCG_ICTLR); |
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} |
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root_domain = irq_domain_add_linear(node, nr_irq, &csky_irqdomain_ops, |
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NULL); |
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if (!root_domain) |
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return -ENXIO; |
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/* for every cpu */ |
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for_each_present_cpu(cpu) { |
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per_cpu(intcl_reg, cpu) = INTCL_base + (INTCL_SIZE * cpu); |
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writel_relaxed(BIT(0), per_cpu(intcl_reg, cpu) + INTCL_PICTLR); |
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} |
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set_handle_irq(&csky_mpintc_handler); |
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#ifdef CONFIG_SMP |
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ipi_irq = irq_create_mapping(root_domain, IPI_IRQ); |
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if (!ipi_irq) |
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return -EIO; |
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set_send_ipi(&csky_mpintc_send_ipi, ipi_irq); |
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#endif |
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return 0; |
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} |
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IRQCHIP_DECLARE(csky_mpintc, "csky,mpintc", csky_mpintc_init);
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