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363 lines
9.2 KiB
363 lines
9.2 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Broadcom BCM6345 style Level 1 interrupt controller driver |
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* |
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* Copyright (C) 2014 Broadcom Corporation |
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* Copyright 2015 Simon Arlott |
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* |
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* This is based on the BCM7038 (which supports SMP) but with a single |
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* enable register instead of separate mask/set/clear registers. |
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* |
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* The BCM3380 has a similar mask/status register layout, but each pair |
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* of words is at separate locations (and SMP is not supported). |
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* |
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* ENABLE/STATUS words are packed next to each other for each CPU: |
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* |
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* BCM6368: |
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* 0x1000_0020: CPU0_W0_ENABLE |
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* 0x1000_0024: CPU0_W1_ENABLE |
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* 0x1000_0028: CPU0_W0_STATUS IRQs 31-63 |
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* 0x1000_002c: CPU0_W1_STATUS IRQs 0-31 |
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* 0x1000_0030: CPU1_W0_ENABLE |
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* 0x1000_0034: CPU1_W1_ENABLE |
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* 0x1000_0038: CPU1_W0_STATUS IRQs 31-63 |
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* 0x1000_003c: CPU1_W1_STATUS IRQs 0-31 |
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* |
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* BCM63168: |
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* 0x1000_0020: CPU0_W0_ENABLE |
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* 0x1000_0024: CPU0_W1_ENABLE |
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* 0x1000_0028: CPU0_W2_ENABLE |
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* 0x1000_002c: CPU0_W3_ENABLE |
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* 0x1000_0030: CPU0_W0_STATUS IRQs 96-127 |
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* 0x1000_0034: CPU0_W1_STATUS IRQs 64-95 |
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* 0x1000_0038: CPU0_W2_STATUS IRQs 32-63 |
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* 0x1000_003c: CPU0_W3_STATUS IRQs 0-31 |
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* 0x1000_0040: CPU1_W0_ENABLE |
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* 0x1000_0044: CPU1_W1_ENABLE |
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* 0x1000_0048: CPU1_W2_ENABLE |
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* 0x1000_004c: CPU1_W3_ENABLE |
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* 0x1000_0050: CPU1_W0_STATUS IRQs 96-127 |
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* 0x1000_0054: CPU1_W1_STATUS IRQs 64-95 |
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* 0x1000_0058: CPU1_W2_STATUS IRQs 32-63 |
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* 0x1000_005c: CPU1_W3_STATUS IRQs 0-31 |
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* |
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* IRQs are numbered in CPU native endian order |
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* (which is big-endian in these examples) |
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*/ |
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/bitops.h> |
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#include <linux/cpumask.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/ioport.h> |
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#include <linux/irq.h> |
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#include <linux/irqdomain.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_address.h> |
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#include <linux/of_platform.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/smp.h> |
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#include <linux/types.h> |
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#include <linux/irqchip.h> |
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#include <linux/irqchip/chained_irq.h> |
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#define IRQS_PER_WORD 32 |
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#define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 2) |
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struct bcm6345_l1_cpu; |
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struct bcm6345_l1_chip { |
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raw_spinlock_t lock; |
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unsigned int n_words; |
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struct irq_domain *domain; |
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struct cpumask cpumask; |
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struct bcm6345_l1_cpu *cpus[NR_CPUS]; |
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}; |
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struct bcm6345_l1_cpu { |
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void __iomem *map_base; |
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unsigned int parent_irq; |
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u32 enable_cache[]; |
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}; |
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static inline unsigned int reg_enable(struct bcm6345_l1_chip *intc, |
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unsigned int word) |
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{ |
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#ifdef __BIG_ENDIAN |
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return (1 * intc->n_words - word - 1) * sizeof(u32); |
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#else |
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return (0 * intc->n_words + word) * sizeof(u32); |
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#endif |
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} |
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static inline unsigned int reg_status(struct bcm6345_l1_chip *intc, |
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unsigned int word) |
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{ |
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#ifdef __BIG_ENDIAN |
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return (2 * intc->n_words - word - 1) * sizeof(u32); |
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#else |
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return (1 * intc->n_words + word) * sizeof(u32); |
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#endif |
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} |
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static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc, |
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struct irq_data *d) |
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{ |
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return cpumask_first_and(&intc->cpumask, irq_data_get_affinity_mask(d)); |
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} |
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static void bcm6345_l1_irq_handle(struct irq_desc *desc) |
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{ |
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struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc); |
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struct bcm6345_l1_cpu *cpu; |
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struct irq_chip *chip = irq_desc_get_chip(desc); |
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unsigned int idx; |
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#ifdef CONFIG_SMP |
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cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; |
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#else |
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cpu = intc->cpus[0]; |
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#endif |
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chained_irq_enter(chip, desc); |
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for (idx = 0; idx < intc->n_words; idx++) { |
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int base = idx * IRQS_PER_WORD; |
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unsigned long pending; |
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irq_hw_number_t hwirq; |
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unsigned int irq; |
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pending = __raw_readl(cpu->map_base + reg_status(intc, idx)); |
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pending &= __raw_readl(cpu->map_base + reg_enable(intc, idx)); |
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for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) { |
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irq = irq_linear_revmap(intc->domain, base + hwirq); |
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if (irq) |
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do_IRQ(irq); |
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else |
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spurious_interrupt(); |
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} |
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} |
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chained_irq_exit(chip, desc); |
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} |
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static inline void __bcm6345_l1_unmask(struct irq_data *d) |
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{ |
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struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); |
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u32 word = d->hwirq / IRQS_PER_WORD; |
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u32 mask = BIT(d->hwirq % IRQS_PER_WORD); |
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unsigned int cpu_idx = cpu_for_irq(intc, d); |
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intc->cpus[cpu_idx]->enable_cache[word] |= mask; |
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__raw_writel(intc->cpus[cpu_idx]->enable_cache[word], |
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intc->cpus[cpu_idx]->map_base + reg_enable(intc, word)); |
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} |
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static inline void __bcm6345_l1_mask(struct irq_data *d) |
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{ |
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struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); |
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u32 word = d->hwirq / IRQS_PER_WORD; |
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u32 mask = BIT(d->hwirq % IRQS_PER_WORD); |
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unsigned int cpu_idx = cpu_for_irq(intc, d); |
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intc->cpus[cpu_idx]->enable_cache[word] &= ~mask; |
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__raw_writel(intc->cpus[cpu_idx]->enable_cache[word], |
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intc->cpus[cpu_idx]->map_base + reg_enable(intc, word)); |
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} |
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static void bcm6345_l1_unmask(struct irq_data *d) |
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{ |
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struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); |
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unsigned long flags; |
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raw_spin_lock_irqsave(&intc->lock, flags); |
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__bcm6345_l1_unmask(d); |
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raw_spin_unlock_irqrestore(&intc->lock, flags); |
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} |
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static void bcm6345_l1_mask(struct irq_data *d) |
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{ |
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struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); |
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unsigned long flags; |
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raw_spin_lock_irqsave(&intc->lock, flags); |
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__bcm6345_l1_mask(d); |
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raw_spin_unlock_irqrestore(&intc->lock, flags); |
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} |
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static int bcm6345_l1_set_affinity(struct irq_data *d, |
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const struct cpumask *dest, |
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bool force) |
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{ |
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struct bcm6345_l1_chip *intc = irq_data_get_irq_chip_data(d); |
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u32 word = d->hwirq / IRQS_PER_WORD; |
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u32 mask = BIT(d->hwirq % IRQS_PER_WORD); |
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unsigned int old_cpu = cpu_for_irq(intc, d); |
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unsigned int new_cpu; |
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struct cpumask valid; |
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unsigned long flags; |
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bool enabled; |
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if (!cpumask_and(&valid, &intc->cpumask, dest)) |
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return -EINVAL; |
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new_cpu = cpumask_any_and(&valid, cpu_online_mask); |
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if (new_cpu >= nr_cpu_ids) |
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return -EINVAL; |
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dest = cpumask_of(new_cpu); |
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raw_spin_lock_irqsave(&intc->lock, flags); |
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if (old_cpu != new_cpu) { |
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enabled = intc->cpus[old_cpu]->enable_cache[word] & mask; |
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if (enabled) |
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__bcm6345_l1_mask(d); |
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cpumask_copy(irq_data_get_affinity_mask(d), dest); |
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if (enabled) |
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__bcm6345_l1_unmask(d); |
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} else { |
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cpumask_copy(irq_data_get_affinity_mask(d), dest); |
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} |
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raw_spin_unlock_irqrestore(&intc->lock, flags); |
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irq_data_update_effective_affinity(d, cpumask_of(new_cpu)); |
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return IRQ_SET_MASK_OK_NOCOPY; |
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} |
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static int __init bcm6345_l1_init_one(struct device_node *dn, |
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unsigned int idx, |
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struct bcm6345_l1_chip *intc) |
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{ |
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struct resource res; |
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resource_size_t sz; |
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struct bcm6345_l1_cpu *cpu; |
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unsigned int i, n_words; |
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if (of_address_to_resource(dn, idx, &res)) |
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return -EINVAL; |
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sz = resource_size(&res); |
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n_words = sz / REG_BYTES_PER_IRQ_WORD; |
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if (!intc->n_words) |
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intc->n_words = n_words; |
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else if (intc->n_words != n_words) |
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return -EINVAL; |
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cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32), |
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GFP_KERNEL); |
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if (!cpu) |
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return -ENOMEM; |
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cpu->map_base = ioremap(res.start, sz); |
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if (!cpu->map_base) |
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return -ENOMEM; |
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for (i = 0; i < n_words; i++) { |
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cpu->enable_cache[i] = 0; |
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__raw_writel(0, cpu->map_base + reg_enable(intc, i)); |
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} |
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cpu->parent_irq = irq_of_parse_and_map(dn, idx); |
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if (!cpu->parent_irq) { |
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pr_err("failed to map parent interrupt %d\n", cpu->parent_irq); |
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return -EINVAL; |
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} |
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irq_set_chained_handler_and_data(cpu->parent_irq, |
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bcm6345_l1_irq_handle, intc); |
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return 0; |
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} |
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static struct irq_chip bcm6345_l1_irq_chip = { |
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.name = "bcm6345-l1", |
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.irq_mask = bcm6345_l1_mask, |
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.irq_unmask = bcm6345_l1_unmask, |
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.irq_set_affinity = bcm6345_l1_set_affinity, |
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}; |
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static int bcm6345_l1_map(struct irq_domain *d, unsigned int virq, |
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irq_hw_number_t hw_irq) |
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{ |
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irq_set_chip_and_handler(virq, |
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&bcm6345_l1_irq_chip, handle_percpu_irq); |
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irq_set_chip_data(virq, d->host_data); |
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irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq))); |
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return 0; |
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} |
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static const struct irq_domain_ops bcm6345_l1_domain_ops = { |
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.xlate = irq_domain_xlate_onecell, |
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.map = bcm6345_l1_map, |
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}; |
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static int __init bcm6345_l1_of_init(struct device_node *dn, |
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struct device_node *parent) |
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{ |
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struct bcm6345_l1_chip *intc; |
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unsigned int idx; |
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int ret; |
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intc = kzalloc(sizeof(*intc), GFP_KERNEL); |
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if (!intc) |
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return -ENOMEM; |
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for_each_possible_cpu(idx) { |
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ret = bcm6345_l1_init_one(dn, idx, intc); |
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if (ret) |
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pr_err("failed to init intc L1 for cpu %d: %d\n", |
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idx, ret); |
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else |
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cpumask_set_cpu(idx, &intc->cpumask); |
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} |
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if (!cpumask_weight(&intc->cpumask)) { |
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ret = -ENODEV; |
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goto out_free; |
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} |
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raw_spin_lock_init(&intc->lock); |
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intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words, |
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&bcm6345_l1_domain_ops, |
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intc); |
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if (!intc->domain) { |
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ret = -ENOMEM; |
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goto out_unmap; |
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} |
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pr_info("registered BCM6345 L1 intc (IRQs: %d)\n", |
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IRQS_PER_WORD * intc->n_words); |
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for_each_cpu(idx, &intc->cpumask) { |
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struct bcm6345_l1_cpu *cpu = intc->cpus[idx]; |
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pr_info(" CPU%u at MMIO 0x%p (irq = %d)\n", idx, |
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cpu->map_base, cpu->parent_irq); |
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} |
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return 0; |
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out_unmap: |
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for_each_possible_cpu(idx) { |
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struct bcm6345_l1_cpu *cpu = intc->cpus[idx]; |
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if (cpu) { |
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if (cpu->map_base) |
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iounmap(cpu->map_base); |
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kfree(cpu); |
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} |
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} |
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out_free: |
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kfree(intc); |
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return ret; |
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} |
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IRQCHIP_DECLARE(bcm6345_l1, "brcm,bcm6345-l1-intc", bcm6345_l1_of_init);
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