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257 lines
6.1 KiB
257 lines
6.1 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* ICS backend for OPAL managed interrupts. |
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* |
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* Copyright 2011 IBM Corp. |
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*/ |
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//#define DEBUG |
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#include <linux/types.h> |
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#include <linux/kernel.h> |
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#include <linux/irq.h> |
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#include <linux/smp.h> |
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#include <linux/interrupt.h> |
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#include <linux/init.h> |
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#include <linux/cpu.h> |
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#include <linux/of.h> |
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#include <linux/spinlock.h> |
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#include <linux/msi.h> |
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#include <linux/list.h> |
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#include <asm/prom.h> |
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#include <asm/smp.h> |
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#include <asm/machdep.h> |
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#include <asm/irq.h> |
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#include <asm/errno.h> |
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#include <asm/xics.h> |
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#include <asm/opal.h> |
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#include <asm/firmware.h> |
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struct ics_native { |
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struct ics ics; |
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struct device_node *node; |
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void __iomem *base; |
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u32 ibase; |
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u32 icount; |
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}; |
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#define to_ics_native(_ics) container_of(_ics, struct ics_native, ics) |
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static void __iomem *ics_native_xive(struct ics_native *in, unsigned int vec) |
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{ |
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return in->base + 0x800 + ((vec - in->ibase) << 2); |
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} |
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static void ics_native_unmask_irq(struct irq_data *d) |
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{ |
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unsigned int vec = (unsigned int)irqd_to_hwirq(d); |
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struct ics *ics = irq_data_get_irq_chip_data(d); |
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struct ics_native *in = to_ics_native(ics); |
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unsigned int server; |
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pr_devel("ics-native: unmask virq %d [hw 0x%x]\n", d->irq, vec); |
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if (vec < in->ibase || vec >= (in->ibase + in->icount)) |
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return; |
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server = xics_get_irq_server(d->irq, irq_data_get_affinity_mask(d), 0); |
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out_be32(ics_native_xive(in, vec), (server << 8) | DEFAULT_PRIORITY); |
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} |
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static unsigned int ics_native_startup(struct irq_data *d) |
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{ |
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#ifdef CONFIG_PCI_MSI |
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/* |
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* The generic MSI code returns with the interrupt disabled on the |
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* card, using the MSI mask bits. Firmware doesn't appear to unmask |
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* at that level, so we do it here by hand. |
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*/ |
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if (irq_data_get_msi_desc(d)) |
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pci_msi_unmask_irq(d); |
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#endif |
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/* unmask it */ |
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ics_native_unmask_irq(d); |
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return 0; |
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} |
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static void ics_native_do_mask(struct ics_native *in, unsigned int vec) |
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{ |
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out_be32(ics_native_xive(in, vec), 0xff); |
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} |
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static void ics_native_mask_irq(struct irq_data *d) |
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{ |
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unsigned int vec = (unsigned int)irqd_to_hwirq(d); |
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struct ics *ics = irq_data_get_irq_chip_data(d); |
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struct ics_native *in = to_ics_native(ics); |
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pr_devel("ics-native: mask virq %d [hw 0x%x]\n", d->irq, vec); |
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if (vec < in->ibase || vec >= (in->ibase + in->icount)) |
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return; |
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ics_native_do_mask(in, vec); |
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} |
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static int ics_native_set_affinity(struct irq_data *d, |
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const struct cpumask *cpumask, |
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bool force) |
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{ |
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unsigned int vec = (unsigned int)irqd_to_hwirq(d); |
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struct ics *ics = irq_data_get_irq_chip_data(d); |
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struct ics_native *in = to_ics_native(ics); |
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int server; |
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u32 xive; |
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if (vec < in->ibase || vec >= (in->ibase + in->icount)) |
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return -EINVAL; |
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server = xics_get_irq_server(d->irq, cpumask, 1); |
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if (server == -1) { |
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pr_warn("%s: No online cpus in the mask %*pb for irq %d\n", |
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__func__, cpumask_pr_args(cpumask), d->irq); |
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return -1; |
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} |
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xive = in_be32(ics_native_xive(in, vec)); |
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xive = (xive & 0xff) | (server << 8); |
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out_be32(ics_native_xive(in, vec), xive); |
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return IRQ_SET_MASK_OK; |
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} |
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static struct irq_chip ics_native_irq_chip = { |
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.name = "ICS", |
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.irq_startup = ics_native_startup, |
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.irq_mask = ics_native_mask_irq, |
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.irq_unmask = ics_native_unmask_irq, |
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.irq_eoi = NULL, /* Patched at init time */ |
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.irq_set_affinity = ics_native_set_affinity, |
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.irq_set_type = xics_set_irq_type, |
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.irq_retrigger = xics_retrigger, |
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}; |
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static int ics_native_map(struct ics *ics, unsigned int virq) |
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{ |
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unsigned int vec = (unsigned int)virq_to_hw(virq); |
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struct ics_native *in = to_ics_native(ics); |
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pr_devel("%s: vec=0x%x\n", __func__, vec); |
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if (vec < in->ibase || vec >= (in->ibase + in->icount)) |
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return -EINVAL; |
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irq_set_chip_and_handler(virq, &ics_native_irq_chip, handle_fasteoi_irq); |
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irq_set_chip_data(virq, ics); |
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return 0; |
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} |
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static void ics_native_mask_unknown(struct ics *ics, unsigned long vec) |
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{ |
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struct ics_native *in = to_ics_native(ics); |
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if (vec < in->ibase || vec >= (in->ibase + in->icount)) |
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return; |
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ics_native_do_mask(in, vec); |
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} |
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static long ics_native_get_server(struct ics *ics, unsigned long vec) |
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{ |
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struct ics_native *in = to_ics_native(ics); |
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u32 xive; |
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if (vec < in->ibase || vec >= (in->ibase + in->icount)) |
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return -EINVAL; |
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xive = in_be32(ics_native_xive(in, vec)); |
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return (xive >> 8) & 0xfff; |
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} |
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static int ics_native_host_match(struct ics *ics, struct device_node *node) |
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{ |
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struct ics_native *in = to_ics_native(ics); |
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return in->node == node; |
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} |
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static struct ics ics_native_template = { |
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.map = ics_native_map, |
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.mask_unknown = ics_native_mask_unknown, |
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.get_server = ics_native_get_server, |
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.host_match = ics_native_host_match, |
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}; |
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static int __init ics_native_add_one(struct device_node *np) |
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{ |
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struct ics_native *ics; |
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u32 ranges[2]; |
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int rc, count; |
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ics = kzalloc(sizeof(struct ics_native), GFP_KERNEL); |
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if (!ics) |
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return -ENOMEM; |
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ics->node = of_node_get(np); |
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memcpy(&ics->ics, &ics_native_template, sizeof(struct ics)); |
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ics->base = of_iomap(np, 0); |
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if (!ics->base) { |
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pr_err("Failed to map %pOFP\n", np); |
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rc = -ENOMEM; |
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goto fail; |
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} |
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count = of_property_count_u32_elems(np, "interrupt-ranges"); |
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if (count < 2 || count & 1) { |
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pr_err("Failed to read interrupt-ranges of %pOFP\n", np); |
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rc = -EINVAL; |
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goto fail; |
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} |
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if (count > 2) { |
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pr_warn("ICS %pOFP has %d ranges, only one supported\n", |
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np, count >> 1); |
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} |
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rc = of_property_read_u32_array(np, "interrupt-ranges", |
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ranges, 2); |
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if (rc) { |
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pr_err("Failed to read interrupt-ranges of %pOFP\n", np); |
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goto fail; |
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} |
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ics->ibase = ranges[0]; |
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ics->icount = ranges[1]; |
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pr_info("ICS native initialized for sources %d..%d\n", |
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ics->ibase, ics->ibase + ics->icount - 1); |
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/* Register ourselves */ |
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xics_register_ics(&ics->ics); |
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return 0; |
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fail: |
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of_node_put(ics->node); |
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kfree(ics); |
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return rc; |
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} |
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int __init ics_native_init(void) |
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{ |
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struct device_node *ics; |
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bool found_one = false; |
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/* We need to patch our irq chip's EOI to point to the |
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* right ICP |
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*/ |
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ics_native_irq_chip.irq_eoi = icp_ops->eoi; |
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/* Find native ICS in the device-tree */ |
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for_each_compatible_node(ics, NULL, "openpower,xics-sources") { |
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if (ics_native_add_one(ics) == 0) |
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found_one = true; |
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} |
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if (found_one) |
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pr_info("ICS native backend registered\n"); |
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return found_one ? 0 : -ENODEV; |
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}
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