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356 lines
8.6 KiB
356 lines
8.6 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2001 Dave Engebretsen, IBM Corporation |
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* Copyright (C) 2003 Anton Blanchard <[email protected]>, IBM |
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* |
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* pSeries specific routines for PCI. |
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*/ |
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#include <linux/init.h> |
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#include <linux/ioport.h> |
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#include <linux/kernel.h> |
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#include <linux/pci.h> |
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#include <linux/string.h> |
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#include <asm/eeh.h> |
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#include <asm/pci-bridge.h> |
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#include <asm/prom.h> |
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#include <asm/ppc-pci.h> |
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#include <asm/pci.h> |
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#include "pseries.h" |
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#if 0 |
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void pcibios_name_device(struct pci_dev *dev) |
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{ |
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struct device_node *dn; |
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|
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/* |
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* Add IBM loc code (slot) as a prefix to the device names for service |
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*/ |
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dn = pci_device_to_OF_node(dev); |
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if (dn) { |
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const char *loc_code = of_get_property(dn, "ibm,loc-code", |
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NULL); |
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if (loc_code) { |
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int loc_len = strlen(loc_code); |
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if (loc_len < sizeof(dev->dev.name)) { |
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memmove(dev->dev.name+loc_len+1, dev->dev.name, |
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sizeof(dev->dev.name)-loc_len-1); |
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memcpy(dev->dev.name, loc_code, loc_len); |
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dev->dev.name[loc_len] = ' '; |
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dev->dev.name[sizeof(dev->dev.name)-1] = '\0'; |
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} |
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} |
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} |
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} |
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_name_device); |
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#endif |
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#ifdef CONFIG_PCI_IOV |
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#define MAX_VFS_FOR_MAP_PE 256 |
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struct pe_map_bar_entry { |
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__be64 bar; /* Input: Virtual Function BAR */ |
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__be16 rid; /* Input: Virtual Function Router ID */ |
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__be16 pe_num; /* Output: Virtual Function PE Number */ |
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__be32 reserved; /* Reserved Space */ |
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}; |
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int pseries_send_map_pe(struct pci_dev *pdev, |
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u16 num_vfs, |
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struct pe_map_bar_entry *vf_pe_array) |
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{ |
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struct pci_dn *pdn; |
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int rc; |
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unsigned long buid, addr; |
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int ibm_map_pes = rtas_token("ibm,open-sriov-map-pe-number"); |
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if (ibm_map_pes == RTAS_UNKNOWN_SERVICE) |
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return -EINVAL; |
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pdn = pci_get_pdn(pdev); |
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addr = rtas_config_addr(pdn->busno, pdn->devfn, 0); |
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buid = pdn->phb->buid; |
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spin_lock(&rtas_data_buf_lock); |
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memcpy(rtas_data_buf, vf_pe_array, |
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RTAS_DATA_BUF_SIZE); |
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rc = rtas_call(ibm_map_pes, 5, 1, NULL, addr, |
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BUID_HI(buid), BUID_LO(buid), |
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rtas_data_buf, |
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num_vfs * sizeof(struct pe_map_bar_entry)); |
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memcpy(vf_pe_array, rtas_data_buf, RTAS_DATA_BUF_SIZE); |
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spin_unlock(&rtas_data_buf_lock); |
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if (rc) |
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dev_err(&pdev->dev, |
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"%s: Failed to associate pes PE#%lx, rc=%x\n", |
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__func__, addr, rc); |
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return rc; |
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} |
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void pseries_set_pe_num(struct pci_dev *pdev, u16 vf_index, __be16 pe_num) |
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{ |
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struct pci_dn *pdn; |
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pdn = pci_get_pdn(pdev); |
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pdn->pe_num_map[vf_index] = be16_to_cpu(pe_num); |
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dev_dbg(&pdev->dev, "VF %04x:%02x:%02x.%x associated with PE#%x\n", |
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pci_domain_nr(pdev->bus), |
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pdev->bus->number, |
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PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)), |
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PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), |
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pdn->pe_num_map[vf_index]); |
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} |
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int pseries_associate_pes(struct pci_dev *pdev, u16 num_vfs) |
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{ |
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struct pci_dn *pdn; |
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int i, rc, vf_index; |
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struct pe_map_bar_entry *vf_pe_array; |
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struct resource *res; |
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u64 size; |
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vf_pe_array = kzalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL); |
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if (!vf_pe_array) |
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return -ENOMEM; |
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pdn = pci_get_pdn(pdev); |
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/* create firmware structure to associate pes */ |
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for (vf_index = 0; vf_index < num_vfs; vf_index++) { |
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pdn->pe_num_map[vf_index] = IODA_INVALID_PE; |
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for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { |
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res = &pdev->resource[i + PCI_IOV_RESOURCES]; |
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if (!res->parent) |
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continue; |
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size = pcibios_iov_resource_alignment(pdev, i + |
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PCI_IOV_RESOURCES); |
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vf_pe_array[vf_index].bar = |
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cpu_to_be64(res->start + size * vf_index); |
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vf_pe_array[vf_index].rid = |
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cpu_to_be16((pci_iov_virtfn_bus(pdev, vf_index) |
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<< 8) | pci_iov_virtfn_devfn(pdev, |
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vf_index)); |
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vf_pe_array[vf_index].pe_num = |
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cpu_to_be16(IODA_INVALID_PE); |
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} |
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} |
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rc = pseries_send_map_pe(pdev, num_vfs, vf_pe_array); |
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/* Only zero is success */ |
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if (!rc) |
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for (vf_index = 0; vf_index < num_vfs; vf_index++) |
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pseries_set_pe_num(pdev, vf_index, |
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vf_pe_array[vf_index].pe_num); |
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kfree(vf_pe_array); |
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return rc; |
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} |
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int pseries_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) |
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{ |
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struct pci_dn *pdn; |
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int rc; |
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const int *max_vfs; |
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int max_config_vfs; |
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struct device_node *dn = pci_device_to_OF_node(pdev); |
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max_vfs = of_get_property(dn, "ibm,number-of-configurable-vfs", NULL); |
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if (!max_vfs) |
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return -EINVAL; |
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/* First integer stores max config */ |
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max_config_vfs = of_read_number(&max_vfs[0], 1); |
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if (max_config_vfs < num_vfs && num_vfs > MAX_VFS_FOR_MAP_PE) { |
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dev_err(&pdev->dev, |
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"Num VFs %x > %x Configurable VFs\n", |
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num_vfs, (num_vfs > MAX_VFS_FOR_MAP_PE) ? |
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MAX_VFS_FOR_MAP_PE : max_config_vfs); |
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return -EINVAL; |
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} |
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pdn = pci_get_pdn(pdev); |
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pdn->pe_num_map = kmalloc_array(num_vfs, |
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sizeof(*pdn->pe_num_map), |
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GFP_KERNEL); |
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if (!pdn->pe_num_map) |
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return -ENOMEM; |
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rc = pseries_associate_pes(pdev, num_vfs); |
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/* Anything other than zero is failure */ |
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if (rc) { |
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dev_err(&pdev->dev, "Failure to enable sriov: %x\n", rc); |
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kfree(pdn->pe_num_map); |
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} else { |
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pci_vf_drivers_autoprobe(pdev, false); |
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} |
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return rc; |
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} |
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int pseries_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) |
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{ |
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/* Allocate PCI data */ |
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add_sriov_vf_pdns(pdev); |
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return pseries_pci_sriov_enable(pdev, num_vfs); |
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} |
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int pseries_pcibios_sriov_disable(struct pci_dev *pdev) |
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{ |
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struct pci_dn *pdn; |
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pdn = pci_get_pdn(pdev); |
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/* Releasing pe_num_map */ |
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kfree(pdn->pe_num_map); |
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/* Release PCI data */ |
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remove_sriov_vf_pdns(pdev); |
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pci_vf_drivers_autoprobe(pdev, true); |
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return 0; |
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} |
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#endif |
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static void __init pSeries_request_regions(void) |
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{ |
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if (!isa_io_base) |
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return; |
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request_region(0x20,0x20,"pic1"); |
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request_region(0xa0,0x20,"pic2"); |
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request_region(0x00,0x20,"dma1"); |
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request_region(0x40,0x20,"timer"); |
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request_region(0x80,0x10,"dma page reg"); |
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request_region(0xc0,0x20,"dma2"); |
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} |
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void __init pSeries_final_fixup(void) |
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{ |
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struct pci_controller *hose; |
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pSeries_request_regions(); |
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eeh_show_enabled(); |
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#ifdef CONFIG_PCI_IOV |
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ppc_md.pcibios_sriov_enable = pseries_pcibios_sriov_enable; |
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ppc_md.pcibios_sriov_disable = pseries_pcibios_sriov_disable; |
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#endif |
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list_for_each_entry(hose, &hose_list, list_node) { |
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struct device_node *dn = hose->dn, *nvdn; |
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while (1) { |
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dn = of_find_all_nodes(dn); |
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if (!dn) |
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break; |
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nvdn = of_parse_phandle(dn, "ibm,nvlink", 0); |
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if (!nvdn) |
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continue; |
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if (!of_device_is_compatible(nvdn, "ibm,npu-link")) |
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continue; |
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if (!of_device_is_compatible(nvdn->parent, |
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"ibm,power9-npu")) |
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continue; |
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#ifdef CONFIG_PPC_POWERNV |
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WARN_ON_ONCE(pnv_npu2_init(hose)); |
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#endif |
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break; |
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} |
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} |
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} |
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/* |
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* Assume the winbond 82c105 is the IDE controller on a |
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* p610/p615/p630. We should probably be more careful in case |
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* someone tries to plug in a similar adapter. |
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*/ |
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static void fixup_winbond_82c105(struct pci_dev* dev) |
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{ |
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int i; |
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unsigned int reg; |
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if (!machine_is(pseries)) |
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return; |
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printk("Using INTC for W82c105 IDE controller.\n"); |
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pci_read_config_dword(dev, 0x40, ®); |
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/* Enable LEGIRQ to use INTC instead of ISA interrupts */ |
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pci_write_config_dword(dev, 0x40, reg | (1<<11)); |
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for (i = 0; i < DEVICE_COUNT_RESOURCE; ++i) { |
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/* zap the 2nd function of the winbond chip */ |
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if (dev->resource[i].flags & IORESOURCE_IO |
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&& dev->bus->number == 0 && dev->devfn == 0x81) |
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dev->resource[i].flags &= ~IORESOURCE_IO; |
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if (dev->resource[i].start == 0 && dev->resource[i].end) { |
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dev->resource[i].flags = 0; |
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dev->resource[i].end = 0; |
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} |
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} |
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} |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105, |
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fixup_winbond_82c105); |
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int pseries_root_bridge_prepare(struct pci_host_bridge *bridge) |
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{ |
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struct device_node *dn, *pdn; |
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struct pci_bus *bus; |
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u32 pcie_link_speed_stats[2]; |
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int rc; |
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bus = bridge->bus; |
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/* Rely on the pcibios_free_controller_deferred() callback. */ |
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pci_set_host_bridge_release(bridge, pcibios_free_controller_deferred, |
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(void *) pci_bus_to_host(bus)); |
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dn = pcibios_get_phb_of_node(bus); |
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if (!dn) |
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return 0; |
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for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) { |
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rc = of_property_read_u32_array(pdn, |
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"ibm,pcie-link-speed-stats", |
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&pcie_link_speed_stats[0], 2); |
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if (!rc) |
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break; |
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} |
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of_node_put(pdn); |
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if (rc) { |
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pr_debug("no ibm,pcie-link-speed-stats property\n"); |
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return 0; |
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} |
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switch (pcie_link_speed_stats[0]) { |
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case 0x01: |
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bus->max_bus_speed = PCIE_SPEED_2_5GT; |
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break; |
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case 0x02: |
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bus->max_bus_speed = PCIE_SPEED_5_0GT; |
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break; |
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case 0x04: |
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bus->max_bus_speed = PCIE_SPEED_8_0GT; |
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break; |
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default: |
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bus->max_bus_speed = PCI_SPEED_UNKNOWN; |
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break; |
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} |
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switch (pcie_link_speed_stats[1]) { |
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case 0x01: |
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bus->cur_bus_speed = PCIE_SPEED_2_5GT; |
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break; |
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case 0x02: |
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bus->cur_bus_speed = PCIE_SPEED_5_0GT; |
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break; |
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case 0x04: |
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bus->cur_bus_speed = PCIE_SPEED_8_0GT; |
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break; |
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default: |
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bus->cur_bus_speed = PCI_SPEED_UNKNOWN; |
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break; |
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} |
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return 0; |
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}
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