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561 lines
14 KiB
561 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* PowerNV setup code. |
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* |
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* Copyright 2011 IBM Corp. |
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*/ |
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#undef DEBUG |
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#include <linux/cpu.h> |
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#include <linux/errno.h> |
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#include <linux/sched.h> |
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#include <linux/kernel.h> |
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#include <linux/tty.h> |
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#include <linux/reboot.h> |
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#include <linux/init.h> |
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#include <linux/console.h> |
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#include <linux/delay.h> |
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#include <linux/irq.h> |
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#include <linux/seq_file.h> |
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#include <linux/of.h> |
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#include <linux/of_fdt.h> |
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#include <linux/interrupt.h> |
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#include <linux/bug.h> |
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#include <linux/pci.h> |
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#include <linux/cpufreq.h> |
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#include <linux/memblock.h> |
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#include <asm/machdep.h> |
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#include <asm/firmware.h> |
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#include <asm/xics.h> |
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#include <asm/xive.h> |
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#include <asm/opal.h> |
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#include <asm/kexec.h> |
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#include <asm/smp.h> |
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#include <asm/tm.h> |
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#include <asm/setup.h> |
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#include <asm/security_features.h> |
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#include "powernv.h" |
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static bool fw_feature_is(const char *state, const char *name, |
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struct device_node *fw_features) |
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{ |
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struct device_node *np; |
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bool rc = false; |
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np = of_get_child_by_name(fw_features, name); |
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if (np) { |
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rc = of_property_read_bool(np, state); |
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of_node_put(np); |
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} |
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return rc; |
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} |
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static void init_fw_feat_flags(struct device_node *np) |
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{ |
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if (fw_feature_is("enabled", "inst-spec-barrier-ori31,31,0", np)) |
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security_ftr_set(SEC_FTR_SPEC_BAR_ORI31); |
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if (fw_feature_is("enabled", "fw-bcctrl-serialized", np)) |
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security_ftr_set(SEC_FTR_BCCTRL_SERIALISED); |
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if (fw_feature_is("enabled", "inst-l1d-flush-ori30,30,0", np)) |
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security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30); |
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if (fw_feature_is("enabled", "inst-l1d-flush-trig2", np)) |
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security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2); |
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if (fw_feature_is("enabled", "fw-l1d-thread-split", np)) |
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security_ftr_set(SEC_FTR_L1D_THREAD_PRIV); |
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if (fw_feature_is("enabled", "fw-count-cache-disabled", np)) |
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security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED); |
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if (fw_feature_is("enabled", "fw-count-cache-flush-bcctr2,0,0", np)) |
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security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST); |
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if (fw_feature_is("enabled", "needs-count-cache-flush-on-context-switch", np)) |
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security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE); |
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/* |
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* The features below are enabled by default, so we instead look to see |
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* if firmware has *disabled* them, and clear them if so. |
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*/ |
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if (fw_feature_is("disabled", "speculation-policy-favor-security", np)) |
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security_ftr_clear(SEC_FTR_FAVOUR_SECURITY); |
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if (fw_feature_is("disabled", "needs-l1d-flush-msr-pr-0-to-1", np)) |
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security_ftr_clear(SEC_FTR_L1D_FLUSH_PR); |
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if (fw_feature_is("disabled", "needs-l1d-flush-msr-hv-1-to-0", np)) |
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security_ftr_clear(SEC_FTR_L1D_FLUSH_HV); |
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if (fw_feature_is("disabled", "needs-spec-barrier-for-bound-checks", np)) |
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security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR); |
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} |
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static void pnv_setup_security_mitigations(void) |
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{ |
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struct device_node *np, *fw_features; |
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enum l1d_flush_type type; |
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bool enable; |
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/* Default to fallback in case fw-features are not available */ |
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type = L1D_FLUSH_FALLBACK; |
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np = of_find_node_by_name(NULL, "ibm,opal"); |
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fw_features = of_get_child_by_name(np, "fw-features"); |
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of_node_put(np); |
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if (fw_features) { |
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init_fw_feat_flags(fw_features); |
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of_node_put(fw_features); |
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if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2)) |
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type = L1D_FLUSH_MTTRIG; |
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if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30)) |
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type = L1D_FLUSH_ORI; |
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} |
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/* |
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* If we are non-Power9 bare metal, we don't need to flush on kernel |
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* entry or after user access: they fix a P9 specific vulnerability. |
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*/ |
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if (!pvr_version_is(PVR_POWER9)) { |
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security_ftr_clear(SEC_FTR_L1D_FLUSH_ENTRY); |
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security_ftr_clear(SEC_FTR_L1D_FLUSH_UACCESS); |
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} |
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enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \ |
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(security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR) || \ |
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security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV)); |
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setup_rfi_flush(type, enable); |
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setup_count_cache_flush(); |
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enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && |
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security_ftr_enabled(SEC_FTR_L1D_FLUSH_ENTRY); |
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setup_entry_flush(enable); |
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enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && |
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security_ftr_enabled(SEC_FTR_L1D_FLUSH_UACCESS); |
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setup_uaccess_flush(enable); |
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setup_stf_barrier(); |
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} |
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static void __init pnv_check_guarded_cores(void) |
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{ |
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struct device_node *dn; |
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int bad_count = 0; |
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for_each_node_by_type(dn, "cpu") { |
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if (of_property_match_string(dn, "status", "bad") >= 0) |
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bad_count++; |
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}; |
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if (bad_count) { |
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printk(" _ _______________\n"); |
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pr_cont(" | | / \\\n"); |
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pr_cont(" | | | WARNING! |\n"); |
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pr_cont(" | | | |\n"); |
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pr_cont(" | | | It looks like |\n"); |
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pr_cont(" |_| | you have %*d |\n", 3, bad_count); |
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pr_cont(" _ | guarded cores |\n"); |
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pr_cont(" (_) \\_______________/\n"); |
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} |
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} |
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static void __init pnv_setup_arch(void) |
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{ |
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set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT); |
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pnv_setup_security_mitigations(); |
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/* Initialize SMP */ |
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pnv_smp_init(); |
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/* Setup PCI */ |
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pnv_pci_init(); |
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/* Setup RTC and NVRAM callbacks */ |
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if (firmware_has_feature(FW_FEATURE_OPAL)) |
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opal_nvram_init(); |
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/* Enable NAP mode */ |
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powersave_nap = 1; |
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pnv_check_guarded_cores(); |
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/* XXX PMCS */ |
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} |
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static void __init pnv_init(void) |
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{ |
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/* |
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* Initialize the LPC bus now so that legacy serial |
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* ports can be found on it |
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*/ |
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opal_lpc_init(); |
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#ifdef CONFIG_HVC_OPAL |
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if (firmware_has_feature(FW_FEATURE_OPAL)) |
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hvc_opal_init_early(); |
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else |
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#endif |
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add_preferred_console("hvc", 0, NULL); |
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if (!radix_enabled()) { |
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size_t size = sizeof(struct slb_entry) * mmu_slb_size; |
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int i; |
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/* Allocate per cpu area to save old slb contents during MCE */ |
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for_each_possible_cpu(i) { |
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paca_ptrs[i]->mce_faulty_slbs = |
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memblock_alloc_node(size, |
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__alignof__(struct slb_entry), |
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cpu_to_node(i)); |
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} |
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} |
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} |
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static void __init pnv_init_IRQ(void) |
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{ |
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/* Try using a XIVE if available, otherwise use a XICS */ |
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if (!xive_native_init()) |
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xics_init(); |
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WARN_ON(!ppc_md.get_irq); |
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} |
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static void pnv_show_cpuinfo(struct seq_file *m) |
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{ |
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struct device_node *root; |
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const char *model = ""; |
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root = of_find_node_by_path("/"); |
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if (root) |
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model = of_get_property(root, "model", NULL); |
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seq_printf(m, "machine\t\t: PowerNV %s\n", model); |
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if (firmware_has_feature(FW_FEATURE_OPAL)) |
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seq_printf(m, "firmware\t: OPAL\n"); |
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else |
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seq_printf(m, "firmware\t: BML\n"); |
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of_node_put(root); |
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if (radix_enabled()) |
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seq_printf(m, "MMU\t\t: Radix\n"); |
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else |
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seq_printf(m, "MMU\t\t: Hash\n"); |
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} |
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static void pnv_prepare_going_down(void) |
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{ |
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/* |
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* Disable all notifiers from OPAL, we can't |
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* service interrupts anymore anyway |
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*/ |
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opal_event_shutdown(); |
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/* Print flash update message if one is scheduled. */ |
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opal_flash_update_print_message(); |
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smp_send_stop(); |
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hard_irq_disable(); |
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} |
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static void __noreturn pnv_restart(char *cmd) |
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{ |
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long rc; |
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pnv_prepare_going_down(); |
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do { |
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if (!cmd || !strlen(cmd)) |
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rc = opal_cec_reboot(); |
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else if (strcmp(cmd, "full") == 0) |
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rc = opal_cec_reboot2(OPAL_REBOOT_FULL_IPL, NULL); |
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else if (strcmp(cmd, "mpipl") == 0) |
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rc = opal_cec_reboot2(OPAL_REBOOT_MPIPL, NULL); |
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else if (strcmp(cmd, "error") == 0) |
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rc = opal_cec_reboot2(OPAL_REBOOT_PLATFORM_ERROR, NULL); |
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else if (strcmp(cmd, "fast") == 0) |
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rc = opal_cec_reboot2(OPAL_REBOOT_FAST, NULL); |
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else |
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rc = OPAL_UNSUPPORTED; |
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if (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) { |
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/* Opal is busy wait for some time and retry */ |
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opal_poll_events(NULL); |
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mdelay(10); |
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} else if (cmd && rc) { |
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/* Unknown error while issuing reboot */ |
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if (rc == OPAL_UNSUPPORTED) |
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pr_err("Unsupported '%s' reboot.\n", cmd); |
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else |
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pr_err("Unable to issue '%s' reboot. Err=%ld\n", |
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cmd, rc); |
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pr_info("Forcing a cec-reboot\n"); |
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cmd = NULL; |
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rc = OPAL_BUSY; |
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} else if (rc != OPAL_SUCCESS) { |
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/* Unknown error while issuing cec-reboot */ |
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pr_err("Unable to reboot. Err=%ld\n", rc); |
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} |
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} while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT); |
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for (;;) |
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opal_poll_events(NULL); |
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} |
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static void __noreturn pnv_power_off(void) |
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{ |
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long rc = OPAL_BUSY; |
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pnv_prepare_going_down(); |
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while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) { |
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rc = opal_cec_power_down(0); |
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if (rc == OPAL_BUSY_EVENT) |
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opal_poll_events(NULL); |
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else |
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mdelay(10); |
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} |
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for (;;) |
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opal_poll_events(NULL); |
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} |
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static void __noreturn pnv_halt(void) |
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{ |
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pnv_power_off(); |
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} |
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static void pnv_progress(char *s, unsigned short hex) |
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{ |
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} |
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static void pnv_shutdown(void) |
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{ |
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/* Let the PCI code clear up IODA tables */ |
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pnv_pci_shutdown(); |
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/* |
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* Stop OPAL activity: Unregister all OPAL interrupts so they |
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* don't fire up while we kexec and make sure all potentially |
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* DMA'ing ops are complete (such as dump retrieval). |
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*/ |
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opal_shutdown(); |
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} |
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#ifdef CONFIG_KEXEC_CORE |
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static void pnv_kexec_wait_secondaries_down(void) |
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{ |
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int my_cpu, i, notified = -1; |
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my_cpu = get_cpu(); |
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for_each_online_cpu(i) { |
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uint8_t status; |
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int64_t rc, timeout = 1000; |
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if (i == my_cpu) |
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continue; |
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for (;;) { |
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rc = opal_query_cpu_status(get_hard_smp_processor_id(i), |
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&status); |
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if (rc != OPAL_SUCCESS || status != OPAL_THREAD_STARTED) |
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break; |
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barrier(); |
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if (i != notified) { |
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printk(KERN_INFO "kexec: waiting for cpu %d " |
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"(physical %d) to enter OPAL\n", |
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i, paca_ptrs[i]->hw_cpu_id); |
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notified = i; |
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} |
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/* |
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* On crash secondaries might be unreachable or hung, |
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* so timeout if we've waited too long |
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* */ |
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mdelay(1); |
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if (timeout-- == 0) { |
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printk(KERN_ERR "kexec: timed out waiting for " |
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"cpu %d (physical %d) to enter OPAL\n", |
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i, paca_ptrs[i]->hw_cpu_id); |
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break; |
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} |
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} |
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} |
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} |
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static void pnv_kexec_cpu_down(int crash_shutdown, int secondary) |
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{ |
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u64 reinit_flags; |
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if (xive_enabled()) |
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xive_teardown_cpu(); |
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else |
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xics_kexec_teardown_cpu(secondary); |
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/* On OPAL, we return all CPUs to firmware */ |
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if (!firmware_has_feature(FW_FEATURE_OPAL)) |
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return; |
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if (secondary) { |
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/* Return secondary CPUs to firmware on OPAL v3 */ |
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mb(); |
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get_paca()->kexec_state = KEXEC_STATE_REAL_MODE; |
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mb(); |
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/* Return the CPU to OPAL */ |
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opal_return_cpu(); |
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} else { |
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/* Primary waits for the secondaries to have reached OPAL */ |
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pnv_kexec_wait_secondaries_down(); |
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/* Switch XIVE back to emulation mode */ |
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if (xive_enabled()) |
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xive_shutdown(); |
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/* |
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* We might be running as little-endian - now that interrupts |
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* are disabled, reset the HILE bit to big-endian so we don't |
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* take interrupts in the wrong endian later |
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* |
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* We reinit to enable both radix and hash on P9 to ensure |
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* the mode used by the next kernel is always supported. |
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*/ |
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reinit_flags = OPAL_REINIT_CPUS_HILE_BE; |
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if (cpu_has_feature(CPU_FTR_ARCH_300)) |
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reinit_flags |= OPAL_REINIT_CPUS_MMU_RADIX | |
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OPAL_REINIT_CPUS_MMU_HASH; |
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opal_reinit_cpus(reinit_flags); |
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} |
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} |
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#endif /* CONFIG_KEXEC_CORE */ |
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#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE |
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static unsigned long pnv_memory_block_size(void) |
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{ |
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/* |
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* We map the kernel linear region with 1GB large pages on radix. For |
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* memory hot unplug to work our memory block size must be at least |
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* this size. |
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*/ |
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if (radix_enabled()) |
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return radix_mem_block_size; |
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else |
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return 256UL * 1024 * 1024; |
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} |
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#endif |
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static void __init pnv_setup_machdep_opal(void) |
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{ |
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ppc_md.get_boot_time = opal_get_boot_time; |
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ppc_md.restart = pnv_restart; |
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pm_power_off = pnv_power_off; |
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ppc_md.halt = pnv_halt; |
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/* ppc_md.system_reset_exception gets filled in by pnv_smp_init() */ |
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ppc_md.machine_check_exception = opal_machine_check; |
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ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery; |
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if (opal_check_token(OPAL_HANDLE_HMI2)) |
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ppc_md.hmi_exception_early = opal_hmi_exception_early2; |
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else |
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ppc_md.hmi_exception_early = opal_hmi_exception_early; |
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ppc_md.handle_hmi_exception = opal_handle_hmi_exception; |
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} |
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static int __init pnv_probe(void) |
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{ |
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if (!of_machine_is_compatible("ibm,powernv")) |
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return 0; |
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if (firmware_has_feature(FW_FEATURE_OPAL)) |
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pnv_setup_machdep_opal(); |
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pr_debug("PowerNV detected !\n"); |
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pnv_init(); |
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return 1; |
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} |
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
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void __init pnv_tm_init(void) |
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{ |
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if (!firmware_has_feature(FW_FEATURE_OPAL) || |
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!pvr_version_is(PVR_POWER9) || |
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early_cpu_has_feature(CPU_FTR_TM)) |
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return; |
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if (opal_reinit_cpus(OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED) != OPAL_SUCCESS) |
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return; |
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pr_info("Enabling TM (Transactional Memory) with Suspend Disabled\n"); |
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cur_cpu_spec->cpu_features |= CPU_FTR_TM; |
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/* Make sure "normal" HTM is off (it should be) */ |
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cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_HTM; |
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/* Turn on no suspend mode, and HTM no SC */ |
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cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NO_SUSPEND | \ |
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PPC_FEATURE2_HTM_NOSC; |
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tm_suspend_disabled = true; |
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} |
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#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
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|
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/* |
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* Returns the cpu frequency for 'cpu' in Hz. This is used by |
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* /proc/cpuinfo |
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*/ |
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static unsigned long pnv_get_proc_freq(unsigned int cpu) |
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{ |
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unsigned long ret_freq; |
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ret_freq = cpufreq_get(cpu) * 1000ul; |
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/* |
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* If the backend cpufreq driver does not exist, |
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* then fallback to old way of reporting the clockrate. |
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*/ |
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if (!ret_freq) |
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ret_freq = ppc_proc_freq; |
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return ret_freq; |
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} |
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static long pnv_machine_check_early(struct pt_regs *regs) |
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{ |
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long handled = 0; |
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if (cur_cpu_spec && cur_cpu_spec->machine_check_early) |
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handled = cur_cpu_spec->machine_check_early(regs); |
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return handled; |
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} |
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define_machine(powernv) { |
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.name = "PowerNV", |
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.probe = pnv_probe, |
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.setup_arch = pnv_setup_arch, |
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.init_IRQ = pnv_init_IRQ, |
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.show_cpuinfo = pnv_show_cpuinfo, |
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.get_proc_freq = pnv_get_proc_freq, |
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.progress = pnv_progress, |
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.machine_shutdown = pnv_shutdown, |
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.power_save = NULL, |
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.calibrate_decr = generic_calibrate_decr, |
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.machine_check_early = pnv_machine_check_early, |
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#ifdef CONFIG_KEXEC_CORE |
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.kexec_cpu_down = pnv_kexec_cpu_down, |
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#endif |
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#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE |
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.memory_block_size = pnv_memory_block_size, |
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#endif |
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};
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