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669 lines
17 KiB
669 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2004 Benjamin Herrenschmuidt ([email protected]), |
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* IBM Corp. |
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*/ |
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|
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#undef DEBUG |
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|
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#include <linux/kernel.h> |
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#include <linux/pci.h> |
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#include <linux/delay.h> |
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#include <linux/string.h> |
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#include <linux/init.h> |
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#include <linux/irq.h> |
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|
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#include <asm/sections.h> |
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#include <asm/io.h> |
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#include <asm/prom.h> |
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#include <asm/pci-bridge.h> |
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#include <asm/machdep.h> |
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#include <asm/iommu.h> |
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#include <asm/ppc-pci.h> |
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#include <asm/isa-bridge.h> |
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|
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#include "maple.h" |
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|
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#ifdef DEBUG |
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#define DBG(x...) printk(x) |
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#else |
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#define DBG(x...) |
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#endif |
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|
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static struct pci_controller *u3_agp, *u3_ht, *u4_pcie; |
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|
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static int __init fixup_one_level_bus_range(struct device_node *node, int higher) |
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{ |
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for (; node != 0;node = node->sibling) { |
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const int *bus_range; |
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const unsigned int *class_code; |
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int len; |
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|
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/* For PCI<->PCI bridges or CardBus bridges, we go down */ |
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class_code = of_get_property(node, "class-code", NULL); |
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if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && |
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(*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) |
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continue; |
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bus_range = of_get_property(node, "bus-range", &len); |
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if (bus_range != NULL && len > 2 * sizeof(int)) { |
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if (bus_range[1] > higher) |
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higher = bus_range[1]; |
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} |
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higher = fixup_one_level_bus_range(node->child, higher); |
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} |
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return higher; |
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} |
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|
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/* This routine fixes the "bus-range" property of all bridges in the |
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* system since they tend to have their "last" member wrong on macs |
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* |
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* Note that the bus numbers manipulated here are OF bus numbers, they |
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* are not Linux bus numbers. |
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*/ |
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static void __init fixup_bus_range(struct device_node *bridge) |
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{ |
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int *bus_range; |
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struct property *prop; |
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int len; |
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|
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/* Lookup the "bus-range" property for the hose */ |
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prop = of_find_property(bridge, "bus-range", &len); |
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if (prop == NULL || prop->value == NULL || len < 2 * sizeof(int)) { |
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printk(KERN_WARNING "Can't get bus-range for %pOF\n", |
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bridge); |
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return; |
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} |
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bus_range = prop->value; |
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bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); |
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} |
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|
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static unsigned long u3_agp_cfa0(u8 devfn, u8 off) |
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{ |
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return (1 << (unsigned long)PCI_SLOT(devfn)) | |
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((unsigned long)PCI_FUNC(devfn) << 8) | |
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((unsigned long)off & 0xFCUL); |
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} |
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|
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static unsigned long u3_agp_cfa1(u8 bus, u8 devfn, u8 off) |
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{ |
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return ((unsigned long)bus << 16) | |
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((unsigned long)devfn << 8) | |
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((unsigned long)off & 0xFCUL) | |
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1UL; |
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} |
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|
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static volatile void __iomem *u3_agp_cfg_access(struct pci_controller* hose, |
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u8 bus, u8 dev_fn, u8 offset) |
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{ |
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unsigned int caddr; |
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|
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if (bus == hose->first_busno) { |
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if (dev_fn < (11 << 3)) |
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return NULL; |
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caddr = u3_agp_cfa0(dev_fn, offset); |
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} else |
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caddr = u3_agp_cfa1(bus, dev_fn, offset); |
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|
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/* Uninorth will return garbage if we don't read back the value ! */ |
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do { |
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out_le32(hose->cfg_addr, caddr); |
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} while (in_le32(hose->cfg_addr) != caddr); |
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|
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offset &= 0x07; |
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return hose->cfg_data + offset; |
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} |
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|
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static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn, |
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int offset, int len, u32 *val) |
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{ |
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struct pci_controller *hose; |
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volatile void __iomem *addr; |
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|
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hose = pci_bus_to_host(bus); |
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if (hose == NULL) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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|
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addr = u3_agp_cfg_access(hose, bus->number, devfn, offset); |
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if (!addr) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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/* |
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* Note: the caller has already checked that offset is |
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* suitably aligned and that len is 1, 2 or 4. |
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*/ |
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switch (len) { |
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case 1: |
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*val = in_8(addr); |
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break; |
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case 2: |
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*val = in_le16(addr); |
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break; |
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default: |
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*val = in_le32(addr); |
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break; |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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|
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static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn, |
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int offset, int len, u32 val) |
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{ |
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struct pci_controller *hose; |
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volatile void __iomem *addr; |
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|
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hose = pci_bus_to_host(bus); |
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if (hose == NULL) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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|
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addr = u3_agp_cfg_access(hose, bus->number, devfn, offset); |
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if (!addr) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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/* |
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* Note: the caller has already checked that offset is |
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* suitably aligned and that len is 1, 2 or 4. |
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*/ |
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switch (len) { |
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case 1: |
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out_8(addr, val); |
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break; |
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case 2: |
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out_le16(addr, val); |
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break; |
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default: |
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out_le32(addr, val); |
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break; |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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|
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static struct pci_ops u3_agp_pci_ops = |
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{ |
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.read = u3_agp_read_config, |
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.write = u3_agp_write_config, |
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}; |
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|
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static unsigned long u3_ht_cfa0(u8 devfn, u8 off) |
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{ |
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return (devfn << 8) | off; |
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} |
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|
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static unsigned long u3_ht_cfa1(u8 bus, u8 devfn, u8 off) |
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{ |
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return u3_ht_cfa0(devfn, off) + (bus << 16) + 0x01000000UL; |
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} |
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|
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static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose, |
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u8 bus, u8 devfn, u8 offset) |
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{ |
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if (bus == hose->first_busno) { |
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if (PCI_SLOT(devfn) == 0) |
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return NULL; |
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return hose->cfg_data + u3_ht_cfa0(devfn, offset); |
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} else |
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return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset); |
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} |
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|
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static int u3_ht_root_read_config(struct pci_controller *hose, u8 offset, |
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int len, u32 *val) |
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{ |
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volatile void __iomem *addr; |
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|
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addr = hose->cfg_addr; |
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addr += ((offset & ~3) << 2) + (4 - len - (offset & 3)); |
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|
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switch (len) { |
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case 1: |
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*val = in_8(addr); |
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break; |
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case 2: |
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*val = in_be16(addr); |
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break; |
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default: |
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*val = in_be32(addr); |
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break; |
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} |
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|
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int u3_ht_root_write_config(struct pci_controller *hose, u8 offset, |
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int len, u32 val) |
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{ |
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volatile void __iomem *addr; |
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|
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addr = hose->cfg_addr + ((offset & ~3) << 2) + (4 - len - (offset & 3)); |
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|
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if (offset >= PCI_BASE_ADDRESS_0 && offset < PCI_CAPABILITY_LIST) |
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return PCIBIOS_SUCCESSFUL; |
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|
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switch (len) { |
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case 1: |
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out_8(addr, val); |
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break; |
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case 2: |
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out_be16(addr, val); |
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break; |
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default: |
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out_be32(addr, val); |
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break; |
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} |
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|
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return PCIBIOS_SUCCESSFUL; |
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} |
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|
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static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, |
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int offset, int len, u32 *val) |
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{ |
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struct pci_controller *hose; |
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volatile void __iomem *addr; |
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|
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hose = pci_bus_to_host(bus); |
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if (hose == NULL) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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|
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if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0)) |
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return u3_ht_root_read_config(hose, offset, len, val); |
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if (offset > 0xff) |
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return PCIBIOS_BAD_REGISTER_NUMBER; |
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addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); |
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if (!addr) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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|
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/* |
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* Note: the caller has already checked that offset is |
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* suitably aligned and that len is 1, 2 or 4. |
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*/ |
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switch (len) { |
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case 1: |
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*val = in_8(addr); |
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break; |
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case 2: |
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*val = in_le16(addr); |
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break; |
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default: |
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*val = in_le32(addr); |
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break; |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, |
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int offset, int len, u32 val) |
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{ |
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struct pci_controller *hose; |
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volatile void __iomem *addr; |
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|
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hose = pci_bus_to_host(bus); |
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if (hose == NULL) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0)) |
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return u3_ht_root_write_config(hose, offset, len, val); |
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if (offset > 0xff) |
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return PCIBIOS_BAD_REGISTER_NUMBER; |
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addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); |
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if (!addr) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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/* |
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* Note: the caller has already checked that offset is |
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* suitably aligned and that len is 1, 2 or 4. |
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*/ |
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switch (len) { |
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case 1: |
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out_8(addr, val); |
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break; |
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case 2: |
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out_le16(addr, val); |
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break; |
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default: |
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out_le32(addr, val); |
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break; |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static struct pci_ops u3_ht_pci_ops = |
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{ |
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.read = u3_ht_read_config, |
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.write = u3_ht_write_config, |
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}; |
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|
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static unsigned int u4_pcie_cfa0(unsigned int devfn, unsigned int off) |
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{ |
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return (1 << PCI_SLOT(devfn)) | |
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(PCI_FUNC(devfn) << 8) | |
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((off >> 8) << 28) | |
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(off & 0xfcu); |
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} |
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|
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static unsigned int u4_pcie_cfa1(unsigned int bus, unsigned int devfn, |
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unsigned int off) |
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{ |
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return (bus << 16) | |
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(devfn << 8) | |
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((off >> 8) << 28) | |
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(off & 0xfcu) | 1u; |
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} |
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|
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static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose, |
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u8 bus, u8 dev_fn, int offset) |
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{ |
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unsigned int caddr; |
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|
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if (bus == hose->first_busno) |
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caddr = u4_pcie_cfa0(dev_fn, offset); |
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else |
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caddr = u4_pcie_cfa1(bus, dev_fn, offset); |
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|
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/* Uninorth will return garbage if we don't read back the value ! */ |
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do { |
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out_le32(hose->cfg_addr, caddr); |
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} while (in_le32(hose->cfg_addr) != caddr); |
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|
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offset &= 0x03; |
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return hose->cfg_data + offset; |
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} |
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|
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static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn, |
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int offset, int len, u32 *val) |
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{ |
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struct pci_controller *hose; |
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volatile void __iomem *addr; |
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|
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hose = pci_bus_to_host(bus); |
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if (hose == NULL) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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if (offset >= 0x1000) |
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return PCIBIOS_BAD_REGISTER_NUMBER; |
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addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); |
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if (!addr) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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/* |
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* Note: the caller has already checked that offset is |
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* suitably aligned and that len is 1, 2 or 4. |
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*/ |
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switch (len) { |
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case 1: |
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*val = in_8(addr); |
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break; |
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case 2: |
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*val = in_le16(addr); |
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break; |
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default: |
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*val = in_le32(addr); |
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break; |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn, |
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int offset, int len, u32 val) |
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{ |
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struct pci_controller *hose; |
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volatile void __iomem *addr; |
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|
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hose = pci_bus_to_host(bus); |
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if (hose == NULL) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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if (offset >= 0x1000) |
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return PCIBIOS_BAD_REGISTER_NUMBER; |
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addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); |
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if (!addr) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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/* |
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* Note: the caller has already checked that offset is |
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* suitably aligned and that len is 1, 2 or 4. |
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*/ |
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switch (len) { |
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case 1: |
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out_8(addr, val); |
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break; |
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case 2: |
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out_le16(addr, val); |
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break; |
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default: |
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out_le32(addr, val); |
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break; |
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} |
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return PCIBIOS_SUCCESSFUL; |
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} |
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|
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static struct pci_ops u4_pcie_pci_ops = |
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{ |
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.read = u4_pcie_read_config, |
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.write = u4_pcie_write_config, |
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}; |
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|
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static void __init setup_u3_agp(struct pci_controller* hose) |
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{ |
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/* On G5, we move AGP up to high bus number so we don't need |
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* to reassign bus numbers for HT. If we ever have P2P bridges |
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* on AGP, we'll have to move pci_assign_all_buses to the |
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* pci_controller structure so we enable it for AGP and not for |
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* HT childs. |
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* We hard code the address because of the different size of |
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* the reg address cell, we shall fix that by killing struct |
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* reg_property and using some accessor functions instead |
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*/ |
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hose->first_busno = 0xf0; |
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hose->last_busno = 0xff; |
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hose->ops = &u3_agp_pci_ops; |
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hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); |
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hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); |
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|
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u3_agp = hose; |
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} |
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|
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static void __init setup_u4_pcie(struct pci_controller* hose) |
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{ |
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/* We currently only implement the "non-atomic" config space, to |
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* be optimised later. |
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*/ |
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hose->ops = &u4_pcie_pci_ops; |
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hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); |
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hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); |
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|
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u4_pcie = hose; |
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} |
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|
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static void __init setup_u3_ht(struct pci_controller* hose) |
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{ |
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hose->ops = &u3_ht_pci_ops; |
|
|
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/* We hard code the address because of the different size of |
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* the reg address cell, we shall fix that by killing struct |
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* reg_property and using some accessor functions instead |
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*/ |
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hose->cfg_data = ioremap(0xf2000000, 0x02000000); |
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hose->cfg_addr = ioremap(0xf8070000, 0x1000); |
|
|
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hose->first_busno = 0; |
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hose->last_busno = 0xef; |
|
|
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u3_ht = hose; |
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} |
|
|
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static int __init maple_add_bridge(struct device_node *dev) |
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{ |
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int len; |
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struct pci_controller *hose; |
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char* disp_name; |
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const int *bus_range; |
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int primary = 1; |
|
|
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DBG("Adding PCI host bridge %pOF\n", dev); |
|
|
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bus_range = of_get_property(dev, "bus-range", &len); |
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if (bus_range == NULL || len < 2 * sizeof(int)) { |
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printk(KERN_WARNING "Can't get bus-range for %pOF, assume bus 0\n", |
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dev); |
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} |
|
|
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hose = pcibios_alloc_controller(dev); |
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if (hose == NULL) |
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return -ENOMEM; |
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hose->first_busno = bus_range ? bus_range[0] : 0; |
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hose->last_busno = bus_range ? bus_range[1] : 0xff; |
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hose->controller_ops = maple_pci_controller_ops; |
|
|
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disp_name = NULL; |
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if (of_device_is_compatible(dev, "u3-agp")) { |
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setup_u3_agp(hose); |
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disp_name = "U3-AGP"; |
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primary = 0; |
|
} else if (of_device_is_compatible(dev, "u3-ht")) { |
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setup_u3_ht(hose); |
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disp_name = "U3-HT"; |
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primary = 1; |
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} else if (of_device_is_compatible(dev, "u4-pcie")) { |
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setup_u4_pcie(hose); |
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disp_name = "U4-PCIE"; |
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primary = 0; |
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} |
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printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n", |
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disp_name, hose->first_busno, hose->last_busno); |
|
|
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/* Interpret the "ranges" property */ |
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/* This also maps the I/O region and sets isa_io/mem_base */ |
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pci_process_bridge_OF_ranges(hose, dev, primary); |
|
|
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/* Fixup "bus-range" OF property */ |
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fixup_bus_range(dev); |
|
|
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/* Check for legacy IOs */ |
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isa_bridge_find_early(hose); |
|
|
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return 0; |
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} |
|
|
|
|
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void maple_pci_irq_fixup(struct pci_dev *dev) |
|
{ |
|
DBG(" -> maple_pci_irq_fixup\n"); |
|
|
|
/* Fixup IRQ for PCIe host */ |
|
if (u4_pcie != NULL && dev->bus->number == 0 && |
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pci_bus_to_host(dev->bus) == u4_pcie) { |
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printk(KERN_DEBUG "Fixup U4 PCIe IRQ\n"); |
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dev->irq = irq_create_mapping(NULL, 1); |
|
if (dev->irq) |
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irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); |
|
} |
|
|
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/* Hide AMD8111 IDE interrupt when in legacy mode so |
|
* the driver calls pci_get_legacy_ide_irq() |
|
*/ |
|
if (dev->vendor == PCI_VENDOR_ID_AMD && |
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dev->device == PCI_DEVICE_ID_AMD_8111_IDE && |
|
(dev->class & 5) != 5) { |
|
dev->irq = 0; |
|
} |
|
|
|
DBG(" <- maple_pci_irq_fixup\n"); |
|
} |
|
|
|
static int maple_pci_root_bridge_prepare(struct pci_host_bridge *bridge) |
|
{ |
|
struct pci_controller *hose = pci_bus_to_host(bridge->bus); |
|
struct device_node *np, *child; |
|
|
|
if (hose != u3_agp) |
|
return 0; |
|
|
|
/* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We |
|
* assume there is no P2P bridge on the AGP bus, which should be a |
|
* safe assumptions hopefully. |
|
*/ |
|
np = hose->dn; |
|
PCI_DN(np)->busno = 0xf0; |
|
for_each_child_of_node(np, child) |
|
PCI_DN(child)->busno = 0xf0; |
|
|
|
return 0; |
|
} |
|
|
|
void __init maple_pci_init(void) |
|
{ |
|
struct device_node *np, *root; |
|
struct device_node *ht = NULL; |
|
|
|
/* Probe root PCI hosts, that is on U3 the AGP host and the |
|
* HyperTransport host. That one is actually "kept" around |
|
* and actually added last as it's resource management relies |
|
* on the AGP resources to have been setup first |
|
*/ |
|
root = of_find_node_by_path("/"); |
|
if (root == NULL) { |
|
printk(KERN_CRIT "maple_find_bridges: can't find root of device tree\n"); |
|
return; |
|
} |
|
for_each_child_of_node(root, np) { |
|
if (!of_node_is_type(np, "pci") && !of_node_is_type(np, "ht")) |
|
continue; |
|
if ((of_device_is_compatible(np, "u4-pcie") || |
|
of_device_is_compatible(np, "u3-agp")) && |
|
maple_add_bridge(np) == 0) |
|
of_node_get(np); |
|
|
|
if (of_device_is_compatible(np, "u3-ht")) { |
|
of_node_get(np); |
|
ht = np; |
|
} |
|
} |
|
of_node_put(root); |
|
|
|
/* Now setup the HyperTransport host if we found any |
|
*/ |
|
if (ht && maple_add_bridge(ht) != 0) |
|
of_node_put(ht); |
|
|
|
ppc_md.pcibios_root_bridge_prepare = maple_pci_root_bridge_prepare; |
|
|
|
/* Tell pci.c to not change any resource allocations. */ |
|
pci_add_flags(PCI_PROBE_ONLY); |
|
} |
|
|
|
int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel) |
|
{ |
|
struct device_node *np; |
|
unsigned int defirq = channel ? 15 : 14; |
|
unsigned int irq; |
|
|
|
if (pdev->vendor != PCI_VENDOR_ID_AMD || |
|
pdev->device != PCI_DEVICE_ID_AMD_8111_IDE) |
|
return defirq; |
|
|
|
np = pci_device_to_OF_node(pdev); |
|
if (np == NULL) { |
|
printk("Failed to locate OF node for IDE %s\n", |
|
pci_name(pdev)); |
|
return defirq; |
|
} |
|
irq = irq_of_parse_and_map(np, channel & 0x1); |
|
if (!irq) { |
|
printk("Failed to map onboard IDE interrupt for channel %d\n", |
|
channel); |
|
return defirq; |
|
} |
|
return irq; |
|
} |
|
|
|
static void quirk_ipr_msi(struct pci_dev *dev) |
|
{ |
|
/* Something prevents MSIs from the IPR from working on Bimini, |
|
* and the driver has no smarts to recover. So disable MSI |
|
* on it for now. */ |
|
|
|
if (machine_is(maple)) { |
|
dev->no_msi = 1; |
|
dev_info(&dev->dev, "Quirk disabled MSI\n"); |
|
} |
|
} |
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN, |
|
quirk_ipr_msi); |
|
|
|
struct pci_controller_ops maple_pci_controller_ops = { |
|
};
|
|
|