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331 lines
8.0 KiB
331 lines
8.0 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* arch/powerpc/sysdev/uic.c |
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* |
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* IBM PowerPC 4xx Universal Interrupt Controller |
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* |
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* Copyright 2007 David Gibson <[email protected]>, IBM Corporation. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/errno.h> |
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#include <linux/reboot.h> |
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#include <linux/slab.h> |
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#include <linux/stddef.h> |
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#include <linux/sched.h> |
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#include <linux/signal.h> |
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#include <linux/device.h> |
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#include <linux/spinlock.h> |
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#include <linux/irq.h> |
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#include <linux/interrupt.h> |
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#include <linux/kernel_stat.h> |
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#include <asm/irq.h> |
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#include <asm/io.h> |
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#include <asm/prom.h> |
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#include <asm/dcr.h> |
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#define NR_UIC_INTS 32 |
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#define UIC_SR 0x0 |
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#define UIC_ER 0x2 |
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#define UIC_CR 0x3 |
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#define UIC_PR 0x4 |
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#define UIC_TR 0x5 |
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#define UIC_MSR 0x6 |
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#define UIC_VR 0x7 |
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#define UIC_VCR 0x8 |
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struct uic *primary_uic; |
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struct uic { |
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int index; |
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int dcrbase; |
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raw_spinlock_t lock; |
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/* The remapper for this UIC */ |
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struct irq_domain *irqhost; |
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}; |
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static void uic_unmask_irq(struct irq_data *d) |
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{ |
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struct uic *uic = irq_data_get_irq_chip_data(d); |
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unsigned int src = irqd_to_hwirq(d); |
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unsigned long flags; |
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u32 er, sr; |
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sr = 1 << (31-src); |
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raw_spin_lock_irqsave(&uic->lock, flags); |
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/* ack level-triggered interrupts here */ |
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if (irqd_is_level_type(d)) |
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mtdcr(uic->dcrbase + UIC_SR, sr); |
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er = mfdcr(uic->dcrbase + UIC_ER); |
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er |= sr; |
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mtdcr(uic->dcrbase + UIC_ER, er); |
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raw_spin_unlock_irqrestore(&uic->lock, flags); |
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} |
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static void uic_mask_irq(struct irq_data *d) |
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{ |
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struct uic *uic = irq_data_get_irq_chip_data(d); |
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unsigned int src = irqd_to_hwirq(d); |
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unsigned long flags; |
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u32 er; |
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raw_spin_lock_irqsave(&uic->lock, flags); |
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er = mfdcr(uic->dcrbase + UIC_ER); |
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er &= ~(1 << (31 - src)); |
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mtdcr(uic->dcrbase + UIC_ER, er); |
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raw_spin_unlock_irqrestore(&uic->lock, flags); |
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} |
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static void uic_ack_irq(struct irq_data *d) |
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{ |
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struct uic *uic = irq_data_get_irq_chip_data(d); |
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unsigned int src = irqd_to_hwirq(d); |
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unsigned long flags; |
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raw_spin_lock_irqsave(&uic->lock, flags); |
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mtdcr(uic->dcrbase + UIC_SR, 1 << (31-src)); |
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raw_spin_unlock_irqrestore(&uic->lock, flags); |
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} |
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static void uic_mask_ack_irq(struct irq_data *d) |
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{ |
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struct uic *uic = irq_data_get_irq_chip_data(d); |
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unsigned int src = irqd_to_hwirq(d); |
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unsigned long flags; |
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u32 er, sr; |
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sr = 1 << (31-src); |
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raw_spin_lock_irqsave(&uic->lock, flags); |
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er = mfdcr(uic->dcrbase + UIC_ER); |
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er &= ~sr; |
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mtdcr(uic->dcrbase + UIC_ER, er); |
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/* On the UIC, acking (i.e. clearing the SR bit) |
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* a level irq will have no effect if the interrupt |
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* is still asserted by the device, even if |
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* the interrupt is already masked. Therefore |
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* we only ack the egde interrupts here, while |
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* level interrupts are ack'ed after the actual |
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* isr call in the uic_unmask_irq() |
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*/ |
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if (!irqd_is_level_type(d)) |
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mtdcr(uic->dcrbase + UIC_SR, sr); |
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raw_spin_unlock_irqrestore(&uic->lock, flags); |
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} |
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static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type) |
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{ |
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struct uic *uic = irq_data_get_irq_chip_data(d); |
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unsigned int src = irqd_to_hwirq(d); |
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unsigned long flags; |
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int trigger, polarity; |
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u32 tr, pr, mask; |
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switch (flow_type & IRQ_TYPE_SENSE_MASK) { |
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case IRQ_TYPE_NONE: |
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uic_mask_irq(d); |
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return 0; |
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case IRQ_TYPE_EDGE_RISING: |
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trigger = 1; polarity = 1; |
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break; |
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case IRQ_TYPE_EDGE_FALLING: |
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trigger = 1; polarity = 0; |
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break; |
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case IRQ_TYPE_LEVEL_HIGH: |
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trigger = 0; polarity = 1; |
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break; |
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case IRQ_TYPE_LEVEL_LOW: |
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trigger = 0; polarity = 0; |
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break; |
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default: |
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return -EINVAL; |
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} |
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mask = ~(1 << (31 - src)); |
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raw_spin_lock_irqsave(&uic->lock, flags); |
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tr = mfdcr(uic->dcrbase + UIC_TR); |
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pr = mfdcr(uic->dcrbase + UIC_PR); |
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tr = (tr & mask) | (trigger << (31-src)); |
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pr = (pr & mask) | (polarity << (31-src)); |
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mtdcr(uic->dcrbase + UIC_PR, pr); |
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mtdcr(uic->dcrbase + UIC_TR, tr); |
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mtdcr(uic->dcrbase + UIC_SR, ~mask); |
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raw_spin_unlock_irqrestore(&uic->lock, flags); |
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return 0; |
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} |
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static struct irq_chip uic_irq_chip = { |
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.name = "UIC", |
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.irq_unmask = uic_unmask_irq, |
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.irq_mask = uic_mask_irq, |
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.irq_mask_ack = uic_mask_ack_irq, |
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.irq_ack = uic_ack_irq, |
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.irq_set_type = uic_set_irq_type, |
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}; |
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static int uic_host_map(struct irq_domain *h, unsigned int virq, |
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irq_hw_number_t hw) |
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{ |
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struct uic *uic = h->host_data; |
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irq_set_chip_data(virq, uic); |
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/* Despite the name, handle_level_irq() works for both level |
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* and edge irqs on UIC. FIXME: check this is correct */ |
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irq_set_chip_and_handler(virq, &uic_irq_chip, handle_level_irq); |
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/* Set default irq type */ |
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irq_set_irq_type(virq, IRQ_TYPE_NONE); |
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return 0; |
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} |
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static const struct irq_domain_ops uic_host_ops = { |
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.map = uic_host_map, |
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.xlate = irq_domain_xlate_twocell, |
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}; |
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static void uic_irq_cascade(struct irq_desc *desc) |
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{ |
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struct irq_chip *chip = irq_desc_get_chip(desc); |
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struct irq_data *idata = irq_desc_get_irq_data(desc); |
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struct uic *uic = irq_desc_get_handler_data(desc); |
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u32 msr; |
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int src; |
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int subvirq; |
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raw_spin_lock(&desc->lock); |
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if (irqd_is_level_type(idata)) |
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chip->irq_mask(idata); |
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else |
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chip->irq_mask_ack(idata); |
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raw_spin_unlock(&desc->lock); |
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msr = mfdcr(uic->dcrbase + UIC_MSR); |
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if (!msr) /* spurious interrupt */ |
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goto uic_irq_ret; |
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src = 32 - ffs(msr); |
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subvirq = irq_linear_revmap(uic->irqhost, src); |
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generic_handle_irq(subvirq); |
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uic_irq_ret: |
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raw_spin_lock(&desc->lock); |
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if (irqd_is_level_type(idata)) |
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chip->irq_ack(idata); |
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if (!irqd_irq_disabled(idata) && chip->irq_unmask) |
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chip->irq_unmask(idata); |
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raw_spin_unlock(&desc->lock); |
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} |
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static struct uic * __init uic_init_one(struct device_node *node) |
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{ |
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struct uic *uic; |
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const u32 *indexp, *dcrreg; |
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int len; |
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BUG_ON(! of_device_is_compatible(node, "ibm,uic")); |
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uic = kzalloc(sizeof(*uic), GFP_KERNEL); |
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if (! uic) |
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return NULL; /* FIXME: panic? */ |
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raw_spin_lock_init(&uic->lock); |
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indexp = of_get_property(node, "cell-index", &len); |
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if (!indexp || (len != sizeof(u32))) { |
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printk(KERN_ERR "uic: Device node %pOF has missing or invalid " |
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"cell-index property\n", node); |
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return NULL; |
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} |
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uic->index = *indexp; |
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dcrreg = of_get_property(node, "dcr-reg", &len); |
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if (!dcrreg || (len != 2*sizeof(u32))) { |
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printk(KERN_ERR "uic: Device node %pOF has missing or invalid " |
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"dcr-reg property\n", node); |
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return NULL; |
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} |
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uic->dcrbase = *dcrreg; |
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uic->irqhost = irq_domain_add_linear(node, NR_UIC_INTS, &uic_host_ops, |
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uic); |
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if (! uic->irqhost) |
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return NULL; /* FIXME: panic? */ |
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/* Start with all interrupts disabled, level and non-critical */ |
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mtdcr(uic->dcrbase + UIC_ER, 0); |
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mtdcr(uic->dcrbase + UIC_CR, 0); |
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mtdcr(uic->dcrbase + UIC_TR, 0); |
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/* Clear any pending interrupts, in case the firmware left some */ |
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mtdcr(uic->dcrbase + UIC_SR, 0xffffffff); |
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printk ("UIC%d (%d IRQ sources) at DCR 0x%x\n", uic->index, |
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NR_UIC_INTS, uic->dcrbase); |
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return uic; |
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} |
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void __init uic_init_tree(void) |
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{ |
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struct device_node *np; |
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struct uic *uic; |
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const u32 *interrupts; |
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/* First locate and initialize the top-level UIC */ |
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for_each_compatible_node(np, NULL, "ibm,uic") { |
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interrupts = of_get_property(np, "interrupts", NULL); |
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if (!interrupts) |
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break; |
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} |
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BUG_ON(!np); /* uic_init_tree() assumes there's a UIC as the |
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* top-level interrupt controller */ |
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primary_uic = uic_init_one(np); |
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if (!primary_uic) |
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panic("Unable to initialize primary UIC %pOF\n", np); |
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irq_set_default_host(primary_uic->irqhost); |
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of_node_put(np); |
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/* The scan again for cascaded UICs */ |
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for_each_compatible_node(np, NULL, "ibm,uic") { |
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interrupts = of_get_property(np, "interrupts", NULL); |
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if (interrupts) { |
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/* Secondary UIC */ |
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int cascade_virq; |
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uic = uic_init_one(np); |
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if (! uic) |
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panic("Unable to initialize a secondary UIC %pOF\n", |
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np); |
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cascade_virq = irq_of_parse_and_map(np, 0); |
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irq_set_handler_data(cascade_virq, uic); |
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irq_set_chained_handler(cascade_virq, uic_irq_cascade); |
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/* FIXME: setup critical cascade?? */ |
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} |
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} |
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} |
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/* Return an interrupt vector or 0 if no interrupt is pending. */ |
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unsigned int uic_get_irq(void) |
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{ |
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u32 msr; |
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int src; |
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BUG_ON(! primary_uic); |
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msr = mfdcr(primary_uic->dcrbase + UIC_MSR); |
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src = 32 - ffs(msr); |
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return irq_linear_revmap(primary_uic->irqhost, src); |
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}
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