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227 lines
5.2 KiB
227 lines
5.2 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2006-2007 PA Semi, Inc |
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* |
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* Author: Shashi Rao, PA Semi |
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* |
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* Maintained by: Olof Johansson <[email protected]> |
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* |
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* Based on arch/powerpc/oprofile/op_model_power4.c |
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*/ |
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#include <linux/oprofile.h> |
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#include <linux/smp.h> |
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#include <linux/percpu.h> |
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#include <asm/processor.h> |
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#include <asm/cputable.h> |
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#include <asm/oprofile_impl.h> |
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#include <asm/reg.h> |
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static unsigned char oprofile_running; |
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/* mmcr values are set in pa6t_reg_setup, used in pa6t_cpu_setup */ |
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static u64 mmcr0_val; |
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static u64 mmcr1_val; |
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/* inited in pa6t_reg_setup */ |
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static u64 reset_value[OP_MAX_COUNTER]; |
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static inline u64 ctr_read(unsigned int i) |
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{ |
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switch (i) { |
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case 0: |
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return mfspr(SPRN_PA6T_PMC0); |
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case 1: |
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return mfspr(SPRN_PA6T_PMC1); |
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case 2: |
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return mfspr(SPRN_PA6T_PMC2); |
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case 3: |
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return mfspr(SPRN_PA6T_PMC3); |
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case 4: |
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return mfspr(SPRN_PA6T_PMC4); |
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case 5: |
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return mfspr(SPRN_PA6T_PMC5); |
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default: |
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printk(KERN_ERR "ctr_read called with bad arg %u\n", i); |
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return 0; |
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} |
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} |
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static inline void ctr_write(unsigned int i, u64 val) |
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{ |
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switch (i) { |
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case 0: |
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mtspr(SPRN_PA6T_PMC0, val); |
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break; |
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case 1: |
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mtspr(SPRN_PA6T_PMC1, val); |
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break; |
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case 2: |
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mtspr(SPRN_PA6T_PMC2, val); |
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break; |
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case 3: |
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mtspr(SPRN_PA6T_PMC3, val); |
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break; |
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case 4: |
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mtspr(SPRN_PA6T_PMC4, val); |
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break; |
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case 5: |
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mtspr(SPRN_PA6T_PMC5, val); |
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break; |
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default: |
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printk(KERN_ERR "ctr_write called with bad arg %u\n", i); |
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break; |
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} |
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} |
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/* precompute the values to stuff in the hardware registers */ |
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static int pa6t_reg_setup(struct op_counter_config *ctr, |
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struct op_system_config *sys, |
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int num_ctrs) |
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{ |
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int pmc; |
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/* |
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* adjust the mmcr0.en[0-5] and mmcr0.inten[0-5] values obtained from the |
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* event_mappings file by turning off the counters that the user doesn't |
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* care about |
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* |
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* setup user and kernel profiling |
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*/ |
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for (pmc = 0; pmc < cur_cpu_spec->num_pmcs; pmc++) |
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if (!ctr[pmc].enabled) { |
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sys->mmcr0 &= ~(0x1UL << pmc); |
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sys->mmcr0 &= ~(0x1UL << (pmc+12)); |
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pr_debug("turned off counter %u\n", pmc); |
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} |
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if (sys->enable_kernel) |
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sys->mmcr0 |= PA6T_MMCR0_SUPEN | PA6T_MMCR0_HYPEN; |
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else |
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sys->mmcr0 &= ~(PA6T_MMCR0_SUPEN | PA6T_MMCR0_HYPEN); |
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if (sys->enable_user) |
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sys->mmcr0 |= PA6T_MMCR0_PREN; |
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else |
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sys->mmcr0 &= ~PA6T_MMCR0_PREN; |
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/* |
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* The performance counter event settings are given in the mmcr0 and |
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* mmcr1 values passed from the user in the op_system_config |
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* structure (sys variable). |
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*/ |
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mmcr0_val = sys->mmcr0; |
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mmcr1_val = sys->mmcr1; |
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pr_debug("mmcr0_val inited to %016lx\n", sys->mmcr0); |
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pr_debug("mmcr1_val inited to %016lx\n", sys->mmcr1); |
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for (pmc = 0; pmc < cur_cpu_spec->num_pmcs; pmc++) { |
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/* counters are 40 bit. Move to cputable at some point? */ |
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reset_value[pmc] = (0x1UL << 39) - ctr[pmc].count; |
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pr_debug("reset_value for pmc%u inited to 0x%llx\n", |
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pmc, reset_value[pmc]); |
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} |
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return 0; |
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} |
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/* configure registers on this cpu */ |
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static int pa6t_cpu_setup(struct op_counter_config *ctr) |
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{ |
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u64 mmcr0 = mmcr0_val; |
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u64 mmcr1 = mmcr1_val; |
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/* Default is all PMCs off */ |
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mmcr0 &= ~(0x3FUL); |
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mtspr(SPRN_PA6T_MMCR0, mmcr0); |
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/* program selected programmable events in */ |
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mtspr(SPRN_PA6T_MMCR1, mmcr1); |
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pr_debug("setup on cpu %d, mmcr0 %016lx\n", smp_processor_id(), |
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mfspr(SPRN_PA6T_MMCR0)); |
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pr_debug("setup on cpu %d, mmcr1 %016lx\n", smp_processor_id(), |
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mfspr(SPRN_PA6T_MMCR1)); |
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return 0; |
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} |
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static int pa6t_start(struct op_counter_config *ctr) |
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{ |
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int i; |
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/* Hold off event counting until rfid */ |
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u64 mmcr0 = mmcr0_val | PA6T_MMCR0_HANDDIS; |
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for (i = 0; i < cur_cpu_spec->num_pmcs; i++) |
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if (ctr[i].enabled) |
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ctr_write(i, reset_value[i]); |
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else |
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ctr_write(i, 0UL); |
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mtspr(SPRN_PA6T_MMCR0, mmcr0); |
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oprofile_running = 1; |
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pr_debug("start on cpu %d, mmcr0 %llx\n", smp_processor_id(), mmcr0); |
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return 0; |
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} |
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static void pa6t_stop(void) |
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{ |
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u64 mmcr0; |
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/* freeze counters */ |
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mmcr0 = mfspr(SPRN_PA6T_MMCR0); |
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mmcr0 |= PA6T_MMCR0_FCM0; |
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mtspr(SPRN_PA6T_MMCR0, mmcr0); |
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oprofile_running = 0; |
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pr_debug("stop on cpu %d, mmcr0 %llx\n", smp_processor_id(), mmcr0); |
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} |
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/* handle the perfmon overflow vector */ |
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static void pa6t_handle_interrupt(struct pt_regs *regs, |
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struct op_counter_config *ctr) |
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{ |
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unsigned long pc = mfspr(SPRN_PA6T_SIAR); |
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int is_kernel = is_kernel_addr(pc); |
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u64 val; |
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int i; |
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u64 mmcr0; |
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/* disable perfmon counting until rfid */ |
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mmcr0 = mfspr(SPRN_PA6T_MMCR0); |
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mtspr(SPRN_PA6T_MMCR0, mmcr0 | PA6T_MMCR0_HANDDIS); |
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/* Record samples. We've got one global bit for whether a sample |
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* was taken, so add it for any counter that triggered overflow. |
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*/ |
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for (i = 0; i < cur_cpu_spec->num_pmcs; i++) { |
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val = ctr_read(i); |
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if (val & (0x1UL << 39)) { /* Overflow bit set */ |
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if (oprofile_running && ctr[i].enabled) { |
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if (mmcr0 & PA6T_MMCR0_SIARLOG) |
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oprofile_add_ext_sample(pc, regs, i, is_kernel); |
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ctr_write(i, reset_value[i]); |
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} else { |
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ctr_write(i, 0UL); |
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} |
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} |
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} |
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/* Restore mmcr0 to a good known value since the PMI changes it */ |
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mmcr0 = mmcr0_val | PA6T_MMCR0_HANDDIS; |
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mtspr(SPRN_PA6T_MMCR0, mmcr0); |
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} |
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struct op_powerpc_model op_model_pa6t = { |
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.reg_setup = pa6t_reg_setup, |
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.cpu_setup = pa6t_cpu_setup, |
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.start = pa6t_start, |
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.stop = pa6t_stop, |
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.handle_interrupt = pa6t_handle_interrupt, |
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};
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