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119 lines
3.9 KiB
119 lines
3.9 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright 2017 Paul Mackerras, IBM Corp. <[email protected]> |
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*/ |
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#include <linux/kvm_host.h> |
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#include <asm/kvm_ppc.h> |
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#include <asm/kvm_book3s.h> |
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#include <asm/kvm_book3s_64.h> |
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#include <asm/reg.h> |
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#include <asm/ppc-opcode.h> |
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/* |
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* This handles the cases where the guest is in real suspend mode |
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* and we want to get back to the guest without dooming the transaction. |
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* The caller has checked that the guest is in real-suspend mode |
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* (MSR[TS] = S and the fake-suspend flag is not set). |
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*/ |
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int kvmhv_p9_tm_emulation_early(struct kvm_vcpu *vcpu) |
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{ |
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u32 instr = vcpu->arch.emul_inst; |
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u64 newmsr, msr, bescr; |
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int rs; |
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/* |
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* rfid, rfebb, and mtmsrd encode bit 31 = 0 since it's a reserved bit |
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* in these instructions, so masking bit 31 out doesn't change these |
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* instructions. For the tsr. instruction if bit 31 = 0 then it is per |
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* ISA an invalid form, however P9 UM, in section 4.6.10 Book II Invalid |
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* Forms, informs specifically that ignoring bit 31 is an acceptable way |
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* to handle TM-related invalid forms that have bit 31 = 0. Moreover, |
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* for emulation purposes both forms (w/ and wo/ bit 31 set) can |
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* generate a softpatch interrupt. Hence both forms are handled below |
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* for tsr. to make them behave the same way. |
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*/ |
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switch (instr & PO_XOP_OPCODE_MASK) { |
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case PPC_INST_RFID: |
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/* XXX do we need to check for PR=0 here? */ |
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newmsr = vcpu->arch.shregs.srr1; |
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/* should only get here for Sx -> T1 transition */ |
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if (!(MSR_TM_TRANSACTIONAL(newmsr) && (newmsr & MSR_TM))) |
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return 0; |
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newmsr = sanitize_msr(newmsr); |
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vcpu->arch.shregs.msr = newmsr; |
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vcpu->arch.cfar = vcpu->arch.regs.nip - 4; |
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vcpu->arch.regs.nip = vcpu->arch.shregs.srr0; |
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return 1; |
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case PPC_INST_RFEBB: |
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/* check for PR=1 and arch 2.06 bit set in PCR */ |
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msr = vcpu->arch.shregs.msr; |
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if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206)) |
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return 0; |
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/* check EBB facility is available */ |
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if (!(vcpu->arch.hfscr & HFSCR_EBB) || |
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((msr & MSR_PR) && !(mfspr(SPRN_FSCR) & FSCR_EBB))) |
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return 0; |
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bescr = mfspr(SPRN_BESCR); |
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/* expect to see a S->T transition requested */ |
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if (((bescr >> 30) & 3) != 2) |
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return 0; |
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bescr &= ~BESCR_GE; |
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if (instr & (1 << 11)) |
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bescr |= BESCR_GE; |
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mtspr(SPRN_BESCR, bescr); |
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msr = (msr & ~MSR_TS_MASK) | MSR_TS_T; |
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vcpu->arch.shregs.msr = msr; |
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vcpu->arch.cfar = vcpu->arch.regs.nip - 4; |
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vcpu->arch.regs.nip = mfspr(SPRN_EBBRR); |
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return 1; |
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case PPC_INST_MTMSRD: |
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/* XXX do we need to check for PR=0 here? */ |
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rs = (instr >> 21) & 0x1f; |
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newmsr = kvmppc_get_gpr(vcpu, rs); |
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msr = vcpu->arch.shregs.msr; |
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/* check this is a Sx -> T1 transition */ |
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if (!(MSR_TM_TRANSACTIONAL(newmsr) && (newmsr & MSR_TM))) |
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return 0; |
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/* mtmsrd doesn't change LE */ |
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newmsr = (newmsr & ~MSR_LE) | (msr & MSR_LE); |
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newmsr = sanitize_msr(newmsr); |
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vcpu->arch.shregs.msr = newmsr; |
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return 1; |
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/* ignore bit 31, see comment above */ |
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case (PPC_INST_TSR & PO_XOP_OPCODE_MASK): |
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/* we know the MSR has the TS field = S (0b01) here */ |
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msr = vcpu->arch.shregs.msr; |
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/* check for PR=1 and arch 2.06 bit set in PCR */ |
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if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206)) |
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return 0; |
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/* check for TM disabled in the HFSCR or MSR */ |
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if (!(vcpu->arch.hfscr & HFSCR_TM) || !(msr & MSR_TM)) |
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return 0; |
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/* L=1 => tresume => set TS to T (0b10) */ |
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if (instr & (1 << 21)) |
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vcpu->arch.shregs.msr = (msr & ~MSR_TS_MASK) | MSR_TS_T; |
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/* Set CR0 to 0b0010 */ |
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vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) | |
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0x20000000; |
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return 1; |
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} |
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return 0; |
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} |
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/* |
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* This is called when we are returning to a guest in TM transactional |
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* state. We roll the guest state back to the checkpointed state. |
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*/ |
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void kvmhv_emulate_tm_rollback(struct kvm_vcpu *vcpu) |
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{ |
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vcpu->arch.shregs.msr &= ~MSR_TS_MASK; /* go to N state */ |
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vcpu->arch.regs.nip = vcpu->arch.tfhar; |
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copy_from_checkpoint(vcpu); |
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vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) | 0xa0000000; |
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}
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