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68 lines
1.9 KiB
68 lines
1.9 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _ASM_POWERPC_MMU_40X_H_ |
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#define _ASM_POWERPC_MMU_40X_H_ |
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/* |
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* PPC40x support |
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*/ |
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#define PPC40X_TLB_SIZE 64 |
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/* |
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* TLB entries are defined by a "high" tag portion and a "low" data |
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* portion. On all architectures, the data portion is 32-bits. |
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* |
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* TLB entries are managed entirely under software control by reading, |
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* writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx |
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* instructions. |
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*/ |
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#define TLB_LO 1 |
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#define TLB_HI 0 |
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#define TLB_DATA TLB_LO |
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#define TLB_TAG TLB_HI |
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/* Tag portion */ |
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#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ |
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#define TLB_PAGESZ_MASK 0x00000380 |
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#define TLB_PAGESZ(x) (((x) & 0x7) << 7) |
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#define PAGESZ_1K 0 |
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#define PAGESZ_4K 1 |
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#define PAGESZ_16K 2 |
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#define PAGESZ_64K 3 |
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#define PAGESZ_256K 4 |
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#define PAGESZ_1M 5 |
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#define PAGESZ_4M 6 |
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#define PAGESZ_16M 7 |
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#define TLB_VALID 0x00000040 /* Entry is valid */ |
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/* Data portion */ |
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#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ |
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#define TLB_PERM_MASK 0x00000300 |
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#define TLB_EX 0x00000200 /* Instruction execution allowed */ |
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#define TLB_WR 0x00000100 /* Writes permitted */ |
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#define TLB_ZSEL_MASK 0x000000F0 |
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#define TLB_ZSEL(x) (((x) & 0xF) << 4) |
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#define TLB_ATTR_MASK 0x0000000F |
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#define TLB_W 0x00000008 /* Caching is write-through */ |
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#define TLB_I 0x00000004 /* Caching is inhibited */ |
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#define TLB_M 0x00000002 /* Memory is coherent */ |
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#define TLB_G 0x00000001 /* Memory is guarded from prefetch */ |
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#ifndef __ASSEMBLY__ |
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typedef struct { |
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unsigned int id; |
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unsigned int active; |
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unsigned long vdso_base; |
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} mm_context_t; |
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#endif /* !__ASSEMBLY__ */ |
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#define mmu_virtual_psize MMU_PAGE_4K |
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#define mmu_linear_psize MMU_PAGE_256M |
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#endif /* _ASM_POWERPC_MMU_40X_H_ */
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