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648 lines
10 KiB
648 lines
10 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* CPM2 Internal Memory Map |
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* Copyright (c) 1999 Dan Malek ([email protected]) |
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* |
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* The Internal Memory Map for devices with CPM2 on them. This |
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* is the superset of all CPM2 devices (8260, 8266, 8280, 8272, |
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* 8560). |
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*/ |
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#ifdef __KERNEL__ |
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#ifndef __IMMAP_CPM2__ |
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#define __IMMAP_CPM2__ |
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#include <linux/types.h> |
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/* System configuration registers. |
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*/ |
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typedef struct sys_82xx_conf { |
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u32 sc_siumcr; |
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u32 sc_sypcr; |
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u8 res1[6]; |
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u16 sc_swsr; |
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u8 res2[20]; |
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u32 sc_bcr; |
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u8 sc_ppc_acr; |
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u8 res3[3]; |
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u32 sc_ppc_alrh; |
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u32 sc_ppc_alrl; |
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u8 sc_lcl_acr; |
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u8 res4[3]; |
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u32 sc_lcl_alrh; |
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u32 sc_lcl_alrl; |
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u32 sc_tescr1; |
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u32 sc_tescr2; |
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u32 sc_ltescr1; |
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u32 sc_ltescr2; |
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u32 sc_pdtea; |
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u8 sc_pdtem; |
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u8 res5[3]; |
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u32 sc_ldtea; |
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u8 sc_ldtem; |
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u8 res6[163]; |
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} sysconf_82xx_cpm2_t; |
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typedef struct sys_85xx_conf { |
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u32 sc_cear; |
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u16 sc_ceer; |
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u16 sc_cemr; |
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u8 res1[70]; |
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u32 sc_smaer; |
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u8 res2[4]; |
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u32 sc_smevr; |
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u32 sc_smctr; |
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u32 sc_lmaer; |
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u8 res3[4]; |
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u32 sc_lmevr; |
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u32 sc_lmctr; |
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u8 res4[144]; |
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} sysconf_85xx_cpm2_t; |
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typedef union sys_conf { |
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sysconf_82xx_cpm2_t siu_82xx; |
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sysconf_85xx_cpm2_t siu_85xx; |
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} sysconf_cpm2_t; |
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/* Memory controller registers. |
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*/ |
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typedef struct mem_ctlr { |
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u32 memc_br0; |
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u32 memc_or0; |
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u32 memc_br1; |
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u32 memc_or1; |
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u32 memc_br2; |
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u32 memc_or2; |
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u32 memc_br3; |
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u32 memc_or3; |
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u32 memc_br4; |
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u32 memc_or4; |
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u32 memc_br5; |
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u32 memc_or5; |
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u32 memc_br6; |
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u32 memc_or6; |
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u32 memc_br7; |
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u32 memc_or7; |
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u32 memc_br8; |
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u32 memc_or8; |
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u32 memc_br9; |
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u32 memc_or9; |
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u32 memc_br10; |
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u32 memc_or10; |
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u32 memc_br11; |
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u32 memc_or11; |
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u8 res1[8]; |
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u32 memc_mar; |
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u8 res2[4]; |
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u32 memc_mamr; |
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u32 memc_mbmr; |
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u32 memc_mcmr; |
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u8 res3[8]; |
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u16 memc_mptpr; |
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u8 res4[2]; |
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u32 memc_mdr; |
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u8 res5[4]; |
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u32 memc_psdmr; |
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u32 memc_lsdmr; |
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u8 memc_purt; |
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u8 res6[3]; |
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u8 memc_psrt; |
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u8 res7[3]; |
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u8 memc_lurt; |
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u8 res8[3]; |
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u8 memc_lsrt; |
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u8 res9[3]; |
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u32 memc_immr; |
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u32 memc_pcibr0; |
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u32 memc_pcibr1; |
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u8 res10[16]; |
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u32 memc_pcimsk0; |
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u32 memc_pcimsk1; |
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u8 res11[52]; |
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} memctl_cpm2_t; |
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/* System Integration Timers. |
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*/ |
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typedef struct sys_int_timers { |
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u8 res1[32]; |
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u16 sit_tmcntsc; |
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u8 res2[2]; |
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u32 sit_tmcnt; |
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u8 res3[4]; |
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u32 sit_tmcntal; |
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u8 res4[16]; |
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u16 sit_piscr; |
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u8 res5[2]; |
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u32 sit_pitc; |
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u32 sit_pitr; |
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u8 res6[94]; |
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u8 res7[390]; |
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} sit_cpm2_t; |
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#define PISCR_PIRQ_MASK ((u16)0xff00) |
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#define PISCR_PS ((u16)0x0080) |
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#define PISCR_PIE ((u16)0x0004) |
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#define PISCR_PTF ((u16)0x0002) |
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#define PISCR_PTE ((u16)0x0001) |
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/* PCI Controller. |
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*/ |
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typedef struct pci_ctlr { |
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u32 pci_omisr; |
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u32 pci_omimr; |
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u8 res1[8]; |
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u32 pci_ifqpr; |
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u32 pci_ofqpr; |
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u8 res2[8]; |
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u32 pci_imr0; |
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u32 pci_imr1; |
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u32 pci_omr0; |
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u32 pci_omr1; |
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u32 pci_odr; |
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u8 res3[4]; |
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u32 pci_idr; |
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u8 res4[20]; |
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u32 pci_imisr; |
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u32 pci_imimr; |
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u8 res5[24]; |
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u32 pci_ifhpr; |
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u8 res6[4]; |
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u32 pci_iftpr; |
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u8 res7[4]; |
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u32 pci_iphpr; |
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u8 res8[4]; |
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u32 pci_iptpr; |
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u8 res9[4]; |
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u32 pci_ofhpr; |
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u8 res10[4]; |
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u32 pci_oftpr; |
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u8 res11[4]; |
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u32 pci_ophpr; |
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u8 res12[4]; |
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u32 pci_optpr; |
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u8 res13[8]; |
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u32 pci_mucr; |
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u8 res14[8]; |
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u32 pci_qbar; |
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u8 res15[12]; |
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u32 pci_dmamr0; |
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u32 pci_dmasr0; |
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u32 pci_dmacdar0; |
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u8 res16[4]; |
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u32 pci_dmasar0; |
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u8 res17[4]; |
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u32 pci_dmadar0; |
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u8 res18[4]; |
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u32 pci_dmabcr0; |
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u32 pci_dmandar0; |
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u8 res19[86]; |
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u32 pci_dmamr1; |
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u32 pci_dmasr1; |
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u32 pci_dmacdar1; |
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u8 res20[4]; |
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u32 pci_dmasar1; |
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u8 res21[4]; |
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u32 pci_dmadar1; |
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u8 res22[4]; |
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u32 pci_dmabcr1; |
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u32 pci_dmandar1; |
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u8 res23[88]; |
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u32 pci_dmamr2; |
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u32 pci_dmasr2; |
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u32 pci_dmacdar2; |
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u8 res24[4]; |
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u32 pci_dmasar2; |
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u8 res25[4]; |
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u32 pci_dmadar2; |
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u8 res26[4]; |
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u32 pci_dmabcr2; |
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u32 pci_dmandar2; |
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u8 res27[88]; |
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u32 pci_dmamr3; |
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u32 pci_dmasr3; |
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u32 pci_dmacdar3; |
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u8 res28[4]; |
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u32 pci_dmasar3; |
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u8 res29[4]; |
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u32 pci_dmadar3; |
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u8 res30[4]; |
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u32 pci_dmabcr3; |
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u32 pci_dmandar3; |
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u8 res31[344]; |
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u32 pci_potar0; |
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u8 res32[4]; |
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u32 pci_pobar0; |
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u8 res33[4]; |
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u32 pci_pocmr0; |
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u8 res34[4]; |
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u32 pci_potar1; |
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u8 res35[4]; |
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u32 pci_pobar1; |
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u8 res36[4]; |
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u32 pci_pocmr1; |
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u8 res37[4]; |
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u32 pci_potar2; |
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u8 res38[4]; |
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u32 pci_pobar2; |
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u8 res39[4]; |
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u32 pci_pocmr2; |
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u8 res40[50]; |
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u32 pci_ptcr; |
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u32 pci_gpcr; |
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u32 pci_gcr; |
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u32 pci_esr; |
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u32 pci_emr; |
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u32 pci_ecr; |
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u32 pci_eacr; |
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u8 res41[4]; |
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u32 pci_edcr; |
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u8 res42[4]; |
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u32 pci_eccr; |
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u8 res43[44]; |
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u32 pci_pitar1; |
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u8 res44[4]; |
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u32 pci_pibar1; |
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u8 res45[4]; |
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u32 pci_picmr1; |
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u8 res46[4]; |
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u32 pci_pitar0; |
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u8 res47[4]; |
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u32 pci_pibar0; |
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u8 res48[4]; |
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u32 pci_picmr0; |
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u8 res49[4]; |
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u32 pci_cfg_addr; |
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u32 pci_cfg_data; |
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u32 pci_int_ack; |
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u8 res50[756]; |
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} pci_cpm2_t; |
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/* Interrupt Controller. |
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*/ |
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typedef struct interrupt_controller { |
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u16 ic_sicr; |
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u8 res1[2]; |
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u32 ic_sivec; |
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u32 ic_sipnrh; |
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u32 ic_sipnrl; |
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u32 ic_siprr; |
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u32 ic_scprrh; |
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u32 ic_scprrl; |
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u32 ic_simrh; |
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u32 ic_simrl; |
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u32 ic_siexr; |
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u8 res2[88]; |
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} intctl_cpm2_t; |
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/* Clocks and Reset. |
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*/ |
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typedef struct clk_and_reset { |
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u32 car_sccr; |
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u8 res1[4]; |
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u32 car_scmr; |
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u8 res2[4]; |
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u32 car_rsr; |
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u32 car_rmr; |
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u8 res[104]; |
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} car_cpm2_t; |
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/* Input/Output Port control/status registers. |
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* Names consistent with processor manual, although they are different |
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* from the original 8xx names....... |
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*/ |
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typedef struct io_port { |
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u32 iop_pdira; |
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u32 iop_ppara; |
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u32 iop_psora; |
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u32 iop_podra; |
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u32 iop_pdata; |
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u8 res1[12]; |
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u32 iop_pdirb; |
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u32 iop_pparb; |
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u32 iop_psorb; |
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u32 iop_podrb; |
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u32 iop_pdatb; |
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u8 res2[12]; |
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u32 iop_pdirc; |
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u32 iop_pparc; |
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u32 iop_psorc; |
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u32 iop_podrc; |
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u32 iop_pdatc; |
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u8 res3[12]; |
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u32 iop_pdird; |
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u32 iop_ppard; |
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u32 iop_psord; |
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u32 iop_podrd; |
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u32 iop_pdatd; |
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u8 res4[12]; |
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} iop_cpm2_t; |
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/* Communication Processor Module Timers |
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*/ |
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typedef struct cpm_timers { |
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u8 cpmt_tgcr1; |
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u8 res1[3]; |
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u8 cpmt_tgcr2; |
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u8 res2[11]; |
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u16 cpmt_tmr1; |
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u16 cpmt_tmr2; |
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u16 cpmt_trr1; |
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u16 cpmt_trr2; |
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u16 cpmt_tcr1; |
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u16 cpmt_tcr2; |
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u16 cpmt_tcn1; |
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u16 cpmt_tcn2; |
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u16 cpmt_tmr3; |
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u16 cpmt_tmr4; |
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u16 cpmt_trr3; |
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u16 cpmt_trr4; |
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u16 cpmt_tcr3; |
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u16 cpmt_tcr4; |
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u16 cpmt_tcn3; |
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u16 cpmt_tcn4; |
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u16 cpmt_ter1; |
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u16 cpmt_ter2; |
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u16 cpmt_ter3; |
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u16 cpmt_ter4; |
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u8 res3[584]; |
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} cpmtimer_cpm2_t; |
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/* DMA control/status registers. |
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*/ |
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typedef struct sdma_csr { |
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u8 res0[24]; |
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u8 sdma_sdsr; |
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u8 res1[3]; |
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u8 sdma_sdmr; |
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u8 res2[3]; |
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u8 sdma_idsr1; |
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u8 res3[3]; |
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u8 sdma_idmr1; |
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u8 res4[3]; |
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u8 sdma_idsr2; |
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u8 res5[3]; |
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u8 sdma_idmr2; |
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u8 res6[3]; |
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u8 sdma_idsr3; |
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u8 res7[3]; |
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u8 sdma_idmr3; |
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u8 res8[3]; |
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u8 sdma_idsr4; |
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u8 res9[3]; |
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u8 sdma_idmr4; |
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u8 res10[707]; |
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} sdma_cpm2_t; |
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/* Fast controllers |
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*/ |
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typedef struct fcc { |
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u32 fcc_gfmr; |
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u32 fcc_fpsmr; |
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u16 fcc_ftodr; |
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u8 res1[2]; |
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u16 fcc_fdsr; |
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u8 res2[2]; |
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u16 fcc_fcce; |
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u8 res3[2]; |
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u16 fcc_fccm; |
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u8 res4[2]; |
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u8 fcc_fccs; |
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u8 res5[3]; |
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u8 fcc_ftirr_phy[4]; |
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} fcc_t; |
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/* Fast controllers continued |
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*/ |
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typedef struct fcc_c { |
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u32 fcc_firper; |
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u32 fcc_firer; |
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u32 fcc_firsr_hi; |
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u32 fcc_firsr_lo; |
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u8 fcc_gfemr; |
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u8 res1[15]; |
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} fcc_c_t; |
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/* TC Layer |
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*/ |
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typedef struct tclayer { |
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u16 tc_tcmode; |
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u16 tc_cdsmr; |
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u16 tc_tcer; |
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u16 tc_rcc; |
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u16 tc_tcmr; |
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u16 tc_fcc; |
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u16 tc_ccc; |
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u16 tc_icc; |
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u16 tc_tcc; |
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u16 tc_ecc; |
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u8 res1[12]; |
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} tclayer_t; |
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/* I2C |
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*/ |
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typedef struct i2c { |
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u8 i2c_i2mod; |
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u8 res1[3]; |
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u8 i2c_i2add; |
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u8 res2[3]; |
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u8 i2c_i2brg; |
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u8 res3[3]; |
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u8 i2c_i2com; |
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u8 res4[3]; |
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u8 i2c_i2cer; |
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u8 res5[3]; |
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u8 i2c_i2cmr; |
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u8 res6[331]; |
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} i2c_cpm2_t; |
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typedef struct scc { /* Serial communication channels */ |
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u32 scc_gsmrl; |
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u32 scc_gsmrh; |
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u16 scc_psmr; |
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u8 res1[2]; |
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u16 scc_todr; |
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u16 scc_dsr; |
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u16 scc_scce; |
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u8 res2[2]; |
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u16 scc_sccm; |
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u8 res3; |
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u8 scc_sccs; |
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u8 res4[8]; |
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} scc_t; |
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typedef struct smc { /* Serial management channels */ |
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u8 res1[2]; |
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u16 smc_smcmr; |
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u8 res2[2]; |
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u8 smc_smce; |
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u8 res3[3]; |
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u8 smc_smcm; |
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u8 res4[5]; |
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} smc_t; |
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/* Serial Peripheral Interface. |
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*/ |
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typedef struct spi_ctrl { |
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u16 spi_spmode; |
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u8 res1[4]; |
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u8 spi_spie; |
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u8 res2[3]; |
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u8 spi_spim; |
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u8 res3[2]; |
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u8 spi_spcom; |
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u8 res4[82]; |
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} spictl_cpm2_t; |
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/* CPM Mux. |
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*/ |
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typedef struct cpmux { |
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u8 cmx_si1cr; |
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u8 res1; |
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u8 cmx_si2cr; |
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u8 res2; |
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u32 cmx_fcr; |
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u32 cmx_scr; |
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u8 cmx_smr; |
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u8 res3; |
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u16 cmx_uar; |
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u8 res4[16]; |
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} cpmux_t; |
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/* SIRAM control |
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*/ |
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typedef struct siram { |
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u16 si_amr; |
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u16 si_bmr; |
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u16 si_cmr; |
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u16 si_dmr; |
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u8 si_gmr; |
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u8 res1; |
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u8 si_cmdr; |
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u8 res2; |
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u8 si_str; |
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u8 res3; |
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u16 si_rsr; |
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} siramctl_t; |
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typedef struct mcc { |
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u16 mcc_mcce; |
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u8 res1[2]; |
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u16 mcc_mccm; |
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u8 res2[2]; |
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u8 mcc_mccf; |
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u8 res3[7]; |
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} mcc_t; |
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typedef struct comm_proc { |
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u32 cp_cpcr; |
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u32 cp_rccr; |
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u8 res1[14]; |
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u16 cp_rter; |
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u8 res2[2]; |
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u16 cp_rtmr; |
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u16 cp_rtscr; |
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u8 res3[2]; |
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u32 cp_rtsr; |
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u8 res4[12]; |
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} cpm_cpm2_t; |
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/* USB Controller. |
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*/ |
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typedef struct cpm_usb_ctlr { |
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u8 usb_usmod; |
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u8 usb_usadr; |
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u8 usb_uscom; |
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u8 res1[1]; |
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__be16 usb_usep[4]; |
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u8 res2[4]; |
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__be16 usb_usber; |
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u8 res3[2]; |
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__be16 usb_usbmr; |
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u8 usb_usbs; |
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u8 res4[7]; |
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} usb_cpm2_t; |
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/* ...and the whole thing wrapped up.... |
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*/ |
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typedef struct immap { |
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/* Some references are into the unique and known dpram spaces, |
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* others are from the generic base. |
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*/ |
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#define im_dprambase im_dpram1 |
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u8 im_dpram1[16*1024]; |
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u8 res1[16*1024]; |
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u8 im_dpram2[4*1024]; |
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u8 res2[8*1024]; |
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u8 im_dpram3[4*1024]; |
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u8 res3[16*1024]; |
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sysconf_cpm2_t im_siu_conf; /* SIU Configuration */ |
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memctl_cpm2_t im_memctl; /* Memory Controller */ |
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sit_cpm2_t im_sit; /* System Integration Timers */ |
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pci_cpm2_t im_pci; /* PCI Controller */ |
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intctl_cpm2_t im_intctl; /* Interrupt Controller */ |
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car_cpm2_t im_clkrst; /* Clocks and reset */ |
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iop_cpm2_t im_ioport; /* IO Port control/status */ |
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cpmtimer_cpm2_t im_cpmtimer; /* CPM timers */ |
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sdma_cpm2_t im_sdma; /* SDMA control/status */ |
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fcc_t im_fcc[3]; /* Three FCCs */ |
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u8 res4z[32]; |
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fcc_c_t im_fcc_c[3]; /* Continued FCCs */ |
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u8 res4[32]; |
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tclayer_t im_tclayer[8]; /* Eight TCLayers */ |
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u16 tc_tcgsr; |
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u16 tc_tcger; |
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/* First set of baud rate generators. |
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*/ |
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u8 res[236]; |
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u32 im_brgc5; |
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u32 im_brgc6; |
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u32 im_brgc7; |
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u32 im_brgc8; |
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u8 res5[608]; |
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i2c_cpm2_t im_i2c; /* I2C control/status */ |
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cpm_cpm2_t im_cpm; /* Communication processor */ |
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/* Second set of baud rate generators. |
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*/ |
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u32 im_brgc1; |
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u32 im_brgc2; |
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u32 im_brgc3; |
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u32 im_brgc4; |
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scc_t im_scc[4]; /* Four SCCs */ |
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smc_t im_smc[2]; /* Couple of SMCs */ |
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spictl_cpm2_t im_spi; /* A SPI */ |
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cpmux_t im_cpmux; /* CPM clock route mux */ |
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siramctl_t im_siramctl1; /* First SI RAM Control */ |
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mcc_t im_mcc1; /* First MCC */ |
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siramctl_t im_siramctl2; /* Second SI RAM Control */ |
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mcc_t im_mcc2; /* Second MCC */ |
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usb_cpm2_t im_usb; /* USB Controller */ |
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u8 res6[1153]; |
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u16 im_si1txram[256]; |
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u8 res7[512]; |
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u16 im_si1rxram[256]; |
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u8 res8[512]; |
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u16 im_si2txram[256]; |
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u8 res9[512]; |
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u16 im_si2rxram[256]; |
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u8 res10[512]; |
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u8 res11[4096]; |
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} cpm2_map_t; |
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extern cpm2_map_t __iomem *cpm2_immr; |
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#endif /* __IMMAP_CPM2__ */ |
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#endif /* __KERNEL__ */
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