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629 lines
24 KiB
629 lines
24 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __ASM_POWERPC_CPUTABLE_H |
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#define __ASM_POWERPC_CPUTABLE_H |
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#include <linux/types.h> |
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#include <uapi/asm/cputable.h> |
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#include <asm/asm-const.h> |
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#ifndef __ASSEMBLY__ |
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/* This structure can grow, it's real size is used by head.S code |
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* via the mkdefs mechanism. |
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*/ |
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struct cpu_spec; |
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typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec); |
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typedef void (*cpu_restore_t)(void); |
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enum powerpc_oprofile_type { |
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PPC_OPROFILE_INVALID = 0, |
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PPC_OPROFILE_RS64 = 1, |
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PPC_OPROFILE_POWER4 = 2, |
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PPC_OPROFILE_G4 = 3, |
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PPC_OPROFILE_FSL_EMB = 4, |
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PPC_OPROFILE_CELL = 5, |
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PPC_OPROFILE_PA6T = 6, |
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}; |
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enum powerpc_pmc_type { |
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PPC_PMC_DEFAULT = 0, |
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PPC_PMC_IBM = 1, |
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PPC_PMC_PA6T = 2, |
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PPC_PMC_G4 = 3, |
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}; |
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struct pt_regs; |
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extern int machine_check_generic(struct pt_regs *regs); |
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extern int machine_check_4xx(struct pt_regs *regs); |
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extern int machine_check_440A(struct pt_regs *regs); |
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extern int machine_check_e500mc(struct pt_regs *regs); |
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extern int machine_check_e500(struct pt_regs *regs); |
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extern int machine_check_e200(struct pt_regs *regs); |
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extern int machine_check_47x(struct pt_regs *regs); |
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int machine_check_8xx(struct pt_regs *regs); |
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int machine_check_83xx(struct pt_regs *regs); |
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extern void cpu_down_flush_e500v2(void); |
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extern void cpu_down_flush_e500mc(void); |
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extern void cpu_down_flush_e5500(void); |
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extern void cpu_down_flush_e6500(void); |
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/* NOTE WELL: Update identify_cpu() if fields are added or removed! */ |
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struct cpu_spec { |
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/* CPU is matched via (PVR & pvr_mask) == pvr_value */ |
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unsigned int pvr_mask; |
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unsigned int pvr_value; |
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char *cpu_name; |
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unsigned long cpu_features; /* Kernel features */ |
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unsigned int cpu_user_features; /* Userland features */ |
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unsigned int cpu_user_features2; /* Userland features v2 */ |
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unsigned int mmu_features; /* MMU features */ |
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/* cache line sizes */ |
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unsigned int icache_bsize; |
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unsigned int dcache_bsize; |
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/* flush caches inside the current cpu */ |
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void (*cpu_down_flush)(void); |
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/* number of performance monitor counters */ |
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unsigned int num_pmcs; |
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enum powerpc_pmc_type pmc_type; |
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/* this is called to initialize various CPU bits like L1 cache, |
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* BHT, SPD, etc... from head.S before branching to identify_machine |
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*/ |
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cpu_setup_t cpu_setup; |
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/* Used to restore cpu setup on secondary processors and at resume */ |
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cpu_restore_t cpu_restore; |
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/* Used by oprofile userspace to select the right counters */ |
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char *oprofile_cpu_type; |
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/* Processor specific oprofile operations */ |
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enum powerpc_oprofile_type oprofile_type; |
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/* Bit locations inside the mmcra change */ |
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unsigned long oprofile_mmcra_sihv; |
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unsigned long oprofile_mmcra_sipr; |
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/* Bits to clear during an oprofile exception */ |
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unsigned long oprofile_mmcra_clear; |
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/* Name of processor class, for the ELF AT_PLATFORM entry */ |
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char *platform; |
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/* Processor specific machine check handling. Return negative |
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* if the error is fatal, 1 if it was fully recovered and 0 to |
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* pass up (not CPU originated) */ |
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int (*machine_check)(struct pt_regs *regs); |
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/* |
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* Processor specific early machine check handler which is |
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* called in real mode to handle SLB and TLB errors. |
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*/ |
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long (*machine_check_early)(struct pt_regs *regs); |
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}; |
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extern struct cpu_spec *cur_cpu_spec; |
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extern unsigned int __start___ftr_fixup, __stop___ftr_fixup; |
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extern void set_cur_cpu_spec(struct cpu_spec *s); |
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extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr); |
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extern void identify_cpu_name(unsigned int pvr); |
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extern void do_feature_fixups(unsigned long value, void *fixup_start, |
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void *fixup_end); |
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extern const char *powerpc_base_platform; |
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#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS |
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extern void cpu_feature_keys_init(void); |
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#else |
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static inline void cpu_feature_keys_init(void) { } |
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#endif |
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#endif /* __ASSEMBLY__ */ |
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/* CPU kernel features */ |
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/* Definitions for features that we have on both 32-bit and 64-bit chips */ |
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#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001) |
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#define CPU_FTR_ALTIVEC ASM_CONST(0x00000002) |
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#define CPU_FTR_DBELL ASM_CONST(0x00000004) |
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#define CPU_FTR_CAN_NAP ASM_CONST(0x00000008) |
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#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00000010) |
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#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00000020) |
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#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00000040) |
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#define CPU_FTR_LWSYNC ASM_CONST(0x00000080) |
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#define CPU_FTR_NOEXECUTE ASM_CONST(0x00000100) |
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#define CPU_FTR_EMB_HV ASM_CONST(0x00000200) |
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/* Definitions for features that only exist on 32-bit chips */ |
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#ifdef CONFIG_PPC32 |
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#define CPU_FTR_L2CR ASM_CONST(0x00002000) |
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#define CPU_FTR_SPEC7450 ASM_CONST(0x00004000) |
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#define CPU_FTR_TAU ASM_CONST(0x00008000) |
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#define CPU_FTR_CAN_DOZE ASM_CONST(0x00010000) |
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#define CPU_FTR_L3CR ASM_CONST(0x00040000) |
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#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00080000) |
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#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00100000) |
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#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00200000) |
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#define CPU_FTR_NO_DPM ASM_CONST(0x00400000) |
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#define CPU_FTR_476_DD2 ASM_CONST(0x00800000) |
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#define CPU_FTR_NEED_COHERENT ASM_CONST(0x01000000) |
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#define CPU_FTR_NO_BTIC ASM_CONST(0x02000000) |
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#define CPU_FTR_PPC_LE ASM_CONST(0x04000000) |
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#define CPU_FTR_SPE ASM_CONST(0x10000000) |
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#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x20000000) |
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#define CPU_FTR_INDEXED_DCR ASM_CONST(0x40000000) |
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#else /* CONFIG_PPC32 */ |
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/* Define these to 0 for the sake of tests in common code */ |
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#define CPU_FTR_PPC_LE (0) |
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#define CPU_FTR_SPE (0) |
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#endif |
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/* |
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* Definitions for the 64-bit processor unique features; |
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* on 32-bit, make the names available but defined to be 0. |
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*/ |
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#ifdef __powerpc64__ |
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#define LONG_ASM_CONST(x) ASM_CONST(x) |
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#else |
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#define LONG_ASM_CONST(x) 0 |
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#endif |
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#define CPU_FTR_REAL_LE LONG_ASM_CONST(0x0000000000001000) |
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#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000000002000) |
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#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000000008000) |
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#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000000010000) |
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#define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000000000020000) |
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#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000000000040000) |
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#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000000000080000) |
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#define CPU_FTR_SMT LONG_ASM_CONST(0x0000000000100000) |
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#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000000000200000) |
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#define CPU_FTR_PURR LONG_ASM_CONST(0x0000000000400000) |
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#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000000000800000) |
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#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000000001000000) |
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#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000000002000000) |
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#define CPU_FTR_VSX LONG_ASM_CONST(0x0000000004000000) |
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#define CPU_FTR_SAO LONG_ASM_CONST(0x0000000008000000) |
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#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000000010000000) |
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#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0000000020000000) |
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#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0000000040000000) |
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#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0000000080000000) |
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#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0000000100000000) |
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#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0000000200000000) |
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/* LONG_ASM_CONST(0x0000000400000000) Free */ |
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#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0000000800000000) |
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#define CPU_FTR_TM LONG_ASM_CONST(0x0000001000000000) |
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#define CPU_FTR_CFAR LONG_ASM_CONST(0x0000002000000000) |
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#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0000004000000000) |
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#define CPU_FTR_DAWR LONG_ASM_CONST(0x0000008000000000) |
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#define CPU_FTR_DABRX LONG_ASM_CONST(0x0000010000000000) |
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#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x0000020000000000) |
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#define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000) |
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#define CPU_FTR_P9_TM_HV_ASSIST LONG_ASM_CONST(0x0000100000000000) |
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#define CPU_FTR_P9_TM_XER_SO_BUG LONG_ASM_CONST(0x0000200000000000) |
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#define CPU_FTR_P9_TLBIE_STQ_BUG LONG_ASM_CONST(0x0000400000000000) |
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#define CPU_FTR_P9_TIDR LONG_ASM_CONST(0x0000800000000000) |
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#define CPU_FTR_P9_TLBIE_ERAT_BUG LONG_ASM_CONST(0x0001000000000000) |
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#define CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002000000000000) |
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#define CPU_FTR_ARCH_31 LONG_ASM_CONST(0x0004000000000000) |
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#define CPU_FTR_DAWR1 LONG_ASM_CONST(0x0008000000000000) |
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#ifndef __ASSEMBLY__ |
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#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN) |
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#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE) |
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/* We only set the altivec features if the kernel was compiled with altivec |
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* support |
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*/ |
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#ifdef CONFIG_ALTIVEC |
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#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC |
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#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC |
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#else |
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#define CPU_FTR_ALTIVEC_COMP 0 |
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#define PPC_FEATURE_HAS_ALTIVEC_COMP 0 |
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#endif |
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/* We only set the VSX features if the kernel was compiled with VSX |
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* support |
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*/ |
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#ifdef CONFIG_VSX |
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#define CPU_FTR_VSX_COMP CPU_FTR_VSX |
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#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX |
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#else |
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#define CPU_FTR_VSX_COMP 0 |
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#define PPC_FEATURE_HAS_VSX_COMP 0 |
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#endif |
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/* We only set the spe features if the kernel was compiled with spe |
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* support |
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*/ |
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#ifdef CONFIG_SPE |
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#define CPU_FTR_SPE_COMP CPU_FTR_SPE |
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#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE |
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#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE |
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#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE |
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#else |
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#define CPU_FTR_SPE_COMP 0 |
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#define PPC_FEATURE_HAS_SPE_COMP 0 |
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#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0 |
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#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0 |
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#endif |
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/* We only set the TM feature if the kernel was compiled with TM supprt */ |
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
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#define CPU_FTR_TM_COMP CPU_FTR_TM |
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#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM |
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#define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC |
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#else |
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#define CPU_FTR_TM_COMP 0 |
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#define PPC_FEATURE2_HTM_COMP 0 |
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#define PPC_FEATURE2_HTM_NOSC_COMP 0 |
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#endif |
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/* We need to mark all pages as being coherent if we're SMP or we have a |
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* 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II |
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* require it for PCI "streaming/prefetch" to work properly. |
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* This is also required by 52xx family. |
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*/ |
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#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ |
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|| defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \ |
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|| defined(CONFIG_PPC_MPC52xx) |
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#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT |
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#else |
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#define CPU_FTR_COMMON 0 |
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#endif |
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/* The powersave features NAP & DOZE seems to confuse BDI when |
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debugging. So if a BDI is used, disable theses |
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*/ |
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#ifndef CONFIG_BDI_SWITCH |
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#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE |
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#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP |
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#else |
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#define CPU_FTR_MAYBE_CAN_DOZE 0 |
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#define CPU_FTR_MAYBE_CAN_NAP 0 |
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#endif |
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#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ |
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE | CPU_FTR_NOEXECUTE) |
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#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_PPC_LE) |
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#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \ |
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CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ |
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
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#define CPU_FTRS_740 (CPU_FTR_COMMON | \ |
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CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ |
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CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ |
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CPU_FTR_PPC_LE) |
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#define CPU_FTRS_750 (CPU_FTR_COMMON | \ |
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CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ |
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CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ |
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CPU_FTR_PPC_LE) |
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#define CPU_FTRS_750CL (CPU_FTRS_750) |
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#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) |
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#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM) |
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#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX) |
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#define CPU_FTRS_750GX (CPU_FTRS_750FX) |
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#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \ |
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CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ |
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CPU_FTR_ALTIVEC_COMP | \ |
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
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#define CPU_FTRS_7400 (CPU_FTR_COMMON | \ |
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CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ |
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CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \ |
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
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#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ |
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CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
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CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ |
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CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
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#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ |
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
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CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ |
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CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ |
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CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
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#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ |
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CPU_FTR_NEED_PAIRED_STWCX | \ |
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
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CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ |
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CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
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#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ |
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CPU_FTR_NEED_PAIRED_STWCX | \ |
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CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ |
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CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
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#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ |
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CPU_FTR_NEED_PAIRED_STWCX | \ |
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
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CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ |
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CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ |
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CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
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#define CPU_FTRS_7455 (CPU_FTR_COMMON | \ |
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
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CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
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CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
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#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ |
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
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CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
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CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \ |
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CPU_FTR_NEED_PAIRED_STWCX) |
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#define CPU_FTRS_7447 (CPU_FTR_COMMON | \ |
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
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CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
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CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
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#define CPU_FTRS_7447A (CPU_FTR_COMMON | \ |
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
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CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
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CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
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#define CPU_FTRS_7448 (CPU_FTR_COMMON | \ |
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
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CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
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CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
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#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_NOEXECUTE) |
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#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ |
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NOEXECUTE) |
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#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ |
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CPU_FTR_MAYBE_CAN_NAP | \ |
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CPU_FTR_COMMON | CPU_FTR_NOEXECUTE) |
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#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \ |
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CPU_FTR_MAYBE_CAN_NAP | \ |
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CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE | CPU_FTR_NOEXECUTE) |
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#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON) |
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#define CPU_FTRS_8XX (CPU_FTR_NOEXECUTE) |
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#define CPU_FTRS_40X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) |
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#define CPU_FTRS_44X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) |
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#define CPU_FTRS_440x6 (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \ |
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CPU_FTR_INDEXED_DCR) |
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#define CPU_FTRS_47X (CPU_FTRS_440x6) |
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#define CPU_FTRS_E200 (CPU_FTR_SPE_COMP | \ |
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CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \ |
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CPU_FTR_NOEXECUTE | \ |
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CPU_FTR_DEBUG_LVL_EXC) |
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#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | \ |
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CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \ |
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CPU_FTR_NOEXECUTE) |
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#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | \ |
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CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ |
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CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) |
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#define CPU_FTRS_E500MC (CPU_FTR_NODSISRALIGN | \ |
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CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ |
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CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV) |
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/* |
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* e5500/e6500 erratum A-006958 is a timebase bug that can use the |
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* same workaround as CPU_FTR_CELL_TB_BUG. |
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*/ |
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#define CPU_FTRS_E5500 (CPU_FTR_NODSISRALIGN | \ |
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CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ |
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CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ |
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CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG) |
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#define CPU_FTRS_E6500 (CPU_FTR_NODSISRALIGN | \ |
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CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ |
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CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ |
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CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \ |
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CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT) |
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|
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/* 64-bit CPUs */ |
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#define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \ |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ |
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CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \ |
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CPU_FTR_HVMODE | CPU_FTR_DABRX) |
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#define CPU_FTRS_POWER5 (CPU_FTR_LWSYNC | \ |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
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CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
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CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \ |
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX) |
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#define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \ |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
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CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
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CPU_FTR_COHERENT_ICACHE | \ |
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CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ |
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CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ |
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \ |
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CPU_FTR_DABRX) |
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#define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \ |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ |
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CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
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CPU_FTR_COHERENT_ICACHE | \ |
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CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ |
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CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ |
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ |
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CPU_FTR_CFAR | CPU_FTR_HVMODE | \ |
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CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX ) |
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#define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \ |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ |
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CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
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CPU_FTR_COHERENT_ICACHE | \ |
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CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ |
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CPU_FTR_DSCR | CPU_FTR_SAO | \ |
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ |
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CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ |
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CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \ |
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CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP ) |
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#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG) |
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#define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \ |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ |
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CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
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CPU_FTR_COHERENT_ICACHE | \ |
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CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ |
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CPU_FTR_DSCR | CPU_FTR_SAO | \ |
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ |
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CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ |
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CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \ |
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CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_P9_TLBIE_STQ_BUG | \ |
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CPU_FTR_P9_TLBIE_ERAT_BUG | CPU_FTR_P9_TIDR) |
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#define CPU_FTRS_POWER9_DD2_0 (CPU_FTRS_POWER9 | CPU_FTR_P9_RADIX_PREFETCH_BUG) |
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#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | \ |
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CPU_FTR_P9_RADIX_PREFETCH_BUG | \ |
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CPU_FTR_POWER9_DD2_1) |
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#define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \ |
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CPU_FTR_P9_TM_HV_ASSIST | \ |
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CPU_FTR_P9_TM_XER_SO_BUG) |
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#define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \ |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ |
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CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
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CPU_FTR_COHERENT_ICACHE | \ |
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CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ |
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CPU_FTR_DSCR | CPU_FTR_SAO | \ |
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CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ |
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CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ |
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CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \ |
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CPU_FTR_ARCH_300 | CPU_FTR_ARCH_31 | \ |
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CPU_FTR_DAWR | CPU_FTR_DAWR1) |
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#define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \ |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
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CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ |
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CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX) |
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#define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \ |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \ |
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CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX) |
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#define CPU_FTRS_COMPATIBLE (CPU_FTR_PPCAS_ARCH_V2) |
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#ifdef __powerpc64__ |
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#ifdef CONFIG_PPC_BOOK3E |
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#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500) |
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#else |
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#ifdef CONFIG_CPU_LITTLE_ENDIAN |
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#define CPU_FTRS_POSSIBLE \ |
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(CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \ |
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \ |
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CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10) |
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#else |
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#define CPU_FTRS_POSSIBLE \ |
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(CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \ |
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CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \ |
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CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \ |
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CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \ |
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CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10) |
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#endif /* CONFIG_CPU_LITTLE_ENDIAN */ |
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#endif |
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#else |
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enum { |
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CPU_FTRS_POSSIBLE = |
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#ifdef CONFIG_PPC_BOOK3S_32 |
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CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU | |
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CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 | |
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CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX | |
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CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 | |
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CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | |
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CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | |
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CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX | |
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CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 | |
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CPU_FTRS_CLASSIC32 | |
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#endif |
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#ifdef CONFIG_PPC_8xx |
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CPU_FTRS_8XX | |
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#endif |
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#ifdef CONFIG_40x |
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CPU_FTRS_40X | |
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#endif |
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#ifdef CONFIG_44x |
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CPU_FTRS_44X | CPU_FTRS_440x6 | |
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#endif |
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#ifdef CONFIG_PPC_47x |
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CPU_FTRS_47X | CPU_FTR_476_DD2 | |
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#endif |
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#ifdef CONFIG_E200 |
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CPU_FTRS_E200 | |
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#endif |
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#ifdef CONFIG_E500 |
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CPU_FTRS_E500 | CPU_FTRS_E500_2 | |
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#endif |
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#ifdef CONFIG_PPC_E500MC |
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CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 | |
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#endif |
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0, |
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}; |
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#endif /* __powerpc64__ */ |
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|
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#ifdef __powerpc64__ |
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#ifdef CONFIG_PPC_BOOK3E |
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#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500) |
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#else |
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|
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#ifdef CONFIG_PPC_DT_CPU_FTRS |
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#define CPU_FTRS_DT_CPU_BASE \ |
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(CPU_FTR_LWSYNC | \ |
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CPU_FTR_FPU_UNAVAILABLE | \ |
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CPU_FTR_NODSISRALIGN | \ |
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CPU_FTR_NOEXECUTE | \ |
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CPU_FTR_COHERENT_ICACHE | \ |
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CPU_FTR_STCX_CHECKS_ADDRESS | \ |
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CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ |
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CPU_FTR_DAWR | \ |
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CPU_FTR_ARCH_206 | \ |
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CPU_FTR_ARCH_207S) |
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#else |
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#define CPU_FTRS_DT_CPU_BASE (~0ul) |
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#endif |
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|
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#ifdef CONFIG_CPU_LITTLE_ENDIAN |
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#define CPU_FTRS_ALWAYS \ |
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(CPU_FTRS_POSSIBLE & ~CPU_FTR_HVMODE & CPU_FTRS_POWER7 & \ |
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CPU_FTRS_POWER8E & CPU_FTRS_POWER8 & CPU_FTRS_POWER9 & \ |
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CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE) |
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#else |
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#define CPU_FTRS_ALWAYS \ |
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(CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \ |
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CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \ |
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CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \ |
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~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & CPU_FTRS_POWER9 & \ |
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CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE) |
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#endif /* CONFIG_CPU_LITTLE_ENDIAN */ |
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#endif |
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#else |
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enum { |
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CPU_FTRS_ALWAYS = |
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#ifdef CONFIG_PPC_BOOK3S_32 |
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CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU & |
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CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 & |
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CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX & |
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CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 & |
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CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & |
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CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & |
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CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX & |
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CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 & |
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CPU_FTRS_CLASSIC32 & |
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#endif |
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#ifdef CONFIG_PPC_8xx |
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CPU_FTRS_8XX & |
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#endif |
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#ifdef CONFIG_40x |
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CPU_FTRS_40X & |
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#endif |
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#ifdef CONFIG_44x |
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CPU_FTRS_44X & CPU_FTRS_440x6 & |
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#endif |
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#ifdef CONFIG_E200 |
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CPU_FTRS_E200 & |
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#endif |
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#ifdef CONFIG_E500 |
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CPU_FTRS_E500 & CPU_FTRS_E500_2 & |
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#endif |
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#ifdef CONFIG_PPC_E500MC |
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CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 & |
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#endif |
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~CPU_FTR_EMB_HV & /* can be removed at runtime */ |
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CPU_FTRS_POSSIBLE, |
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}; |
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#endif /* __powerpc64__ */ |
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|
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/* |
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* Maximum number of hw breakpoint supported on powerpc. Number of |
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* breakpoints supported by actual hw might be less than this, which |
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* is decided at run time in nr_wp_slots(). |
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*/ |
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#define HBP_NUM_MAX 2 |
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|
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#endif /* !__ASSEMBLY__ */ |
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|
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#endif /* __ASM_POWERPC_CPUTABLE_H */
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