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847 lines
27 KiB
847 lines
27 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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#ifndef _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ |
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#define _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ |
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/* |
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* PowerPC64 memory management structures |
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* |
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* Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com> |
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* PPC64 rework. |
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*/ |
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|
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#include <asm/page.h> |
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#include <asm/bug.h> |
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#include <asm/asm-const.h> |
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|
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/* |
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* This is necessary to get the definition of PGTABLE_RANGE which we |
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* need for various slices related matters. Note that this isn't the |
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* complete pgtable.h but only a portion of it. |
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*/ |
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#include <asm/book3s/64/pgtable.h> |
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#include <asm/bug.h> |
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#include <asm/task_size_64.h> |
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#include <asm/cpu_has_feature.h> |
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|
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/* |
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* SLB |
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*/ |
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#define SLB_NUM_BOLTED 2 |
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#define SLB_CACHE_ENTRIES 8 |
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#define SLB_MIN_SIZE 32 |
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/* Bits in the SLB ESID word */ |
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#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */ |
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/* Bits in the SLB VSID word */ |
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#define SLB_VSID_SHIFT 12 |
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#define SLB_VSID_SHIFT_256M SLB_VSID_SHIFT |
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#define SLB_VSID_SHIFT_1T 24 |
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#define SLB_VSID_SSIZE_SHIFT 62 |
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#define SLB_VSID_B ASM_CONST(0xc000000000000000) |
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#define SLB_VSID_B_256M ASM_CONST(0x0000000000000000) |
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#define SLB_VSID_B_1T ASM_CONST(0x4000000000000000) |
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#define SLB_VSID_KS ASM_CONST(0x0000000000000800) |
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#define SLB_VSID_KP ASM_CONST(0x0000000000000400) |
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#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */ |
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#define SLB_VSID_L ASM_CONST(0x0000000000000100) |
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#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */ |
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#define SLB_VSID_LP ASM_CONST(0x0000000000000030) |
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#define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000) |
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#define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010) |
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#define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020) |
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#define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030) |
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#define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP) |
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#define SLB_VSID_KERNEL (SLB_VSID_KP) |
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#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C) |
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#define SLBIE_C (0x08000000) |
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#define SLBIE_SSIZE_SHIFT 25 |
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|
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/* |
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* Hash table |
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*/ |
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#define HPTES_PER_GROUP 8 |
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#define HPTE_V_SSIZE_SHIFT 62 |
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#define HPTE_V_AVPN_SHIFT 7 |
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#define HPTE_V_COMMON_BITS ASM_CONST(0x000fffffffffffff) |
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#define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80) |
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#define HPTE_V_AVPN_3_0 ASM_CONST(0x000fffffffffff80) |
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#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT) |
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#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL)) |
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#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010) |
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#define HPTE_V_LOCK ASM_CONST(0x0000000000000008) |
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#define HPTE_V_LARGE ASM_CONST(0x0000000000000004) |
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#define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002) |
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#define HPTE_V_VALID ASM_CONST(0x0000000000000001) |
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|
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/* |
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* ISA 3.0 has a different HPTE format. |
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*/ |
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#define HPTE_R_3_0_SSIZE_SHIFT 58 |
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#define HPTE_R_3_0_SSIZE_MASK (3ull << HPTE_R_3_0_SSIZE_SHIFT) |
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#define HPTE_R_PP0 ASM_CONST(0x8000000000000000) |
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#define HPTE_R_TS ASM_CONST(0x4000000000000000) |
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#define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000) |
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#define HPTE_R_KEY_BIT4 ASM_CONST(0x2000000000000000) |
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#define HPTE_R_KEY_BIT3 ASM_CONST(0x1000000000000000) |
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#define HPTE_R_RPN_SHIFT 12 |
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#define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000) |
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#define HPTE_R_RPN_3_0 ASM_CONST(0x01fffffffffff000) |
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#define HPTE_R_PP ASM_CONST(0x0000000000000003) |
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#define HPTE_R_PPP ASM_CONST(0x8000000000000003) |
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#define HPTE_R_N ASM_CONST(0x0000000000000004) |
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#define HPTE_R_G ASM_CONST(0x0000000000000008) |
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#define HPTE_R_M ASM_CONST(0x0000000000000010) |
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#define HPTE_R_I ASM_CONST(0x0000000000000020) |
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#define HPTE_R_W ASM_CONST(0x0000000000000040) |
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#define HPTE_R_WIMG ASM_CONST(0x0000000000000078) |
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#define HPTE_R_C ASM_CONST(0x0000000000000080) |
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#define HPTE_R_R ASM_CONST(0x0000000000000100) |
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#define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00) |
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#define HPTE_R_KEY_BIT2 ASM_CONST(0x0000000000000800) |
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#define HPTE_R_KEY_BIT1 ASM_CONST(0x0000000000000400) |
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#define HPTE_R_KEY_BIT0 ASM_CONST(0x0000000000000200) |
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#define HPTE_R_KEY (HPTE_R_KEY_LO | HPTE_R_KEY_HI) |
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#define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000) |
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#define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000) |
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/* Values for PP (assumes Ks=0, Kp=1) */ |
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#define PP_RWXX 0 /* Supervisor read/write, User none */ |
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#define PP_RWRX 1 /* Supervisor read/write, User read */ |
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#define PP_RWRW 2 /* Supervisor read/write, User read/write */ |
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#define PP_RXRX 3 /* Supervisor read, User read */ |
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#define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */ |
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/* Fields for tlbiel instruction in architecture 2.06 */ |
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#define TLBIEL_INVAL_SEL_MASK 0xc00 /* invalidation selector */ |
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#define TLBIEL_INVAL_PAGE 0x000 /* invalidate a single page */ |
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#define TLBIEL_INVAL_SET_LPID 0x800 /* invalidate a set for current LPID */ |
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#define TLBIEL_INVAL_SET 0xc00 /* invalidate a set for all LPIDs */ |
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#define TLBIEL_INVAL_SET_MASK 0xfff000 /* set number to inval. */ |
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#define TLBIEL_INVAL_SET_SHIFT 12 |
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#define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */ |
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#define POWER8_TLB_SETS 512 /* # sets in POWER8 TLB */ |
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#define POWER9_TLB_SETS_HASH 256 /* # sets in POWER9 TLB Hash mode */ |
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#define POWER9_TLB_SETS_RADIX 128 /* # sets in POWER9 TLB Radix mode */ |
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#ifndef __ASSEMBLY__ |
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struct mmu_hash_ops { |
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void (*hpte_invalidate)(unsigned long slot, |
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unsigned long vpn, |
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int bpsize, int apsize, |
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int ssize, int local); |
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long (*hpte_updatepp)(unsigned long slot, |
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unsigned long newpp, |
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unsigned long vpn, |
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int bpsize, int apsize, |
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int ssize, unsigned long flags); |
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void (*hpte_updateboltedpp)(unsigned long newpp, |
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unsigned long ea, |
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int psize, int ssize); |
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long (*hpte_insert)(unsigned long hpte_group, |
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unsigned long vpn, |
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unsigned long prpn, |
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unsigned long rflags, |
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unsigned long vflags, |
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int psize, int apsize, |
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int ssize); |
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long (*hpte_remove)(unsigned long hpte_group); |
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int (*hpte_removebolted)(unsigned long ea, |
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int psize, int ssize); |
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void (*flush_hash_range)(unsigned long number, int local); |
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void (*hugepage_invalidate)(unsigned long vsid, |
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unsigned long addr, |
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unsigned char *hpte_slot_array, |
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int psize, int ssize, int local); |
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int (*resize_hpt)(unsigned long shift); |
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/* |
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* Special for kexec. |
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* To be called in real mode with interrupts disabled. No locks are |
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* taken as such, concurrent access on pre POWER5 hardware could result |
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* in a deadlock. |
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* The linear mapping is destroyed as well. |
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*/ |
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void (*hpte_clear_all)(void); |
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}; |
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extern struct mmu_hash_ops mmu_hash_ops; |
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struct hash_pte { |
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__be64 v; |
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__be64 r; |
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}; |
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extern struct hash_pte *htab_address; |
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extern unsigned long htab_size_bytes; |
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extern unsigned long htab_hash_mask; |
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static inline int shift_to_mmu_psize(unsigned int shift) |
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{ |
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int psize; |
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for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) |
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if (mmu_psize_defs[psize].shift == shift) |
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return psize; |
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return -1; |
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} |
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static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) |
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{ |
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if (mmu_psize_defs[mmu_psize].shift) |
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return mmu_psize_defs[mmu_psize].shift; |
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BUG(); |
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} |
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static inline unsigned int ap_to_shift(unsigned long ap) |
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{ |
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int psize; |
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for (psize = 0; psize < MMU_PAGE_COUNT; psize++) { |
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if (mmu_psize_defs[psize].ap == ap) |
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return mmu_psize_defs[psize].shift; |
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} |
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return -1; |
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} |
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static inline unsigned long get_sllp_encoding(int psize) |
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{ |
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unsigned long sllp; |
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sllp = ((mmu_psize_defs[psize].sllp & SLB_VSID_L) >> 6) | |
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((mmu_psize_defs[psize].sllp & SLB_VSID_LP) >> 4); |
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return sllp; |
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} |
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#endif /* __ASSEMBLY__ */ |
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/* |
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* Segment sizes. |
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* These are the values used by hardware in the B field of |
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* SLB entries and the first dword of MMU hashtable entries. |
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* The B field is 2 bits; the values 2 and 3 are unused and reserved. |
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*/ |
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#define MMU_SEGSIZE_256M 0 |
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#define MMU_SEGSIZE_1T 1 |
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/* |
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* encode page number shift. |
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* in order to fit the 78 bit va in a 64 bit variable we shift the va by |
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* 12 bits. This enable us to address upto 76 bit va. |
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* For hpt hash from a va we can ignore the page size bits of va and for |
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* hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure |
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* we work in all cases including 4k page size. |
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*/ |
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#define VPN_SHIFT 12 |
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/* |
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* HPTE Large Page (LP) details |
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*/ |
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#define LP_SHIFT 12 |
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#define LP_BITS 8 |
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#define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT) |
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#ifndef __ASSEMBLY__ |
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static inline int slb_vsid_shift(int ssize) |
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{ |
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if (ssize == MMU_SEGSIZE_256M) |
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return SLB_VSID_SHIFT; |
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return SLB_VSID_SHIFT_1T; |
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} |
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static inline int segment_shift(int ssize) |
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{ |
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if (ssize == MMU_SEGSIZE_256M) |
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return SID_SHIFT; |
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return SID_SHIFT_1T; |
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} |
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/* |
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* This array is indexed by the LP field of the HPTE second dword. |
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* Since this field may contain some RPN bits, some entries are |
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* replicated so that we get the same value irrespective of RPN. |
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* The top 4 bits are the page size index (MMU_PAGE_*) for the |
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* actual page size, the bottom 4 bits are the base page size. |
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*/ |
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extern u8 hpte_page_sizes[1 << LP_BITS]; |
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static inline unsigned long __hpte_page_size(unsigned long h, unsigned long l, |
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bool is_base_size) |
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{ |
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unsigned int i, lp; |
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if (!(h & HPTE_V_LARGE)) |
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return 1ul << 12; |
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/* Look at the 8 bit LP value */ |
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lp = (l >> LP_SHIFT) & ((1 << LP_BITS) - 1); |
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i = hpte_page_sizes[lp]; |
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if (!i) |
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return 0; |
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if (!is_base_size) |
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i >>= 4; |
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return 1ul << mmu_psize_defs[i & 0xf].shift; |
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} |
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static inline unsigned long hpte_page_size(unsigned long h, unsigned long l) |
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{ |
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return __hpte_page_size(h, l, 0); |
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} |
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static inline unsigned long hpte_base_page_size(unsigned long h, unsigned long l) |
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{ |
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return __hpte_page_size(h, l, 1); |
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} |
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/* |
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* The current system page and segment sizes |
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*/ |
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extern int mmu_kernel_ssize; |
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extern int mmu_highuser_ssize; |
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extern u16 mmu_slb_size; |
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extern unsigned long tce_alloc_start, tce_alloc_end; |
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/* |
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* If the processor supports 64k normal pages but not 64k cache |
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* inhibited pages, we have to be prepared to switch processes |
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* to use 4k pages when they create cache-inhibited mappings. |
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* If this is the case, mmu_ci_restrictions will be set to 1. |
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*/ |
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extern int mmu_ci_restrictions; |
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/* |
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* This computes the AVPN and B fields of the first dword of a HPTE, |
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* for use when we want to match an existing PTE. The bottom 7 bits |
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* of the returned value are zero. |
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*/ |
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static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize, |
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int ssize) |
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{ |
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unsigned long v; |
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/* |
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* The AVA field omits the low-order 23 bits of the 78 bits VA. |
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* These bits are not needed in the PTE, because the |
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* low-order b of these bits are part of the byte offset |
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* into the virtual page and, if b < 23, the high-order |
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* 23-b of these bits are always used in selecting the |
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* PTEGs to be searched |
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*/ |
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v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm); |
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v <<= HPTE_V_AVPN_SHIFT; |
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v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT; |
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return v; |
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} |
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/* |
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* ISA v3.0 defines a new HPTE format, which differs from the old |
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* format in having smaller AVPN and ARPN fields, and the B field |
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* in the second dword instead of the first. |
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*/ |
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static inline unsigned long hpte_old_to_new_v(unsigned long v) |
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{ |
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/* trim AVPN, drop B */ |
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return v & HPTE_V_COMMON_BITS; |
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} |
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static inline unsigned long hpte_old_to_new_r(unsigned long v, unsigned long r) |
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{ |
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/* move B field from 1st to 2nd dword, trim ARPN */ |
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return (r & ~HPTE_R_3_0_SSIZE_MASK) | |
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(((v) >> HPTE_V_SSIZE_SHIFT) << HPTE_R_3_0_SSIZE_SHIFT); |
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} |
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static inline unsigned long hpte_new_to_old_v(unsigned long v, unsigned long r) |
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{ |
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/* insert B field */ |
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return (v & HPTE_V_COMMON_BITS) | |
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((r & HPTE_R_3_0_SSIZE_MASK) << |
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(HPTE_V_SSIZE_SHIFT - HPTE_R_3_0_SSIZE_SHIFT)); |
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} |
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static inline unsigned long hpte_new_to_old_r(unsigned long r) |
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{ |
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/* clear out B field */ |
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return r & ~HPTE_R_3_0_SSIZE_MASK; |
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} |
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static inline unsigned long hpte_get_old_v(struct hash_pte *hptep) |
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{ |
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unsigned long hpte_v; |
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hpte_v = be64_to_cpu(hptep->v); |
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if (cpu_has_feature(CPU_FTR_ARCH_300)) |
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hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r)); |
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return hpte_v; |
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} |
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/* |
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* This function sets the AVPN and L fields of the HPTE appropriately |
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* using the base page size and actual page size. |
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*/ |
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static inline unsigned long hpte_encode_v(unsigned long vpn, int base_psize, |
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int actual_psize, int ssize) |
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{ |
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unsigned long v; |
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v = hpte_encode_avpn(vpn, base_psize, ssize); |
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if (actual_psize != MMU_PAGE_4K) |
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v |= HPTE_V_LARGE; |
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return v; |
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} |
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|
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/* |
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* This function sets the ARPN, and LP fields of the HPTE appropriately |
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* for the page size. We assume the pa is already "clean" that is properly |
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* aligned for the requested page size |
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*/ |
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static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize, |
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int actual_psize) |
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{ |
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/* A 4K page needs no special encoding */ |
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if (actual_psize == MMU_PAGE_4K) |
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return pa & HPTE_R_RPN; |
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else { |
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unsigned int penc = mmu_psize_defs[base_psize].penc[actual_psize]; |
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unsigned int shift = mmu_psize_defs[actual_psize].shift; |
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return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT); |
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} |
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} |
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/* |
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* Build a VPN_SHIFT bit shifted va given VSID, EA and segment size. |
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*/ |
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static inline unsigned long hpt_vpn(unsigned long ea, |
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unsigned long vsid, int ssize) |
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{ |
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unsigned long mask; |
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int s_shift = segment_shift(ssize); |
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mask = (1ul << (s_shift - VPN_SHIFT)) - 1; |
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return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask); |
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} |
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/* |
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* This hashes a virtual address |
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*/ |
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static inline unsigned long hpt_hash(unsigned long vpn, |
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unsigned int shift, int ssize) |
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{ |
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unsigned long mask; |
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unsigned long hash, vsid; |
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/* VPN_SHIFT can be atmost 12 */ |
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if (ssize == MMU_SEGSIZE_256M) { |
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mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1; |
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hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^ |
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((vpn & mask) >> (shift - VPN_SHIFT)); |
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} else { |
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mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1; |
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vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT); |
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hash = vsid ^ (vsid << 25) ^ |
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((vpn & mask) >> (shift - VPN_SHIFT)) ; |
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} |
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return hash & 0x7fffffffffUL; |
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} |
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#define HPTE_LOCAL_UPDATE 0x1 |
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#define HPTE_NOHPTE_UPDATE 0x2 |
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extern int __hash_page_4K(unsigned long ea, unsigned long access, |
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unsigned long vsid, pte_t *ptep, unsigned long trap, |
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unsigned long flags, int ssize, int subpage_prot); |
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extern int __hash_page_64K(unsigned long ea, unsigned long access, |
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unsigned long vsid, pte_t *ptep, unsigned long trap, |
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unsigned long flags, int ssize); |
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struct mm_struct; |
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unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap); |
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extern int hash_page_mm(struct mm_struct *mm, unsigned long ea, |
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unsigned long access, unsigned long trap, |
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unsigned long flags); |
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extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap, |
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unsigned long dsisr); |
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int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid, |
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pte_t *ptep, unsigned long trap, unsigned long flags, |
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int ssize, unsigned int shift, unsigned int mmu_psize); |
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE |
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extern int __hash_page_thp(unsigned long ea, unsigned long access, |
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unsigned long vsid, pmd_t *pmdp, unsigned long trap, |
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unsigned long flags, int ssize, unsigned int psize); |
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#else |
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static inline int __hash_page_thp(unsigned long ea, unsigned long access, |
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unsigned long vsid, pmd_t *pmdp, |
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unsigned long trap, unsigned long flags, |
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int ssize, unsigned int psize) |
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{ |
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BUG(); |
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return -1; |
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} |
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#endif |
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extern void hash_failure_debug(unsigned long ea, unsigned long access, |
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unsigned long vsid, unsigned long trap, |
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int ssize, int psize, int lpsize, |
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unsigned long pte); |
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extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend, |
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unsigned long pstart, unsigned long prot, |
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int psize, int ssize); |
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int htab_remove_mapping(unsigned long vstart, unsigned long vend, |
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int psize, int ssize); |
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extern void pseries_add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages); |
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extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr); |
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extern void hash__setup_new_exec(void); |
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#ifdef CONFIG_PPC_PSERIES |
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void hpte_init_pseries(void); |
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#else |
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static inline void hpte_init_pseries(void) { } |
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#endif |
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extern void hpte_init_native(void); |
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struct slb_entry { |
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u64 esid; |
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u64 vsid; |
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}; |
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extern void slb_initialize(void); |
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void slb_flush_and_restore_bolted(void); |
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void slb_flush_all_realmode(void); |
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void __slb_restore_bolted_realmode(void); |
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void slb_restore_bolted_realmode(void); |
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void slb_save_contents(struct slb_entry *slb_ptr); |
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void slb_dump_contents(struct slb_entry *slb_ptr); |
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extern void slb_vmalloc_update(void); |
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extern void slb_set_size(u16 size); |
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#endif /* __ASSEMBLY__ */ |
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|
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/* |
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* VSID allocation (256MB segment) |
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* |
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* We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated |
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* from mmu context id and effective segment id of the address. |
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* |
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* For user processes max context id is limited to MAX_USER_CONTEXT. |
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* more details in get_user_context |
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* |
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* For kernel space get_kernel_context |
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* |
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* The proto-VSIDs are then scrambled into real VSIDs with the |
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* multiplicative hash: |
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* |
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* VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS |
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* |
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* VSID_MULTIPLIER is prime, so in particular it is |
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* co-prime to VSID_MODULUS, making this a 1:1 scrambling function. |
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* Because the modulus is 2^n-1 we can compute it efficiently without |
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* a divide or extra multiply (see below). The scramble function gives |
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* robust scattering in the hash table (at least based on some initial |
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* results). |
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* |
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* We use VSID 0 to indicate an invalid VSID. The means we can't use context id |
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* 0, because a context id of 0 and an EA of 0 gives a proto-VSID of 0, which |
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* will produce a VSID of 0. |
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* |
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* We also need to avoid the last segment of the last context, because that |
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* would give a protovsid of 0x1fffffffff. That will result in a VSID 0 |
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* because of the modulo operation in vsid scramble. |
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*/ |
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|
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/* |
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* Max Va bits we support as of now is 68 bits. We want 19 bit |
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* context ID. |
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* Restrictions: |
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* GPU has restrictions of not able to access beyond 128TB |
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* (47 bit effective address). We also cannot do more than 20bit PID. |
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* For p4 and p5 which can only do 65 bit VA, we restrict our CONTEXT_BITS |
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* to 16 bits (ie, we can only have 2^16 pids at the same time). |
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*/ |
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#define VA_BITS 68 |
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#define CONTEXT_BITS 19 |
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#define ESID_BITS (VA_BITS - (SID_SHIFT + CONTEXT_BITS)) |
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#define ESID_BITS_1T (VA_BITS - (SID_SHIFT_1T + CONTEXT_BITS)) |
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#define ESID_BITS_MASK ((1 << ESID_BITS) - 1) |
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#define ESID_BITS_1T_MASK ((1 << ESID_BITS_1T) - 1) |
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/* |
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* Now certain config support MAX_PHYSMEM more than 512TB. Hence we will need |
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* to use more than one context for linear mapping the kernel. |
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* For vmalloc and memmap, we use just one context with 512TB. With 64 byte |
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* struct page size, we need ony 32 TB in memmap for 2PB (51 bits (MAX_PHYSMEM_BITS)). |
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*/ |
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#if (H_MAX_PHYSMEM_BITS > MAX_EA_BITS_PER_CONTEXT) |
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#define MAX_KERNEL_CTX_CNT (1UL << (H_MAX_PHYSMEM_BITS - MAX_EA_BITS_PER_CONTEXT)) |
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#else |
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#define MAX_KERNEL_CTX_CNT 1 |
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#endif |
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#define MAX_VMALLOC_CTX_CNT 1 |
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#define MAX_IO_CTX_CNT 1 |
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#define MAX_VMEMMAP_CTX_CNT 1 |
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/* |
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* 256MB segment |
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* The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments |
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* available for user + kernel mapping. VSID 0 is reserved as invalid, contexts |
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* 1-4 are used for kernel mapping. Each segment contains 2^28 bytes. Each |
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* context maps 2^49 bytes (512TB). |
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* |
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* We also need to avoid the last segment of the last context, because that |
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* would give a protovsid of 0x1fffffffff. That will result in a VSID 0 |
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* because of the modulo operation in vsid scramble. |
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* |
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*/ |
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#define MAX_USER_CONTEXT ((ASM_CONST(1) << CONTEXT_BITS) - 2) |
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// The + 2 accounts for INVALID_REGION and 1 more to avoid overlap with kernel |
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#define MIN_USER_CONTEXT (MAX_KERNEL_CTX_CNT + MAX_VMALLOC_CTX_CNT + \ |
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MAX_IO_CTX_CNT + MAX_VMEMMAP_CTX_CNT + 2) |
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/* |
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* For platforms that support on 65bit VA we limit the context bits |
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*/ |
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#define MAX_USER_CONTEXT_65BIT_VA ((ASM_CONST(1) << (65 - (SID_SHIFT + ESID_BITS))) - 2) |
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/* |
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* This should be computed such that protovosid * vsid_mulitplier |
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* doesn't overflow 64 bits. The vsid_mutliplier should also be |
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* co-prime to vsid_modulus. We also need to make sure that number |
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* of bits in multiplied result (dividend) is less than twice the number of |
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* protovsid bits for our modulus optmization to work. |
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* |
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* The below table shows the current values used. |
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* |-------+------------+----------------------+------------+-------------------| |
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* | | Prime Bits | proto VSID_BITS_65VA | Total Bits | 2* prot VSID_BITS | |
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* |-------+------------+----------------------+------------+-------------------| |
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* | 1T | 24 | 25 | 49 | 50 | |
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* |-------+------------+----------------------+------------+-------------------| |
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* | 256MB | 24 | 37 | 61 | 74 | |
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* |-------+------------+----------------------+------------+-------------------| |
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* |
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* |-------+------------+----------------------+------------+--------------------| |
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* | | Prime Bits | proto VSID_BITS_68VA | Total Bits | 2* proto VSID_BITS | |
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* |-------+------------+----------------------+------------+--------------------| |
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* | 1T | 24 | 28 | 52 | 56 | |
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* |-------+------------+----------------------+------------+--------------------| |
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* | 256MB | 24 | 40 | 64 | 80 | |
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* |-------+------------+----------------------+------------+--------------------| |
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* |
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*/ |
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#define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */ |
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#define VSID_BITS_256M (VA_BITS - SID_SHIFT) |
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#define VSID_BITS_65_256M (65 - SID_SHIFT) |
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/* |
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* Modular multiplicative inverse of VSID_MULTIPLIER under modulo VSID_MODULUS |
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*/ |
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#define VSID_MULINV_256M ASM_CONST(665548017062) |
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#define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */ |
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#define VSID_BITS_1T (VA_BITS - SID_SHIFT_1T) |
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#define VSID_BITS_65_1T (65 - SID_SHIFT_1T) |
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#define VSID_MULINV_1T ASM_CONST(209034062) |
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|
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/* 1TB VSID reserved for VRMA */ |
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#define VRMA_VSID 0x1ffffffUL |
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#define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT)) |
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|
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/* 4 bits per slice and we have one slice per 1TB */ |
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#define SLICE_ARRAY_SIZE (H_PGTABLE_RANGE >> 41) |
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#define LOW_SLICE_ARRAY_SZ (BITS_PER_LONG / BITS_PER_BYTE) |
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#define TASK_SLICE_ARRAY_SZ(x) ((x)->hash_context->slb_addr_limit >> 41) |
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#ifndef __ASSEMBLY__ |
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|
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#ifdef CONFIG_PPC_SUBPAGE_PROT |
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/* |
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* For the sub-page protection option, we extend the PGD with one of |
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* these. Basically we have a 3-level tree, with the top level being |
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* the protptrs array. To optimize speed and memory consumption when |
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* only addresses < 4GB are being protected, pointers to the first |
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* four pages of sub-page protection words are stored in the low_prot |
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* array. |
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* Each page of sub-page protection words protects 1GB (4 bytes |
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* protects 64k). For the 3-level tree, each page of pointers then |
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* protects 8TB. |
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*/ |
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struct subpage_prot_table { |
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unsigned long maxaddr; /* only addresses < this are protected */ |
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unsigned int **protptrs[(TASK_SIZE_USER64 >> 43)]; |
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unsigned int *low_prot[4]; |
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}; |
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#define SBP_L1_BITS (PAGE_SHIFT - 2) |
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#define SBP_L2_BITS (PAGE_SHIFT - 3) |
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#define SBP_L1_COUNT (1 << SBP_L1_BITS) |
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#define SBP_L2_COUNT (1 << SBP_L2_BITS) |
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#define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS) |
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#define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS) |
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extern void subpage_prot_free(struct mm_struct *mm); |
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#else |
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static inline void subpage_prot_free(struct mm_struct *mm) {} |
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#endif /* CONFIG_PPC_SUBPAGE_PROT */ |
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/* |
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* One bit per slice. We have lower slices which cover 256MB segments |
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* upto 4G range. That gets us 16 low slices. For the rest we track slices |
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* in 1TB size. |
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*/ |
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struct slice_mask { |
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u64 low_slices; |
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DECLARE_BITMAP(high_slices, SLICE_NUM_HIGH); |
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}; |
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|
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struct hash_mm_context { |
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u16 user_psize; /* page size index */ |
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|
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/* SLB page size encodings*/ |
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unsigned char low_slices_psize[LOW_SLICE_ARRAY_SZ]; |
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unsigned char high_slices_psize[SLICE_ARRAY_SIZE]; |
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unsigned long slb_addr_limit; |
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#ifdef CONFIG_PPC_64K_PAGES |
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struct slice_mask mask_64k; |
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#endif |
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struct slice_mask mask_4k; |
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#ifdef CONFIG_HUGETLB_PAGE |
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struct slice_mask mask_16m; |
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struct slice_mask mask_16g; |
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#endif |
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#ifdef CONFIG_PPC_SUBPAGE_PROT |
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struct subpage_prot_table *spt; |
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#endif /* CONFIG_PPC_SUBPAGE_PROT */ |
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}; |
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#if 0 |
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/* |
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* The code below is equivalent to this function for arguments |
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* < 2^VSID_BITS, which is all this should ever be called |
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* with. However gcc is not clever enough to compute the |
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* modulus (2^n-1) without a second multiply. |
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*/ |
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#define vsid_scramble(protovsid, size) \ |
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((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size)) |
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|
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/* simplified form avoiding mod operation */ |
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#define vsid_scramble(protovsid, size) \ |
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({ \ |
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unsigned long x; \ |
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x = (protovsid) * VSID_MULTIPLIER_##size; \ |
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x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \ |
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(x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \ |
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}) |
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|
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#else /* 1 */ |
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static inline unsigned long vsid_scramble(unsigned long protovsid, |
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unsigned long vsid_multiplier, int vsid_bits) |
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{ |
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unsigned long vsid; |
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unsigned long vsid_modulus = ((1UL << vsid_bits) - 1); |
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/* |
|
* We have same multipler for both 256 and 1T segements now |
|
*/ |
|
vsid = protovsid * vsid_multiplier; |
|
vsid = (vsid >> vsid_bits) + (vsid & vsid_modulus); |
|
return (vsid + ((vsid + 1) >> vsid_bits)) & vsid_modulus; |
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} |
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|
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#endif /* 1 */ |
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|
|
/* Returns the segment size indicator for a user address */ |
|
static inline int user_segment_size(unsigned long addr) |
|
{ |
|
/* Use 1T segments if possible for addresses >= 1T */ |
|
if (addr >= (1UL << SID_SHIFT_1T)) |
|
return mmu_highuser_ssize; |
|
return MMU_SEGSIZE_256M; |
|
} |
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|
|
static inline unsigned long get_vsid(unsigned long context, unsigned long ea, |
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int ssize) |
|
{ |
|
unsigned long va_bits = VA_BITS; |
|
unsigned long vsid_bits; |
|
unsigned long protovsid; |
|
|
|
/* |
|
* Bad address. We return VSID 0 for that |
|
*/ |
|
if ((ea & EA_MASK) >= H_PGTABLE_RANGE) |
|
return 0; |
|
|
|
if (!mmu_has_feature(MMU_FTR_68_BIT_VA)) |
|
va_bits = 65; |
|
|
|
if (ssize == MMU_SEGSIZE_256M) { |
|
vsid_bits = va_bits - SID_SHIFT; |
|
protovsid = (context << ESID_BITS) | |
|
((ea >> SID_SHIFT) & ESID_BITS_MASK); |
|
return vsid_scramble(protovsid, VSID_MULTIPLIER_256M, vsid_bits); |
|
} |
|
/* 1T segment */ |
|
vsid_bits = va_bits - SID_SHIFT_1T; |
|
protovsid = (context << ESID_BITS_1T) | |
|
((ea >> SID_SHIFT_1T) & ESID_BITS_1T_MASK); |
|
return vsid_scramble(protovsid, VSID_MULTIPLIER_1T, vsid_bits); |
|
} |
|
|
|
/* |
|
* For kernel space, we use context ids as |
|
* below. Range is 512TB per context. |
|
* |
|
* 0x00001 - [ 0xc000000000000000 - 0xc001ffffffffffff] |
|
* 0x00002 - [ 0xc002000000000000 - 0xc003ffffffffffff] |
|
* 0x00003 - [ 0xc004000000000000 - 0xc005ffffffffffff] |
|
* 0x00004 - [ 0xc006000000000000 - 0xc007ffffffffffff] |
|
* |
|
* vmap, IO, vmemap |
|
* |
|
* 0x00005 - [ 0xc008000000000000 - 0xc009ffffffffffff] |
|
* 0x00006 - [ 0xc00a000000000000 - 0xc00bffffffffffff] |
|
* 0x00007 - [ 0xc00c000000000000 - 0xc00dffffffffffff] |
|
* |
|
*/ |
|
static inline unsigned long get_kernel_context(unsigned long ea) |
|
{ |
|
unsigned long region_id = get_region_id(ea); |
|
unsigned long ctx; |
|
/* |
|
* Depending on Kernel config, kernel region can have one context |
|
* or more. |
|
*/ |
|
if (region_id == LINEAR_MAP_REGION_ID) { |
|
/* |
|
* We already verified ea to be not beyond the addr limit. |
|
*/ |
|
ctx = 1 + ((ea & EA_MASK) >> MAX_EA_BITS_PER_CONTEXT); |
|
} else |
|
ctx = region_id + MAX_KERNEL_CTX_CNT - 1; |
|
return ctx; |
|
} |
|
|
|
/* |
|
* This is only valid for addresses >= PAGE_OFFSET |
|
*/ |
|
static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize) |
|
{ |
|
unsigned long context; |
|
|
|
if (!is_kernel_addr(ea)) |
|
return 0; |
|
|
|
context = get_kernel_context(ea); |
|
return get_vsid(context, ea, ssize); |
|
} |
|
|
|
unsigned htab_shift_for_mem_size(unsigned long mem_size); |
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|
|
#endif /* __ASSEMBLY__ */ |
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|
|
#endif /* _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ */
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