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172 lines
4.9 KiB
172 lines
4.9 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _ASM_POWERPC_BOOK3S_64_HASH_4K_H |
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#define _ASM_POWERPC_BOOK3S_64_HASH_4K_H |
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#define H_PTE_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps: 2^9 x 4KB = 2MB |
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#define H_PMD_INDEX_SIZE 7 // size: 8B << 7 = 1KB, maps: 2^7 x 2MB = 256MB |
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#define H_PUD_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps: 2^9 x 256MB = 128GB |
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#define H_PGD_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps: 2^9 x 128GB = 64TB |
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/* |
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* Each context is 512TB. But on 4k we restrict our max TASK size to 64TB |
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* Hence also limit max EA bits to 64TB. |
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*/ |
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#define MAX_EA_BITS_PER_CONTEXT 46 |
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/* |
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* Our page table limit us to 64TB. For 64TB physical memory, we only need 64GB |
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* of vmemmap space. To better support sparse memory layout, we use 61TB |
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* linear map range, 1TB of vmalloc, 1TB of I/O and 1TB of vmememmap. |
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*/ |
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#define REGION_SHIFT (40) |
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#define H_KERN_MAP_SIZE (ASM_CONST(1) << REGION_SHIFT) |
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/* |
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* Limits the linear mapping range |
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*/ |
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#define H_MAX_PHYSMEM_BITS 46 |
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/* |
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* Define the address range of the kernel non-linear virtual area (61TB) |
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*/ |
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#define H_KERN_VIRT_START ASM_CONST(0xc0003d0000000000) |
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#ifndef __ASSEMBLY__ |
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#define H_PTE_TABLE_SIZE (sizeof(pte_t) << H_PTE_INDEX_SIZE) |
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#define H_PMD_TABLE_SIZE (sizeof(pmd_t) << H_PMD_INDEX_SIZE) |
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#define H_PUD_TABLE_SIZE (sizeof(pud_t) << H_PUD_INDEX_SIZE) |
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#define H_PGD_TABLE_SIZE (sizeof(pgd_t) << H_PGD_INDEX_SIZE) |
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#define H_PAGE_F_GIX_SHIFT _PAGE_PA_MAX |
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#define H_PAGE_F_SECOND _RPAGE_PKEY_BIT0 /* HPTE is in 2ndary HPTEG */ |
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#define H_PAGE_F_GIX (_RPAGE_RPN43 | _RPAGE_RPN42 | _RPAGE_RPN41) |
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#define H_PAGE_BUSY _RPAGE_RSV1 |
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#define H_PAGE_HASHPTE _RPAGE_PKEY_BIT4 |
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/* PTE flags to conserve for HPTE identification */ |
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#define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | \ |
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H_PAGE_F_SECOND | H_PAGE_F_GIX) |
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/* |
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* Not supported by 4k linux page size |
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*/ |
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#define H_PAGE_4K_PFN 0x0 |
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#define H_PAGE_THP_HUGE 0x0 |
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#define H_PAGE_COMBO 0x0 |
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/* 8 bytes per each pte entry */ |
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#define H_PTE_FRAG_SIZE_SHIFT (H_PTE_INDEX_SIZE + 3) |
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#define H_PTE_FRAG_NR (PAGE_SIZE >> H_PTE_FRAG_SIZE_SHIFT) |
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#define H_PMD_FRAG_SIZE_SHIFT (H_PMD_INDEX_SIZE + 3) |
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#define H_PMD_FRAG_NR (PAGE_SIZE >> H_PMD_FRAG_SIZE_SHIFT) |
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/* memory key bits, only 8 keys supported */ |
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#define H_PTE_PKEY_BIT4 0 |
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#define H_PTE_PKEY_BIT3 0 |
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#define H_PTE_PKEY_BIT2 _RPAGE_PKEY_BIT3 |
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#define H_PTE_PKEY_BIT1 _RPAGE_PKEY_BIT2 |
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#define H_PTE_PKEY_BIT0 _RPAGE_PKEY_BIT1 |
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/* |
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* On all 4K setups, remap_4k_pfn() equates to remap_pfn_range() |
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*/ |
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#define remap_4k_pfn(vma, addr, pfn, prot) \ |
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remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot)) |
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#ifdef CONFIG_HUGETLB_PAGE |
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static inline int hash__hugepd_ok(hugepd_t hpd) |
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{ |
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unsigned long hpdval = hpd_val(hpd); |
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/* |
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* if it is not a pte and have hugepd shift mask |
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* set, then it is a hugepd directory pointer |
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*/ |
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if (!(hpdval & _PAGE_PTE) && (hpdval & _PAGE_PRESENT) && |
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((hpdval & HUGEPD_SHIFT_MASK) != 0)) |
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return true; |
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return false; |
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} |
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#endif |
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/* |
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* 4K PTE format is different from 64K PTE format. Saving the hash_slot is just |
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* a matter of returning the PTE bits that need to be modified. On 64K PTE, |
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* things are a little more involved and hence needs many more parameters to |
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* accomplish the same. However we want to abstract this out from the caller by |
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* keeping the prototype consistent across the two formats. |
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*/ |
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static inline unsigned long pte_set_hidx(pte_t *ptep, real_pte_t rpte, |
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unsigned int subpg_index, unsigned long hidx, |
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int offset) |
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{ |
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return (hidx << H_PAGE_F_GIX_SHIFT) & |
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(H_PAGE_F_SECOND | H_PAGE_F_GIX); |
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} |
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE |
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static inline char *get_hpte_slot_array(pmd_t *pmdp) |
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{ |
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BUG(); |
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return NULL; |
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} |
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static inline unsigned int hpte_valid(unsigned char *hpte_slot_array, int index) |
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{ |
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BUG(); |
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return 0; |
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} |
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static inline unsigned int hpte_hash_index(unsigned char *hpte_slot_array, |
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int index) |
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{ |
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BUG(); |
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return 0; |
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} |
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static inline void mark_hpte_slot_valid(unsigned char *hpte_slot_array, |
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unsigned int index, unsigned int hidx) |
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{ |
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BUG(); |
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} |
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static inline int hash__pmd_trans_huge(pmd_t pmd) |
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{ |
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return 0; |
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} |
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static inline int hash__pmd_same(pmd_t pmd_a, pmd_t pmd_b) |
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{ |
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BUG(); |
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return 0; |
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} |
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static inline pmd_t hash__pmd_mkhuge(pmd_t pmd) |
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{ |
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BUG(); |
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return pmd; |
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} |
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extern unsigned long hash__pmd_hugepage_update(struct mm_struct *mm, |
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unsigned long addr, pmd_t *pmdp, |
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unsigned long clr, unsigned long set); |
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extern pmd_t hash__pmdp_collapse_flush(struct vm_area_struct *vma, |
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unsigned long address, pmd_t *pmdp); |
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extern void hash__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, |
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pgtable_t pgtable); |
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extern pgtable_t hash__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); |
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extern pmd_t hash__pmdp_huge_get_and_clear(struct mm_struct *mm, |
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unsigned long addr, pmd_t *pmdp); |
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extern int hash__has_transparent_hugepage(void); |
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#endif |
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static inline pmd_t hash__pmd_mkdevmap(pmd_t pmd) |
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{ |
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BUG(); |
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return pmd; |
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} |
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#endif /* !__ASSEMBLY__ */ |
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#endif /* _ASM_POWERPC_BOOK3S_64_HASH_4K_H */
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