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564 lines
14 KiB
564 lines
14 KiB
/* |
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* MPC8xx Internal Memory Map |
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* Copyright (c) 1997 Dan Malek ([email protected]) |
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* |
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* The I/O on the MPC860 is comprised of blocks of special registers |
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* and the dual port ram for the Communication Processor Module. |
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* Within this space are functional units such as the SIU, memory |
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* controller, system timers, and other control functions. It is |
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* a combination that I found difficult to separate into logical |
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* functional files.....but anyone else is welcome to try. -- Dan |
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*/ |
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#ifdef __KERNEL__ |
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#ifndef __IMMAP_8XX__ |
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#define __IMMAP_8XX__ |
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|
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/* System configuration registers. |
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*/ |
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typedef struct sys_conf { |
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uint sc_siumcr; |
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uint sc_sypcr; |
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uint sc_swt; |
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char res1[2]; |
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ushort sc_swsr; |
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uint sc_sipend; |
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uint sc_simask; |
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uint sc_siel; |
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uint sc_sivec; |
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uint sc_tesr; |
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char res2[0xc]; |
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uint sc_sdcr; |
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char res3[0x4c]; |
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} sysconf8xx_t; |
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|
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/* PCMCIA configuration registers. |
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*/ |
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typedef struct pcmcia_conf { |
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uint pcmc_pbr0; |
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uint pcmc_por0; |
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uint pcmc_pbr1; |
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uint pcmc_por1; |
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uint pcmc_pbr2; |
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uint pcmc_por2; |
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uint pcmc_pbr3; |
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uint pcmc_por3; |
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uint pcmc_pbr4; |
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uint pcmc_por4; |
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uint pcmc_pbr5; |
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uint pcmc_por5; |
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uint pcmc_pbr6; |
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uint pcmc_por6; |
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uint pcmc_pbr7; |
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uint pcmc_por7; |
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char res1[0x20]; |
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uint pcmc_pgcra; |
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uint pcmc_pgcrb; |
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uint pcmc_pscr; |
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char res2[4]; |
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uint pcmc_pipr; |
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char res3[4]; |
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uint pcmc_per; |
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char res4[4]; |
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} pcmconf8xx_t; |
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|
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/* Memory controller registers. |
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*/ |
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typedef struct mem_ctlr { |
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uint memc_br0; |
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uint memc_or0; |
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uint memc_br1; |
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uint memc_or1; |
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uint memc_br2; |
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uint memc_or2; |
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uint memc_br3; |
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uint memc_or3; |
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uint memc_br4; |
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uint memc_or4; |
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uint memc_br5; |
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uint memc_or5; |
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uint memc_br6; |
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uint memc_or6; |
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uint memc_br7; |
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uint memc_or7; |
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char res1[0x24]; |
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uint memc_mar; |
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uint memc_mcr; |
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char res2[4]; |
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uint memc_mamr; |
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uint memc_mbmr; |
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ushort memc_mstat; |
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ushort memc_mptpr; |
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uint memc_mdr; |
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char res3[0x80]; |
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} memctl8xx_t; |
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|
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/*----------------------------------------------------------------------- |
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* BR - Memory Controller: Base Register 16-9 |
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*/ |
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#define BR_BA_MSK 0xffff8000 /* Base Address Mask */ |
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#define BR_AT_MSK 0x00007000 /* Address Type Mask */ |
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#define BR_PS_MSK 0x00000c00 /* Port Size Mask */ |
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#define BR_PS_32 0x00000000 /* 32 bit port size */ |
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#define BR_PS_16 0x00000800 /* 16 bit port size */ |
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#define BR_PS_8 0x00000400 /* 8 bit port size */ |
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#define BR_PARE 0x00000200 /* Parity Enable */ |
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#define BR_WP 0x00000100 /* Write Protect */ |
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#define BR_MS_MSK 0x000000c0 /* Machine Select Mask */ |
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#define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */ |
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#define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ |
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#define BR_MS_UPMB 0x000000c0 /* U.P.M.B Machine Select */ |
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#define BR_V 0x00000001 /* Bank Valid */ |
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|
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/*----------------------------------------------------------------------- |
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* OR - Memory Controller: Option Register 16-11 |
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*/ |
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#define OR_AM_MSK 0xffff8000 /* Address Mask Mask */ |
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#define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */ |
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#define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */ |
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/* Address Multiplex */ |
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#define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */ |
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#define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */ |
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#define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */ |
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#define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */ |
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#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */ |
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#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/ |
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#define OR_BI 0x00000100 /* Burst inhibit */ |
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#define OR_SCY_MSK 0x000000f0 /* Cycle Length in Clocks */ |
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#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ |
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#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ |
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#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ |
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#define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */ |
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#define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */ |
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#define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */ |
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#define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */ |
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#define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ |
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#define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */ |
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#define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */ |
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#define OR_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */ |
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#define OR_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */ |
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#define OR_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */ |
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#define OR_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */ |
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#define OR_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */ |
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#define OR_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */ |
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#define OR_SETA 0x00000008 /* External Transfer Acknowledge */ |
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#define OR_TRLX 0x00000004 /* Timing Relaxed */ |
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#define OR_EHTR 0x00000002 /* Extended Hold Time on Read */ |
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/* System Integration Timers. |
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*/ |
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typedef struct sys_int_timers { |
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ushort sit_tbscr; |
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char res0[0x02]; |
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uint sit_tbreff0; |
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uint sit_tbreff1; |
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char res1[0x14]; |
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ushort sit_rtcsc; |
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char res2[0x02]; |
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uint sit_rtc; |
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uint sit_rtsec; |
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uint sit_rtcal; |
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char res3[0x10]; |
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ushort sit_piscr; |
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char res4[2]; |
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uint sit_pitc; |
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uint sit_pitr; |
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char res5[0x34]; |
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} sit8xx_t; |
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#define TBSCR_TBIRQ_MASK ((ushort)0xff00) |
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#define TBSCR_REFA ((ushort)0x0080) |
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#define TBSCR_REFB ((ushort)0x0040) |
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#define TBSCR_REFAE ((ushort)0x0008) |
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#define TBSCR_REFBE ((ushort)0x0004) |
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#define TBSCR_TBF ((ushort)0x0002) |
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#define TBSCR_TBE ((ushort)0x0001) |
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#define RTCSC_RTCIRQ_MASK ((ushort)0xff00) |
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#define RTCSC_SEC ((ushort)0x0080) |
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#define RTCSC_ALR ((ushort)0x0040) |
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#define RTCSC_38K ((ushort)0x0010) |
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#define RTCSC_SIE ((ushort)0x0008) |
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#define RTCSC_ALE ((ushort)0x0004) |
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#define RTCSC_RTF ((ushort)0x0002) |
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#define RTCSC_RTE ((ushort)0x0001) |
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#define PISCR_PIRQ_MASK ((ushort)0xff00) |
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#define PISCR_PS ((ushort)0x0080) |
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#define PISCR_PIE ((ushort)0x0004) |
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#define PISCR_PTF ((ushort)0x0002) |
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#define PISCR_PTE ((ushort)0x0001) |
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/* Clocks and Reset. |
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*/ |
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typedef struct clk_and_reset { |
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uint car_sccr; |
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uint car_plprcr; |
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uint car_rsr; |
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char res[0x74]; /* Reserved area */ |
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} car8xx_t; |
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/* System Integration Timers keys. |
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*/ |
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typedef struct sitk { |
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uint sitk_tbscrk; |
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uint sitk_tbreff0k; |
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uint sitk_tbreff1k; |
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uint sitk_tbk; |
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char res1[0x10]; |
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uint sitk_rtcsck; |
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uint sitk_rtck; |
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uint sitk_rtseck; |
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uint sitk_rtcalk; |
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char res2[0x10]; |
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uint sitk_piscrk; |
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uint sitk_pitck; |
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char res3[0x38]; |
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} sitk8xx_t; |
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/* Clocks and reset keys. |
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*/ |
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typedef struct cark { |
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uint cark_sccrk; |
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uint cark_plprcrk; |
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uint cark_rsrk; |
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char res[0x474]; |
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} cark8xx_t; |
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/* The key to unlock registers maintained by keep-alive power. |
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*/ |
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#define KAPWR_KEY ((unsigned int)0x55ccaa33) |
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/* Video interface. MPC823 Only. |
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*/ |
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typedef struct vid823 { |
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ushort vid_vccr; |
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ushort res1; |
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u_char vid_vsr; |
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u_char res2; |
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u_char vid_vcmr; |
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u_char res3; |
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uint vid_vbcb; |
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uint res4; |
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uint vid_vfcr0; |
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uint vid_vfaa0; |
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uint vid_vfba0; |
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uint vid_vfcr1; |
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uint vid_vfaa1; |
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uint vid_vfba1; |
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u_char res5[0x18]; |
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} vid823_t; |
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/* LCD interface. 823 Only. |
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*/ |
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typedef struct lcd { |
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uint lcd_lccr; |
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uint lcd_lchcr; |
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uint lcd_lcvcr; |
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char res1[4]; |
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uint lcd_lcfaa; |
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uint lcd_lcfba; |
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char lcd_lcsr; |
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char res2[0x7]; |
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} lcd823_t; |
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/* I2C |
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*/ |
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typedef struct i2c { |
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u_char i2c_i2mod; |
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char res1[3]; |
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u_char i2c_i2add; |
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char res2[3]; |
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u_char i2c_i2brg; |
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char res3[3]; |
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u_char i2c_i2com; |
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char res4[3]; |
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u_char i2c_i2cer; |
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char res5[3]; |
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u_char i2c_i2cmr; |
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char res6[0x8b]; |
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} i2c8xx_t; |
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/* DMA control/status registers. |
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*/ |
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typedef struct sdma_csr { |
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char res1[4]; |
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uint sdma_sdar; |
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u_char sdma_sdsr; |
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char res3[3]; |
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u_char sdma_sdmr; |
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char res4[3]; |
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u_char sdma_idsr1; |
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char res5[3]; |
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u_char sdma_idmr1; |
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char res6[3]; |
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u_char sdma_idsr2; |
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char res7[3]; |
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u_char sdma_idmr2; |
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char res8[0x13]; |
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} sdma8xx_t; |
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/* Communication Processor Module Interrupt Controller. |
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*/ |
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typedef struct cpm_ic { |
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ushort cpic_civr; |
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char res[0xe]; |
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uint cpic_cicr; |
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uint cpic_cipr; |
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uint cpic_cimr; |
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uint cpic_cisr; |
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} cpic8xx_t; |
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/* Input/Output Port control/status registers. |
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*/ |
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typedef struct io_port { |
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ushort iop_padir; |
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ushort iop_papar; |
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ushort iop_paodr; |
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ushort iop_padat; |
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char res1[8]; |
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ushort iop_pcdir; |
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ushort iop_pcpar; |
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ushort iop_pcso; |
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ushort iop_pcdat; |
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ushort iop_pcint; |
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char res2[6]; |
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ushort iop_pddir; |
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ushort iop_pdpar; |
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char res3[2]; |
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ushort iop_pddat; |
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uint utmode; |
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char res4[4]; |
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} iop8xx_t; |
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/* Communication Processor Module Timers |
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*/ |
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typedef struct cpm_timers { |
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ushort cpmt_tgcr; |
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char res1[0xe]; |
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ushort cpmt_tmr1; |
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ushort cpmt_tmr2; |
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ushort cpmt_trr1; |
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ushort cpmt_trr2; |
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ushort cpmt_tcr1; |
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ushort cpmt_tcr2; |
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ushort cpmt_tcn1; |
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ushort cpmt_tcn2; |
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ushort cpmt_tmr3; |
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ushort cpmt_tmr4; |
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ushort cpmt_trr3; |
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ushort cpmt_trr4; |
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ushort cpmt_tcr3; |
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ushort cpmt_tcr4; |
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ushort cpmt_tcn3; |
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ushort cpmt_tcn4; |
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ushort cpmt_ter1; |
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ushort cpmt_ter2; |
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ushort cpmt_ter3; |
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ushort cpmt_ter4; |
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char res2[8]; |
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} cpmtimer8xx_t; |
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/* Finally, the Communication Processor stuff..... |
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*/ |
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typedef struct scc { /* Serial communication channels */ |
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uint scc_gsmrl; |
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uint scc_gsmrh; |
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ushort scc_psmr; |
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char res1[2]; |
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ushort scc_todr; |
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ushort scc_dsr; |
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ushort scc_scce; |
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char res2[2]; |
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ushort scc_sccm; |
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char res3; |
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u_char scc_sccs; |
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char res4[8]; |
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} scc_t; |
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typedef struct smc { /* Serial management channels */ |
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char res1[2]; |
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ushort smc_smcmr; |
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char res2[2]; |
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u_char smc_smce; |
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char res3[3]; |
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u_char smc_smcm; |
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char res4[5]; |
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} smc_t; |
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/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but |
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* it fits within the address space. |
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*/ |
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typedef struct fec { |
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uint fec_addr_low; /* lower 32 bits of station address */ |
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ushort fec_addr_high; /* upper 16 bits of station address */ |
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ushort res1; /* reserved */ |
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uint fec_grp_hash_table_high; /* upper 32-bits of hash table */ |
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uint fec_grp_hash_table_low; /* lower 32-bits of hash table */ |
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uint fec_r_des_start; /* beginning of Rx descriptor ring */ |
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uint fec_x_des_start; /* beginning of Tx descriptor ring */ |
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uint fec_r_buff_size; /* Rx buffer size */ |
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uint res2[9]; /* reserved */ |
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uint fec_ecntrl; /* ethernet control register */ |
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uint fec_ievent; /* interrupt event register */ |
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uint fec_imask; /* interrupt mask register */ |
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uint fec_ivec; /* interrupt level and vector status */ |
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uint fec_r_des_active; /* Rx ring updated flag */ |
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uint fec_x_des_active; /* Tx ring updated flag */ |
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uint res3[10]; /* reserved */ |
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uint fec_mii_data; /* MII data register */ |
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uint fec_mii_speed; /* MII speed control register */ |
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uint res4[17]; /* reserved */ |
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uint fec_r_bound; /* end of RAM (read-only) */ |
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uint fec_r_fstart; /* Rx FIFO start address */ |
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uint res5[6]; /* reserved */ |
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uint fec_x_fstart; /* Tx FIFO start address */ |
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uint res6[17]; /* reserved */ |
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uint fec_fun_code; /* fec SDMA function code */ |
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uint res7[3]; /* reserved */ |
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uint fec_r_cntrl; /* Rx control register */ |
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uint fec_r_hash; /* Rx hash register */ |
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uint res8[14]; /* reserved */ |
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uint fec_x_cntrl; /* Tx control register */ |
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uint res9[0x1e]; /* reserved */ |
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} fec_t; |
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|
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/* The FEC and LCD color map share the same address space.... |
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* I guess we will never see an 823T :-). |
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*/ |
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union fec_lcd { |
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fec_t fl_un_fec; |
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u_char fl_un_cmap[0x200]; |
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}; |
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typedef struct comm_proc { |
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/* General control and status registers. |
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*/ |
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ushort cp_cpcr; |
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u_char res1[2]; |
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ushort cp_rccr; |
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u_char res2; |
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u_char cp_rmds; |
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u_char res3[4]; |
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ushort cp_cpmcr1; |
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ushort cp_cpmcr2; |
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ushort cp_cpmcr3; |
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ushort cp_cpmcr4; |
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u_char res4[2]; |
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ushort cp_rter; |
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u_char res5[2]; |
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ushort cp_rtmr; |
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u_char res6[0x14]; |
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|
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/* Baud rate generators. |
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*/ |
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uint cp_brgc1; |
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uint cp_brgc2; |
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uint cp_brgc3; |
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uint cp_brgc4; |
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|
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/* Serial Communication Channels. |
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*/ |
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scc_t cp_scc[4]; |
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|
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/* Serial Management Channels. |
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*/ |
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smc_t cp_smc[2]; |
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|
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/* Serial Peripheral Interface. |
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*/ |
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ushort cp_spmode; |
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u_char res7[4]; |
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u_char cp_spie; |
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u_char res8[3]; |
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u_char cp_spim; |
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u_char res9[2]; |
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u_char cp_spcom; |
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u_char res10[2]; |
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|
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/* Parallel Interface Port. |
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*/ |
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u_char res11[2]; |
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ushort cp_pipc; |
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u_char res12[2]; |
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ushort cp_ptpr; |
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uint cp_pbdir; |
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uint cp_pbpar; |
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u_char res13[2]; |
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ushort cp_pbodr; |
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uint cp_pbdat; |
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|
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/* Port E - MPC87x/88x only. |
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*/ |
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uint cp_pedir; |
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uint cp_pepar; |
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uint cp_peso; |
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uint cp_peodr; |
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uint cp_pedat; |
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/* Communications Processor Timing Register - |
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Contains RMII Timing for the FECs on MPC87x/88x only. |
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*/ |
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uint cp_cptr; |
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/* Serial Interface and Time Slot Assignment. |
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*/ |
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uint cp_simode; |
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u_char cp_sigmr; |
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u_char res15; |
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u_char cp_sistr; |
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u_char cp_sicmr; |
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u_char res16[4]; |
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uint cp_sicr; |
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uint cp_sirp; |
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u_char res17[0xc]; |
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|
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/* 256 bytes of MPC823 video controller RAM array. |
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*/ |
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u_char cp_vcram[0x100]; |
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u_char cp_siram[0x200]; |
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|
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/* The fast ethernet controller is not really part of the CPM, |
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* but it resides in the address space. |
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* The LCD color map is also here. |
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*/ |
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union fec_lcd fl_un; |
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#define cp_fec fl_un.fl_un_fec |
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#define lcd_cmap fl_un.fl_un_cmap |
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char res18[0xE00]; |
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|
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/* The DUET family has a second FEC here */ |
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fec_t cp_fec2; |
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#define cp_fec1 cp_fec /* consistency macro */ |
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|
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/* Dual Ported RAM follows. |
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* There are many different formats for this memory area |
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* depending upon the devices used and options chosen. |
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* Some processors don't have all of it populated. |
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*/ |
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u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */ |
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u_char cp_dparam[0x400]; /* Parameter RAM */ |
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} cpm8xx_t; |
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|
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/* Internal memory map. |
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*/ |
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typedef struct immap { |
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sysconf8xx_t im_siu_conf; /* SIU Configuration */ |
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pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ |
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memctl8xx_t im_memctl; /* Memory Controller */ |
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sit8xx_t im_sit; /* System integration timers */ |
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car8xx_t im_clkrst; /* Clocks and reset */ |
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sitk8xx_t im_sitk; /* Sys int timer keys */ |
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cark8xx_t im_clkrstk; /* Clocks and reset keys */ |
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vid823_t im_vid; /* Video (823 only) */ |
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lcd823_t im_lcd; /* LCD (823 only) */ |
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i2c8xx_t im_i2c; /* I2C control/status */ |
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sdma8xx_t im_sdma; /* SDMA control/status */ |
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cpic8xx_t im_cpic; /* CPM Interrupt Controller */ |
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iop8xx_t im_ioport; /* IO Port control/status */ |
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cpmtimer8xx_t im_cpmtimer; /* CPM timers */ |
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cpm8xx_t im_cpm; /* Communication processor */ |
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} immap_t; |
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#endif /* __IMMAP_8XX__ */ |
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#endif /* __KERNEL__ */
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