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725 lines
22 KiB
725 lines
22 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* OMAP3xxx PRM module functions |
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* |
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* Copyright (C) 2010-2012 Texas Instruments, Inc. |
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* Copyright (C) 2010 Nokia Corporation |
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* Benoît Cousson |
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* Paul Walmsley |
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* Rajendra Nayak <[email protected]> |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/errno.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/of_irq.h> |
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|
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#include "soc.h" |
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#include "common.h" |
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#include "vp.h" |
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#include "powerdomain.h" |
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#include "prm3xxx.h" |
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#include "prm2xxx_3xxx.h" |
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#include "cm2xxx_3xxx.h" |
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#include "prm-regbits-34xx.h" |
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#include "cm3xxx.h" |
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#include "cm-regbits-34xx.h" |
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#include "clock.h" |
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static void omap3xxx_prm_read_pending_irqs(unsigned long *events); |
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static void omap3xxx_prm_ocp_barrier(void); |
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static void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask); |
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static void omap3xxx_prm_restore_irqen(u32 *saved_mask); |
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static const struct omap_prcm_irq omap3_prcm_irqs[] = { |
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OMAP_PRCM_IRQ("wkup", 0, 0), |
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OMAP_PRCM_IRQ("io", 9, 1), |
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}; |
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static struct omap_prcm_irq_setup omap3_prcm_irq_setup = { |
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.ack = OMAP3_PRM_IRQSTATUS_MPU_OFFSET, |
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.mask = OMAP3_PRM_IRQENABLE_MPU_OFFSET, |
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.nr_regs = 1, |
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.irqs = omap3_prcm_irqs, |
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.nr_irqs = ARRAY_SIZE(omap3_prcm_irqs), |
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.irq = 11 + OMAP_INTC_START, |
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.read_pending_irqs = &omap3xxx_prm_read_pending_irqs, |
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.ocp_barrier = &omap3xxx_prm_ocp_barrier, |
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.save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen, |
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.restore_irqen = &omap3xxx_prm_restore_irqen, |
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.reconfigure_io_chain = NULL, |
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}; |
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/* |
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* omap3_prm_reset_src_map - map from bits in the PRM_RSTST hardware |
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* register (which are specific to OMAP3xxx SoCs) to reset source ID |
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* bit shifts (which is an OMAP SoC-independent enumeration) |
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*/ |
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static struct prm_reset_src_map omap3xxx_prm_reset_src_map[] = { |
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{ OMAP3430_GLOBAL_COLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT }, |
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{ OMAP3430_GLOBAL_SW_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT }, |
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{ OMAP3430_SECURITY_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT }, |
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{ OMAP3430_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT }, |
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{ OMAP3430_SECURE_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT }, |
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{ OMAP3430_EXTERNAL_WARM_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT }, |
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{ OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT, |
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OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT }, |
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{ OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT, |
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OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT }, |
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{ OMAP3430_ICEPICK_RST_SHIFT, OMAP_ICEPICK_RST_SRC_ID_SHIFT }, |
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{ OMAP3430_ICECRUSHER_RST_SHIFT, OMAP_ICECRUSHER_RST_SRC_ID_SHIFT }, |
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{ -1, -1 }, |
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}; |
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/* PRM VP */ |
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/* |
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* struct omap3_vp - OMAP3 VP register access description. |
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* @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg |
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*/ |
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struct omap3_vp { |
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u32 tranxdone_status; |
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}; |
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static struct omap3_vp omap3_vp[] = { |
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[OMAP3_VP_VDD_MPU_ID] = { |
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.tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK, |
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}, |
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[OMAP3_VP_VDD_CORE_ID] = { |
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.tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK, |
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}, |
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}; |
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#define MAX_VP_ID ARRAY_SIZE(omap3_vp); |
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static u32 omap3_prm_vp_check_txdone(u8 vp_id) |
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{ |
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struct omap3_vp *vp = &omap3_vp[vp_id]; |
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u32 irqstatus; |
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irqstatus = omap2_prm_read_mod_reg(OCP_MOD, |
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OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
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return irqstatus & vp->tranxdone_status; |
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} |
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static void omap3_prm_vp_clear_txdone(u8 vp_id) |
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{ |
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struct omap3_vp *vp = &omap3_vp[vp_id]; |
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omap2_prm_write_mod_reg(vp->tranxdone_status, |
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OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
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} |
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u32 omap3_prm_vcvp_read(u8 offset) |
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{ |
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return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset); |
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} |
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void omap3_prm_vcvp_write(u32 val, u8 offset) |
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{ |
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omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset); |
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} |
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u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) |
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{ |
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return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset); |
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} |
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/** |
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* omap3xxx_prm_dpll3_reset - use DPLL3 reset to reboot the OMAP SoC |
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* |
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* Set the DPLL3 reset bit, which should reboot the SoC. This is the |
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* recommended way to restart the SoC, considering Errata i520. No |
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* return value. |
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*/ |
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static void omap3xxx_prm_dpll3_reset(void) |
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{ |
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omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, OMAP3430_GR_MOD, |
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OMAP2_RM_RSTCTRL); |
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/* OCP barrier */ |
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omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP2_RM_RSTCTRL); |
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} |
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/** |
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* omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events |
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* @events: ptr to a u32, preallocated by caller |
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* |
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* Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM |
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* MPU IRQs, and store the result into the u32 pointed to by @events. |
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* No return value. |
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*/ |
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static void omap3xxx_prm_read_pending_irqs(unsigned long *events) |
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{ |
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u32 mask, st; |
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/* XXX Can the mask read be avoided (e.g., can it come from RAM?) */ |
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mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); |
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st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
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events[0] = mask & st; |
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} |
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/** |
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* omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete |
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* |
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* Force any buffered writes to the PRM IP block to complete. Needed |
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* by the PRM IRQ handler, which reads and writes directly to the IP |
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* block, to avoid race conditions after acknowledging or clearing IRQ |
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* bits. No return value. |
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*/ |
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static void omap3xxx_prm_ocp_barrier(void) |
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{ |
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omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET); |
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} |
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/** |
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* omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg |
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* @saved_mask: ptr to a u32 array to save IRQENABLE bits |
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* |
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* Save the PRM_IRQENABLE_MPU register to @saved_mask. @saved_mask |
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* must be allocated by the caller. Intended to be used in the PRM |
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* interrupt handler suspend callback. The OCP barrier is needed to |
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* ensure the write to disable PRM interrupts reaches the PRM before |
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* returning; otherwise, spurious interrupts might occur. No return |
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* value. |
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*/ |
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static void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask) |
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{ |
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saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD, |
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OMAP3_PRM_IRQENABLE_MPU_OFFSET); |
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omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); |
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/* OCP barrier */ |
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omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET); |
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} |
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/** |
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* omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args |
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* @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously |
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* |
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* Restore the PRM_IRQENABLE_MPU register from @saved_mask. Intended |
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* to be used in the PRM interrupt handler resume callback to restore |
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* values saved by omap3xxx_prm_save_and_clear_irqen(). No OCP |
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* barrier should be needed here; any pending PRM interrupts will fire |
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* once the writes reach the PRM. No return value. |
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*/ |
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static void omap3xxx_prm_restore_irqen(u32 *saved_mask) |
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{ |
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omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD, |
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OMAP3_PRM_IRQENABLE_MPU_OFFSET); |
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} |
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/** |
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* omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt |
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* @module: PRM module to clear wakeups from |
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* @regs: register set to clear, 1 or 3 |
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* @wkst_mask: wkst bits to clear |
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* |
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* The purpose of this function is to clear any wake-up events latched |
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* in the PRCM PM_WKST_x registers. It is possible that a wake-up event |
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* may occur whilst attempting to clear a PM_WKST_x register and thus |
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* set another bit in this register. A while loop is used to ensure |
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* that any peripheral wake-up events occurring while attempting to |
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* clear the PM_WKST_x are detected and cleared. |
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*/ |
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static int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask) |
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{ |
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u32 wkst, fclk, iclk, clken; |
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u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; |
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u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; |
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u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; |
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u16 grpsel_off = (regs == 3) ? |
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OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; |
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int c = 0; |
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wkst = omap2_prm_read_mod_reg(module, wkst_off); |
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wkst &= omap2_prm_read_mod_reg(module, grpsel_off); |
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wkst &= wkst_mask; |
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if (wkst) { |
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iclk = omap2_cm_read_mod_reg(module, iclk_off); |
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fclk = omap2_cm_read_mod_reg(module, fclk_off); |
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while (wkst) { |
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clken = wkst; |
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omap2_cm_set_mod_reg_bits(clken, module, iclk_off); |
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/* |
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* For USBHOST, we don't know whether HOST1 or |
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* HOST2 woke us up, so enable both f-clocks |
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*/ |
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if (module == OMAP3430ES2_USBHOST_MOD) |
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clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; |
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omap2_cm_set_mod_reg_bits(clken, module, fclk_off); |
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omap2_prm_write_mod_reg(wkst, module, wkst_off); |
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wkst = omap2_prm_read_mod_reg(module, wkst_off); |
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wkst &= wkst_mask; |
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c++; |
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} |
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omap2_cm_write_mod_reg(iclk, module, iclk_off); |
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omap2_cm_write_mod_reg(fclk, module, fclk_off); |
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} |
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return c; |
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} |
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/** |
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* omap3_prm_reset_modem - toggle reset signal for modem |
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* |
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* Toggles the reset signal to modem IP block. Required to allow |
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* OMAP3430 without stacked modem to idle properly. |
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*/ |
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void __init omap3_prm_reset_modem(void) |
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{ |
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omap2_prm_write_mod_reg( |
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OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | |
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OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, |
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CORE_MOD, OMAP2_RM_RSTCTRL); |
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omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); |
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} |
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/** |
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* omap3_prm_init_pm - initialize PM related registers for PRM |
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* @has_uart4: SoC has UART4 |
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* @has_iva: SoC has IVA |
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* |
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* Initializes PRM registers for PM use. Called from PM init. |
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*/ |
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void __init omap3_prm_init_pm(bool has_uart4, bool has_iva) |
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{ |
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u32 en_uart4_mask; |
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u32 grpsel_uart4_mask; |
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/* |
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* Enable control of expternal oscillator through |
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* sys_clkreq. In the long run clock framework should |
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* take care of this. |
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*/ |
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omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, |
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1 << OMAP_AUTOEXTCLKMODE_SHIFT, |
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OMAP3430_GR_MOD, |
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OMAP3_PRM_CLKSRC_CTRL_OFFSET); |
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/* setup wakup source */ |
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omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | |
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OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, |
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WKUP_MOD, PM_WKEN); |
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/* No need to write EN_IO, that is always enabled */ |
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omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | |
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OMAP3430_GRPSEL_GPT1_MASK | |
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OMAP3430_GRPSEL_GPT12_MASK, |
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WKUP_MOD, OMAP3430_PM_MPUGRPSEL); |
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/* Enable PM_WKEN to support DSS LPR */ |
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omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, |
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OMAP3430_DSS_MOD, PM_WKEN); |
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if (has_uart4) { |
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en_uart4_mask = OMAP3630_EN_UART4_MASK; |
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grpsel_uart4_mask = OMAP3630_GRPSEL_UART4_MASK; |
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} else { |
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en_uart4_mask = 0; |
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grpsel_uart4_mask = 0; |
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} |
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/* Enable wakeups in PER */ |
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omap2_prm_write_mod_reg(en_uart4_mask | |
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OMAP3430_EN_GPIO2_MASK | |
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OMAP3430_EN_GPIO3_MASK | |
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OMAP3430_EN_GPIO4_MASK | |
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OMAP3430_EN_GPIO5_MASK | |
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OMAP3430_EN_GPIO6_MASK | |
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OMAP3430_EN_UART3_MASK | |
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OMAP3430_EN_MCBSP2_MASK | |
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OMAP3430_EN_MCBSP3_MASK | |
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OMAP3430_EN_MCBSP4_MASK, |
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OMAP3430_PER_MOD, PM_WKEN); |
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/* and allow them to wake up MPU */ |
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omap2_prm_write_mod_reg(grpsel_uart4_mask | |
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OMAP3430_GRPSEL_GPIO2_MASK | |
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OMAP3430_GRPSEL_GPIO3_MASK | |
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OMAP3430_GRPSEL_GPIO4_MASK | |
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OMAP3430_GRPSEL_GPIO5_MASK | |
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OMAP3430_GRPSEL_GPIO6_MASK | |
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OMAP3430_GRPSEL_UART3_MASK | |
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OMAP3430_GRPSEL_MCBSP2_MASK | |
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OMAP3430_GRPSEL_MCBSP3_MASK | |
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OMAP3430_GRPSEL_MCBSP4_MASK, |
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OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); |
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/* Don't attach IVA interrupts */ |
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if (has_iva) { |
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omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); |
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omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); |
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omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); |
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omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, |
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OMAP3430_PM_IVAGRPSEL); |
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} |
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/* Clear any pending 'reset' flags */ |
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omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); |
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omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); |
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omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); |
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omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); |
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omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); |
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omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); |
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omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, |
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OMAP2_RM_RSTST); |
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|
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/* Clear any pending PRCM interrupts */ |
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omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
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|
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/* We need to idle iva2_pwrdm even on am3703 with no iva2. */ |
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omap3xxx_prm_iva_idle(); |
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omap3_prm_reset_modem(); |
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} |
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|
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/** |
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* omap3430_pre_es3_1_reconfigure_io_chain - restart wake-up daisy chain |
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* |
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* The ST_IO_CHAIN bit does not exist in 3430 before es3.1. The only |
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* thing we can do is toggle EN_IO bit for earlier omaps. |
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*/ |
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static void omap3430_pre_es3_1_reconfigure_io_chain(void) |
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{ |
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omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, |
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PM_WKEN); |
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omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, |
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PM_WKEN); |
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omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); |
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} |
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|
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/** |
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* omap3_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain |
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* |
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* Clear any previously-latched I/O wakeup events and ensure that the |
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* I/O wakeup gates are aligned with the current mux settings. Works |
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* by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then |
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* deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit. No |
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* return value. These registers are only available in 3430 es3.1 and later. |
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*/ |
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static void omap3_prm_reconfigure_io_chain(void) |
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{ |
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int i = 0; |
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|
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omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, |
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PM_WKEN); |
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omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) & |
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OMAP3430_ST_IO_CHAIN_MASK, |
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MAX_IOPAD_LATCH_TIME, i); |
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if (i == MAX_IOPAD_LATCH_TIME) |
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pr_warn("PRM: I/O chain clock line assertion timed out\n"); |
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omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, |
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PM_WKEN); |
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omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD, |
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PM_WKST); |
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omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST); |
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} |
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|
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/** |
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* omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches |
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* |
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* Activates the I/O wakeup event latches and allows events logged by |
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* those latches to signal a wakeup event to the PRCM. For I/O |
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* wakeups to occur, WAKEUPENABLE bits must be set in the pad mux |
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* registers, and omap3xxx_prm_reconfigure_io_chain() must be called. |
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* No return value. |
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*/ |
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static void omap3xxx_prm_enable_io_wakeup(void) |
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{ |
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if (prm_features & PRM_HAS_IO_WAKEUP) |
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omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, |
|
PM_WKEN); |
|
} |
|
|
|
/** |
|
* omap3xxx_prm_read_reset_sources - return the last SoC reset source |
|
* |
|
* Return a u32 representing the last reset sources of the SoC. The |
|
* returned reset source bits are standardized across OMAP SoCs. |
|
*/ |
|
static u32 omap3xxx_prm_read_reset_sources(void) |
|
{ |
|
struct prm_reset_src_map *p; |
|
u32 r = 0; |
|
u32 v; |
|
|
|
v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST); |
|
|
|
p = omap3xxx_prm_reset_src_map; |
|
while (p->reg_shift >= 0 && p->std_shift >= 0) { |
|
if (v & (1 << p->reg_shift)) |
|
r |= 1 << p->std_shift; |
|
p++; |
|
} |
|
|
|
return r; |
|
} |
|
|
|
/** |
|
* omap3xxx_prm_iva_idle - ensure IVA is in idle so it can be put into retention |
|
* |
|
* In cases where IVA2 is activated by bootcode, it may prevent |
|
* full-chip retention or off-mode because it is not idle. This |
|
* function forces the IVA2 into idle state so it can go |
|
* into retention/off and thus allow full-chip retention/off. |
|
*/ |
|
void omap3xxx_prm_iva_idle(void) |
|
{ |
|
/* ensure IVA2 clock is disabled */ |
|
omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); |
|
|
|
/* if no clock activity, nothing else to do */ |
|
if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & |
|
OMAP3430_CLKACTIVITY_IVA2_MASK)) |
|
return; |
|
|
|
/* Reset IVA2 */ |
|
omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | |
|
OMAP3430_RST2_IVA2_MASK | |
|
OMAP3430_RST3_IVA2_MASK, |
|
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
|
|
|
/* Enable IVA2 clock */ |
|
omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, |
|
OMAP3430_IVA2_MOD, CM_FCLKEN); |
|
|
|
/* Un-reset IVA2 */ |
|
omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
|
|
|
/* Disable IVA2 clock */ |
|
omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); |
|
|
|
/* Reset IVA2 */ |
|
omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | |
|
OMAP3430_RST2_IVA2_MASK | |
|
OMAP3430_RST3_IVA2_MASK, |
|
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
|
} |
|
|
|
/** |
|
* omap3xxx_prm_clear_global_cold_reset - checks the global cold reset status |
|
* and clears it if asserted |
|
* |
|
* Checks if cold-reset has occurred and clears the status bit if yes. Returns |
|
* 1 if cold-reset has occurred, 0 otherwise. |
|
*/ |
|
int omap3xxx_prm_clear_global_cold_reset(void) |
|
{ |
|
if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & |
|
OMAP3430_GLOBAL_COLD_RST_MASK) { |
|
omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, |
|
OMAP3430_GR_MOD, |
|
OMAP3_PRM_RSTST_OFFSET); |
|
return 1; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
void omap3_prm_save_scratchpad_contents(u32 *ptr) |
|
{ |
|
*ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD, |
|
OMAP3_PRM_CLKSRC_CTRL_OFFSET); |
|
|
|
*ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD, |
|
OMAP3_PRM_CLKSEL_OFFSET); |
|
} |
|
|
|
/* Powerdomain low-level functions */ |
|
|
|
static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) |
|
{ |
|
omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, |
|
(pwrst << OMAP_POWERSTATE_SHIFT), |
|
pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); |
|
return 0; |
|
} |
|
|
|
static int omap3_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) |
|
{ |
|
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, |
|
OMAP2_PM_PWSTCTRL, |
|
OMAP_POWERSTATE_MASK); |
|
} |
|
|
|
static int omap3_pwrdm_read_pwrst(struct powerdomain *pwrdm) |
|
{ |
|
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, |
|
OMAP2_PM_PWSTST, |
|
OMAP_POWERSTATEST_MASK); |
|
} |
|
|
|
/* Applicable only for OMAP3. Not supported on OMAP2 */ |
|
static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) |
|
{ |
|
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, |
|
OMAP3430_PM_PREPWSTST, |
|
OMAP3430_LASTPOWERSTATEENTERED_MASK); |
|
} |
|
|
|
static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) |
|
{ |
|
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, |
|
OMAP2_PM_PWSTST, |
|
OMAP3430_LOGICSTATEST_MASK); |
|
} |
|
|
|
static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm) |
|
{ |
|
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, |
|
OMAP2_PM_PWSTCTRL, |
|
OMAP3430_LOGICSTATEST_MASK); |
|
} |
|
|
|
static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) |
|
{ |
|
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, |
|
OMAP3430_PM_PREPWSTST, |
|
OMAP3430_LASTLOGICSTATEENTERED_MASK); |
|
} |
|
|
|
static int omap3_get_mem_bank_lastmemst_mask(u8 bank) |
|
{ |
|
switch (bank) { |
|
case 0: |
|
return OMAP3430_LASTMEM1STATEENTERED_MASK; |
|
case 1: |
|
return OMAP3430_LASTMEM2STATEENTERED_MASK; |
|
case 2: |
|
return OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK; |
|
case 3: |
|
return OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK; |
|
default: |
|
WARN_ON(1); /* should never happen */ |
|
return -EEXIST; |
|
} |
|
return 0; |
|
} |
|
|
|
static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) |
|
{ |
|
u32 m; |
|
|
|
m = omap3_get_mem_bank_lastmemst_mask(bank); |
|
|
|
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, |
|
OMAP3430_PM_PREPWSTST, m); |
|
} |
|
|
|
static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) |
|
{ |
|
omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST); |
|
return 0; |
|
} |
|
|
|
static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) |
|
{ |
|
return omap2_prm_rmw_mod_reg_bits(0, |
|
1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, |
|
pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); |
|
} |
|
|
|
static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) |
|
{ |
|
return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, |
|
0, pwrdm->prcm_offs, |
|
OMAP2_PM_PWSTCTRL); |
|
} |
|
|
|
struct pwrdm_ops omap3_pwrdm_operations = { |
|
.pwrdm_set_next_pwrst = omap3_pwrdm_set_next_pwrst, |
|
.pwrdm_read_next_pwrst = omap3_pwrdm_read_next_pwrst, |
|
.pwrdm_read_pwrst = omap3_pwrdm_read_pwrst, |
|
.pwrdm_read_prev_pwrst = omap3_pwrdm_read_prev_pwrst, |
|
.pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst, |
|
.pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst, |
|
.pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst, |
|
.pwrdm_read_prev_logic_pwrst = omap3_pwrdm_read_prev_logic_pwrst, |
|
.pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst, |
|
.pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst, |
|
.pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst, |
|
.pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst, |
|
.pwrdm_read_prev_mem_pwrst = omap3_pwrdm_read_prev_mem_pwrst, |
|
.pwrdm_clear_all_prev_pwrst = omap3_pwrdm_clear_all_prev_pwrst, |
|
.pwrdm_enable_hdwr_sar = omap3_pwrdm_enable_hdwr_sar, |
|
.pwrdm_disable_hdwr_sar = omap3_pwrdm_disable_hdwr_sar, |
|
.pwrdm_wait_transition = omap2_pwrdm_wait_transition, |
|
}; |
|
|
|
/* |
|
* |
|
*/ |
|
|
|
static int omap3xxx_prm_late_init(void); |
|
|
|
static struct prm_ll_data omap3xxx_prm_ll_data = { |
|
.read_reset_sources = &omap3xxx_prm_read_reset_sources, |
|
.late_init = &omap3xxx_prm_late_init, |
|
.assert_hardreset = &omap2_prm_assert_hardreset, |
|
.deassert_hardreset = &omap2_prm_deassert_hardreset, |
|
.is_hardreset_asserted = &omap2_prm_is_hardreset_asserted, |
|
.reset_system = &omap3xxx_prm_dpll3_reset, |
|
.clear_mod_irqs = &omap3xxx_prm_clear_mod_irqs, |
|
.vp_check_txdone = &omap3_prm_vp_check_txdone, |
|
.vp_clear_txdone = &omap3_prm_vp_clear_txdone, |
|
}; |
|
|
|
int __init omap3xxx_prm_init(const struct omap_prcm_init_data *data) |
|
{ |
|
omap2_clk_legacy_provider_init(TI_CLKM_PRM, |
|
prm_base.va + OMAP3430_IVA2_MOD); |
|
if (omap3_has_io_wakeup()) |
|
prm_features |= PRM_HAS_IO_WAKEUP; |
|
|
|
return prm_register(&omap3xxx_prm_ll_data); |
|
} |
|
|
|
static const struct of_device_id omap3_prm_dt_match_table[] = { |
|
{ .compatible = "ti,omap3-prm" }, |
|
{ } |
|
}; |
|
|
|
static int omap3xxx_prm_late_init(void) |
|
{ |
|
struct device_node *np; |
|
int irq_num; |
|
|
|
if (!(prm_features & PRM_HAS_IO_WAKEUP)) |
|
return 0; |
|
|
|
if (omap3_has_io_chain_ctrl()) |
|
omap3_prcm_irq_setup.reconfigure_io_chain = |
|
omap3_prm_reconfigure_io_chain; |
|
else |
|
omap3_prcm_irq_setup.reconfigure_io_chain = |
|
omap3430_pre_es3_1_reconfigure_io_chain; |
|
|
|
np = of_find_matching_node(NULL, omap3_prm_dt_match_table); |
|
if (!np) { |
|
pr_err("PRM: no device tree node for interrupt?\n"); |
|
|
|
return -ENODEV; |
|
} |
|
|
|
irq_num = of_irq_get(np, 0); |
|
if (irq_num == -EPROBE_DEFER) |
|
return irq_num; |
|
|
|
omap3_prcm_irq_setup.irq = irq_num; |
|
|
|
omap3xxx_prm_enable_io_wakeup(); |
|
|
|
return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup); |
|
} |
|
|
|
static void __exit omap3xxx_prm_exit(void) |
|
{ |
|
prm_unregister(&omap3xxx_prm_ll_data); |
|
} |
|
__exitcall(omap3xxx_prm_exit);
|
|
|