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128 lines
4.9 KiB
128 lines
4.9 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* OMAP2xxx Power/Reset Management (PRM) register definitions |
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* |
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* Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc. |
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* Copyright (C) 2008-2010 Nokia Corporation |
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* Paul Walmsley |
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* |
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* The PRM hardware modules on the OMAP2/3 are quite similar to each |
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* other. The PRM on OMAP4 has a new register layout, and is handled |
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* in a separate file. |
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*/ |
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#ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_H |
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#define __ARCH_ARM_MACH_OMAP2_PRM2XXX_H |
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#include "prcm-common.h" |
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#include "prm.h" |
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#include "prm2xxx_3xxx.h" |
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#define OMAP2420_PRM_REGADDR(module, reg) \ |
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OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) |
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#define OMAP2430_PRM_REGADDR(module, reg) \ |
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OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) |
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/* |
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* OMAP2-specific global PRM registers |
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* Use {read,write}l_relaxed() with these registers. |
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* |
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* With a few exceptions, these are the register names beginning with |
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* PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE |
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* bits.) |
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* |
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*/ |
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#define OMAP2_PRCM_REVISION_OFFSET 0x0000 |
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#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000) |
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#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010 |
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#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010) |
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#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018 |
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#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018) |
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#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c |
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#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c) |
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#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050 |
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#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050) |
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#define OMAP2_PRCM_VOLTST_OFFSET 0x0054 |
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#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054) |
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#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060 |
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#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060) |
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#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070 |
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#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070) |
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#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078 |
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#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078) |
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#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080 |
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#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080) |
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#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084 |
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#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084) |
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#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090 |
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#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090) |
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#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094 |
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#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094) |
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#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098 |
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#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098) |
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#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000) |
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#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010) |
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#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018) |
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#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c) |
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#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050) |
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#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054) |
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#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060) |
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#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070) |
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#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078) |
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#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080) |
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#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084) |
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#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090) |
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#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094) |
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#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098) |
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/* |
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* Module specific PRM register offsets from PRM_BASE + domain offset |
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* |
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* Use prm_{read,write}_mod_reg() with these registers. |
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* |
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* With a few exceptions, these are the register names beginning with |
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* {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the |
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* IRQSTATUS and IRQENABLE bits.) |
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*/ |
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/* Register offsets appearing on both OMAP2 and OMAP3 */ |
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#define OMAP2_RM_RSTCTRL 0x0050 |
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#define OMAP2_RM_RSTTIME 0x0054 |
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#define OMAP2_RM_RSTST 0x0058 |
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#define OMAP2_PM_PWSTCTRL 0x00e0 |
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#define OMAP2_PM_PWSTST 0x00e4 |
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#define PM_WKEN 0x00a0 |
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#define PM_WKEN1 PM_WKEN |
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#define PM_WKST 0x00b0 |
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#define PM_WKST1 PM_WKST |
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#define PM_WKDEP 0x00c8 |
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#define PM_EVGENCTRL 0x00d4 |
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#define PM_EVGENONTIM 0x00d8 |
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#define PM_EVGENOFFTIM 0x00dc |
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/* OMAP2xxx specific register offsets */ |
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#define OMAP24XX_PM_WKEN2 0x00a4 |
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#define OMAP24XX_PM_WKST2 0x00b4 |
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#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */ |
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#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */ |
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#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8 |
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#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc |
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#ifndef __ASSEMBLER__ |
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/* Function prototypes */ |
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extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm); |
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extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm); |
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int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data); |
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#endif |
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#endif
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