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780 lines
17 KiB
780 lines
17 KiB
/** |
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* @file nmi_int.c |
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* |
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* @remark Copyright 2002-2009 OProfile authors |
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* @remark Read the file COPYING |
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* |
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* @author John Levon <[email protected]> |
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* @author Robert Richter <[email protected]> |
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* @author Barry Kasindorf <[email protected]> |
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* @author Jason Yeh <[email protected]> |
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* @author Suravee Suthikulpanit <[email protected]> |
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*/ |
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|
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#include <linux/init.h> |
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#include <linux/notifier.h> |
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#include <linux/smp.h> |
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#include <linux/oprofile.h> |
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#include <linux/syscore_ops.h> |
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#include <linux/slab.h> |
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#include <linux/moduleparam.h> |
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#include <linux/kdebug.h> |
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#include <linux/cpu.h> |
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#include <asm/nmi.h> |
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#include <asm/msr.h> |
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#include <asm/apic.h> |
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#include "op_counter.h" |
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#include "op_x86_model.h" |
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static struct op_x86_model_spec *model; |
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static DEFINE_PER_CPU(struct op_msrs, cpu_msrs); |
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static DEFINE_PER_CPU(unsigned long, saved_lvtpc); |
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|
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/* must be protected with get_online_cpus()/put_online_cpus(): */ |
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static int nmi_enabled; |
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static int ctr_running; |
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struct op_counter_config counter_config[OP_MAX_COUNTER]; |
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|
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/* common functions */ |
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u64 op_x86_get_ctrl(struct op_x86_model_spec const *model, |
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struct op_counter_config *counter_config) |
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{ |
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u64 val = 0; |
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u16 event = (u16)counter_config->event; |
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val |= ARCH_PERFMON_EVENTSEL_INT; |
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val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0; |
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val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0; |
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val |= (counter_config->unit_mask & 0xFF) << 8; |
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counter_config->extra &= (ARCH_PERFMON_EVENTSEL_INV | |
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ARCH_PERFMON_EVENTSEL_EDGE | |
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ARCH_PERFMON_EVENTSEL_CMASK); |
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val |= counter_config->extra; |
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event &= model->event_mask ? model->event_mask : 0xFF; |
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val |= event & 0xFF; |
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val |= (u64)(event & 0x0F00) << 24; |
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return val; |
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} |
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static int profile_exceptions_notify(unsigned int val, struct pt_regs *regs) |
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{ |
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if (ctr_running) |
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model->check_ctrs(regs, this_cpu_ptr(&cpu_msrs)); |
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else if (!nmi_enabled) |
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return NMI_DONE; |
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else |
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model->stop(this_cpu_ptr(&cpu_msrs)); |
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return NMI_HANDLED; |
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} |
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static void nmi_cpu_save_registers(struct op_msrs *msrs) |
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{ |
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struct op_msr *counters = msrs->counters; |
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struct op_msr *controls = msrs->controls; |
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unsigned int i; |
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for (i = 0; i < model->num_counters; ++i) { |
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if (counters[i].addr) |
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rdmsrl(counters[i].addr, counters[i].saved); |
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} |
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for (i = 0; i < model->num_controls; ++i) { |
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if (controls[i].addr) |
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rdmsrl(controls[i].addr, controls[i].saved); |
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} |
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} |
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static void nmi_cpu_start(void *dummy) |
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{ |
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struct op_msrs const *msrs = this_cpu_ptr(&cpu_msrs); |
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if (!msrs->controls) |
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WARN_ON_ONCE(1); |
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else |
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model->start(msrs); |
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} |
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static int nmi_start(void) |
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{ |
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get_online_cpus(); |
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ctr_running = 1; |
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/* make ctr_running visible to the nmi handler: */ |
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smp_mb(); |
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on_each_cpu(nmi_cpu_start, NULL, 1); |
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put_online_cpus(); |
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return 0; |
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} |
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static void nmi_cpu_stop(void *dummy) |
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{ |
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struct op_msrs const *msrs = this_cpu_ptr(&cpu_msrs); |
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if (!msrs->controls) |
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WARN_ON_ONCE(1); |
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else |
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model->stop(msrs); |
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} |
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static void nmi_stop(void) |
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{ |
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get_online_cpus(); |
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on_each_cpu(nmi_cpu_stop, NULL, 1); |
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ctr_running = 0; |
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put_online_cpus(); |
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} |
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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
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static DEFINE_PER_CPU(int, switch_index); |
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static inline int has_mux(void) |
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{ |
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return !!model->switch_ctrl; |
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} |
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inline int op_x86_phys_to_virt(int phys) |
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{ |
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return __this_cpu_read(switch_index) + phys; |
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} |
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inline int op_x86_virt_to_phys(int virt) |
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{ |
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return virt % model->num_counters; |
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} |
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static void nmi_shutdown_mux(void) |
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{ |
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int i; |
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if (!has_mux()) |
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return; |
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for_each_possible_cpu(i) { |
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kfree(per_cpu(cpu_msrs, i).multiplex); |
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per_cpu(cpu_msrs, i).multiplex = NULL; |
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per_cpu(switch_index, i) = 0; |
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} |
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} |
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static int nmi_setup_mux(void) |
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{ |
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size_t multiplex_size = |
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sizeof(struct op_msr) * model->num_virt_counters; |
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int i; |
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if (!has_mux()) |
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return 1; |
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for_each_possible_cpu(i) { |
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per_cpu(cpu_msrs, i).multiplex = |
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kzalloc(multiplex_size, GFP_KERNEL); |
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if (!per_cpu(cpu_msrs, i).multiplex) |
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return 0; |
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} |
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return 1; |
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} |
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static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) |
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{ |
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int i; |
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struct op_msr *multiplex = msrs->multiplex; |
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if (!has_mux()) |
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return; |
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for (i = 0; i < model->num_virt_counters; ++i) { |
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if (counter_config[i].enabled) { |
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multiplex[i].saved = -(u64)counter_config[i].count; |
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} else { |
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multiplex[i].saved = 0; |
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} |
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} |
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per_cpu(switch_index, cpu) = 0; |
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} |
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static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs) |
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{ |
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struct op_msr *counters = msrs->counters; |
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struct op_msr *multiplex = msrs->multiplex; |
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int i; |
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for (i = 0; i < model->num_counters; ++i) { |
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int virt = op_x86_phys_to_virt(i); |
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if (counters[i].addr) |
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rdmsrl(counters[i].addr, multiplex[virt].saved); |
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} |
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} |
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static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs) |
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{ |
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struct op_msr *counters = msrs->counters; |
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struct op_msr *multiplex = msrs->multiplex; |
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int i; |
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for (i = 0; i < model->num_counters; ++i) { |
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int virt = op_x86_phys_to_virt(i); |
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if (counters[i].addr) |
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wrmsrl(counters[i].addr, multiplex[virt].saved); |
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} |
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} |
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static void nmi_cpu_switch(void *dummy) |
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{ |
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int cpu = smp_processor_id(); |
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int si = per_cpu(switch_index, cpu); |
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struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); |
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nmi_cpu_stop(NULL); |
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nmi_cpu_save_mpx_registers(msrs); |
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/* move to next set */ |
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si += model->num_counters; |
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if ((si >= model->num_virt_counters) || (counter_config[si].count == 0)) |
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per_cpu(switch_index, cpu) = 0; |
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else |
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per_cpu(switch_index, cpu) = si; |
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model->switch_ctrl(model, msrs); |
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nmi_cpu_restore_mpx_registers(msrs); |
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nmi_cpu_start(NULL); |
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} |
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/* |
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* Quick check to see if multiplexing is necessary. |
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* The check should be sufficient since counters are used |
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* in ordre. |
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*/ |
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static int nmi_multiplex_on(void) |
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{ |
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return counter_config[model->num_counters].count ? 0 : -EINVAL; |
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} |
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static int nmi_switch_event(void) |
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{ |
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if (!has_mux()) |
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return -ENOSYS; /* not implemented */ |
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if (nmi_multiplex_on() < 0) |
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return -EINVAL; /* not necessary */ |
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get_online_cpus(); |
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if (ctr_running) |
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on_each_cpu(nmi_cpu_switch, NULL, 1); |
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put_online_cpus(); |
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return 0; |
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} |
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static inline void mux_init(struct oprofile_operations *ops) |
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{ |
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if (has_mux()) |
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ops->switch_events = nmi_switch_event; |
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} |
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static void mux_clone(int cpu) |
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{ |
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if (!has_mux()) |
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return; |
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memcpy(per_cpu(cpu_msrs, cpu).multiplex, |
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per_cpu(cpu_msrs, 0).multiplex, |
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sizeof(struct op_msr) * model->num_virt_counters); |
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} |
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#else |
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inline int op_x86_phys_to_virt(int phys) { return phys; } |
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inline int op_x86_virt_to_phys(int virt) { return virt; } |
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static inline void nmi_shutdown_mux(void) { } |
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static inline int nmi_setup_mux(void) { return 1; } |
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static inline void |
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nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { } |
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static inline void mux_init(struct oprofile_operations *ops) { } |
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static void mux_clone(int cpu) { } |
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#endif |
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static void free_msrs(void) |
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{ |
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int i; |
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for_each_possible_cpu(i) { |
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kfree(per_cpu(cpu_msrs, i).counters); |
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per_cpu(cpu_msrs, i).counters = NULL; |
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kfree(per_cpu(cpu_msrs, i).controls); |
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per_cpu(cpu_msrs, i).controls = NULL; |
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} |
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nmi_shutdown_mux(); |
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} |
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static int allocate_msrs(void) |
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{ |
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size_t controls_size = sizeof(struct op_msr) * model->num_controls; |
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size_t counters_size = sizeof(struct op_msr) * model->num_counters; |
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int i; |
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for_each_possible_cpu(i) { |
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per_cpu(cpu_msrs, i).counters = kzalloc(counters_size, |
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GFP_KERNEL); |
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if (!per_cpu(cpu_msrs, i).counters) |
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goto fail; |
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per_cpu(cpu_msrs, i).controls = kzalloc(controls_size, |
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GFP_KERNEL); |
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if (!per_cpu(cpu_msrs, i).controls) |
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goto fail; |
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} |
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if (!nmi_setup_mux()) |
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goto fail; |
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return 1; |
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fail: |
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free_msrs(); |
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return 0; |
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} |
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static void nmi_cpu_setup(void) |
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{ |
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int cpu = smp_processor_id(); |
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struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); |
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nmi_cpu_save_registers(msrs); |
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raw_spin_lock(&oprofilefs_lock); |
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model->setup_ctrs(model, msrs); |
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nmi_cpu_setup_mux(cpu, msrs); |
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raw_spin_unlock(&oprofilefs_lock); |
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per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC); |
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apic_write(APIC_LVTPC, APIC_DM_NMI); |
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} |
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static void nmi_cpu_restore_registers(struct op_msrs *msrs) |
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{ |
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struct op_msr *counters = msrs->counters; |
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struct op_msr *controls = msrs->controls; |
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unsigned int i; |
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for (i = 0; i < model->num_controls; ++i) { |
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if (controls[i].addr) |
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wrmsrl(controls[i].addr, controls[i].saved); |
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} |
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for (i = 0; i < model->num_counters; ++i) { |
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if (counters[i].addr) |
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wrmsrl(counters[i].addr, counters[i].saved); |
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} |
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} |
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static void nmi_cpu_shutdown(void) |
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{ |
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unsigned int v; |
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int cpu = smp_processor_id(); |
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struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu); |
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|
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/* restoring APIC_LVTPC can trigger an apic error because the delivery |
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* mode and vector nr combination can be illegal. That's by design: on |
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* power on apic lvt contain a zero vector nr which are legal only for |
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* NMI delivery mode. So inhibit apic err before restoring lvtpc |
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*/ |
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v = apic_read(APIC_LVTERR); |
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apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); |
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apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu)); |
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apic_write(APIC_LVTERR, v); |
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nmi_cpu_restore_registers(msrs); |
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} |
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static int nmi_cpu_online(unsigned int cpu) |
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{ |
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local_irq_disable(); |
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if (nmi_enabled) |
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nmi_cpu_setup(); |
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if (ctr_running) |
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nmi_cpu_start(NULL); |
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local_irq_enable(); |
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return 0; |
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} |
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static int nmi_cpu_down_prep(unsigned int cpu) |
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{ |
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local_irq_disable(); |
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if (ctr_running) |
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nmi_cpu_stop(NULL); |
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if (nmi_enabled) |
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nmi_cpu_shutdown(); |
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local_irq_enable(); |
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return 0; |
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} |
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static int nmi_create_files(struct dentry *root) |
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{ |
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unsigned int i; |
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for (i = 0; i < model->num_virt_counters; ++i) { |
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struct dentry *dir; |
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char buf[4]; |
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/* quick little hack to _not_ expose a counter if it is not |
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* available for use. This should protect userspace app. |
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* NOTE: assumes 1:1 mapping here (that counters are organized |
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* sequentially in their struct assignment). |
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*/ |
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if (!avail_to_resrv_perfctr_nmi_bit(op_x86_virt_to_phys(i))) |
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continue; |
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snprintf(buf, sizeof(buf), "%d", i); |
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dir = oprofilefs_mkdir(root, buf); |
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oprofilefs_create_ulong(dir, "enabled", &counter_config[i].enabled); |
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oprofilefs_create_ulong(dir, "event", &counter_config[i].event); |
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oprofilefs_create_ulong(dir, "count", &counter_config[i].count); |
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oprofilefs_create_ulong(dir, "unit_mask", &counter_config[i].unit_mask); |
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oprofilefs_create_ulong(dir, "kernel", &counter_config[i].kernel); |
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oprofilefs_create_ulong(dir, "user", &counter_config[i].user); |
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oprofilefs_create_ulong(dir, "extra", &counter_config[i].extra); |
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} |
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return 0; |
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} |
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static enum cpuhp_state cpuhp_nmi_online; |
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static int nmi_setup(void) |
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{ |
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int err = 0; |
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int cpu; |
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if (!allocate_msrs()) |
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return -ENOMEM; |
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/* We need to serialize save and setup for HT because the subset |
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* of msrs are distinct for save and setup operations |
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*/ |
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/* Assume saved/restored counters are the same on all CPUs */ |
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err = model->fill_in_addresses(&per_cpu(cpu_msrs, 0)); |
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if (err) |
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goto fail; |
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for_each_possible_cpu(cpu) { |
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if (!IS_ENABLED(CONFIG_SMP) || !cpu) |
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continue; |
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memcpy(per_cpu(cpu_msrs, cpu).counters, |
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per_cpu(cpu_msrs, 0).counters, |
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sizeof(struct op_msr) * model->num_counters); |
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memcpy(per_cpu(cpu_msrs, cpu).controls, |
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per_cpu(cpu_msrs, 0).controls, |
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sizeof(struct op_msr) * model->num_controls); |
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mux_clone(cpu); |
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} |
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nmi_enabled = 0; |
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ctr_running = 0; |
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/* make variables visible to the nmi handler: */ |
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smp_mb(); |
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err = register_nmi_handler(NMI_LOCAL, profile_exceptions_notify, |
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0, "oprofile"); |
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if (err) |
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goto fail; |
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nmi_enabled = 1; |
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/* make nmi_enabled visible to the nmi handler: */ |
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smp_mb(); |
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err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/oprofile:online", |
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nmi_cpu_online, nmi_cpu_down_prep); |
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if (err < 0) |
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goto fail_nmi; |
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cpuhp_nmi_online = err; |
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return 0; |
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fail_nmi: |
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unregister_nmi_handler(NMI_LOCAL, "oprofile"); |
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fail: |
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free_msrs(); |
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return err; |
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} |
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static void nmi_shutdown(void) |
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{ |
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struct op_msrs *msrs; |
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cpuhp_remove_state(cpuhp_nmi_online); |
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nmi_enabled = 0; |
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ctr_running = 0; |
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/* make variables visible to the nmi handler: */ |
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smp_mb(); |
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unregister_nmi_handler(NMI_LOCAL, "oprofile"); |
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msrs = &get_cpu_var(cpu_msrs); |
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model->shutdown(msrs); |
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free_msrs(); |
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put_cpu_var(cpu_msrs); |
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} |
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#ifdef CONFIG_PM |
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|
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static int nmi_suspend(void) |
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{ |
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/* Only one CPU left, just stop that one */ |
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if (nmi_enabled == 1) |
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nmi_cpu_stop(NULL); |
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return 0; |
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} |
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static void nmi_resume(void) |
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{ |
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if (nmi_enabled == 1) |
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nmi_cpu_start(NULL); |
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} |
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static struct syscore_ops oprofile_syscore_ops = { |
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.resume = nmi_resume, |
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.suspend = nmi_suspend, |
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}; |
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static void __init init_suspend_resume(void) |
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{ |
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register_syscore_ops(&oprofile_syscore_ops); |
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} |
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static void exit_suspend_resume(void) |
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{ |
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unregister_syscore_ops(&oprofile_syscore_ops); |
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} |
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|
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#else |
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static inline void init_suspend_resume(void) { } |
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static inline void exit_suspend_resume(void) { } |
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|
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#endif /* CONFIG_PM */ |
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static int __init p4_init(char **cpu_type) |
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{ |
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__u8 cpu_model = boot_cpu_data.x86_model; |
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|
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if (cpu_model > 6 || cpu_model == 5) |
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return 0; |
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#ifndef CONFIG_SMP |
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*cpu_type = "i386/p4"; |
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model = &op_p4_spec; |
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return 1; |
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#else |
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switch (smp_num_siblings) { |
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case 1: |
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*cpu_type = "i386/p4"; |
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model = &op_p4_spec; |
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return 1; |
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|
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case 2: |
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*cpu_type = "i386/p4-ht"; |
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model = &op_p4_ht2_spec; |
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return 1; |
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} |
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#endif |
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|
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printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n"); |
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printk(KERN_INFO "oprofile: Reverting to timer mode.\n"); |
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return 0; |
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} |
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|
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enum __force_cpu_type { |
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reserved = 0, /* do not force */ |
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timer, |
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arch_perfmon, |
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}; |
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|
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static int force_cpu_type; |
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|
|
static int set_cpu_type(const char *str, const struct kernel_param *kp) |
|
{ |
|
if (!strcmp(str, "timer")) { |
|
force_cpu_type = timer; |
|
printk(KERN_INFO "oprofile: forcing NMI timer mode\n"); |
|
} else if (!strcmp(str, "arch_perfmon")) { |
|
force_cpu_type = arch_perfmon; |
|
printk(KERN_INFO "oprofile: forcing architectural perfmon\n"); |
|
} else { |
|
force_cpu_type = 0; |
|
} |
|
|
|
return 0; |
|
} |
|
module_param_call(cpu_type, set_cpu_type, NULL, NULL, 0); |
|
|
|
static int __init ppro_init(char **cpu_type) |
|
{ |
|
__u8 cpu_model = boot_cpu_data.x86_model; |
|
struct op_x86_model_spec *spec = &op_ppro_spec; /* default */ |
|
|
|
if (force_cpu_type == arch_perfmon && boot_cpu_has(X86_FEATURE_ARCH_PERFMON)) |
|
return 0; |
|
|
|
/* |
|
* Documentation on identifying Intel processors by CPU family |
|
* and model can be found in the Intel Software Developer's |
|
* Manuals (SDM): |
|
* |
|
* http://www.intel.com/products/processor/manuals/ |
|
* |
|
* As of May 2010 the documentation for this was in the: |
|
* "Intel 64 and IA-32 Architectures Software Developer's |
|
* Manual Volume 3B: System Programming Guide", "Table B-1 |
|
* CPUID Signature Values of DisplayFamily_DisplayModel". |
|
*/ |
|
switch (cpu_model) { |
|
case 0 ... 2: |
|
*cpu_type = "i386/ppro"; |
|
break; |
|
case 3 ... 5: |
|
*cpu_type = "i386/pii"; |
|
break; |
|
case 6 ... 8: |
|
case 10 ... 11: |
|
*cpu_type = "i386/piii"; |
|
break; |
|
case 9: |
|
case 13: |
|
*cpu_type = "i386/p6_mobile"; |
|
break; |
|
case 14: |
|
*cpu_type = "i386/core"; |
|
break; |
|
case 0x0f: |
|
case 0x16: |
|
case 0x17: |
|
case 0x1d: |
|
*cpu_type = "i386/core_2"; |
|
break; |
|
case 0x1a: |
|
case 0x1e: |
|
case 0x2e: |
|
spec = &op_arch_perfmon_spec; |
|
*cpu_type = "i386/core_i7"; |
|
break; |
|
case 0x1c: |
|
*cpu_type = "i386/atom"; |
|
break; |
|
default: |
|
/* Unknown */ |
|
return 0; |
|
} |
|
|
|
model = spec; |
|
return 1; |
|
} |
|
|
|
int __init op_nmi_init(struct oprofile_operations *ops) |
|
{ |
|
__u8 vendor = boot_cpu_data.x86_vendor; |
|
__u8 family = boot_cpu_data.x86; |
|
char *cpu_type = NULL; |
|
int ret = 0; |
|
|
|
if (!boot_cpu_has(X86_FEATURE_APIC)) |
|
return -ENODEV; |
|
|
|
if (force_cpu_type == timer) |
|
return -ENODEV; |
|
|
|
switch (vendor) { |
|
case X86_VENDOR_AMD: |
|
/* Needs to be at least an Athlon (or hammer in 32bit mode) */ |
|
|
|
switch (family) { |
|
case 6: |
|
cpu_type = "i386/athlon"; |
|
break; |
|
case 0xf: |
|
/* |
|
* Actually it could be i386/hammer too, but |
|
* give user space an consistent name. |
|
*/ |
|
cpu_type = "x86-64/hammer"; |
|
break; |
|
case 0x10: |
|
cpu_type = "x86-64/family10"; |
|
break; |
|
case 0x11: |
|
cpu_type = "x86-64/family11h"; |
|
break; |
|
case 0x12: |
|
cpu_type = "x86-64/family12h"; |
|
break; |
|
case 0x14: |
|
cpu_type = "x86-64/family14h"; |
|
break; |
|
case 0x15: |
|
cpu_type = "x86-64/family15h"; |
|
break; |
|
default: |
|
return -ENODEV; |
|
} |
|
model = &op_amd_spec; |
|
break; |
|
|
|
case X86_VENDOR_INTEL: |
|
switch (family) { |
|
/* Pentium IV */ |
|
case 0xf: |
|
p4_init(&cpu_type); |
|
break; |
|
|
|
/* A P6-class processor */ |
|
case 6: |
|
ppro_init(&cpu_type); |
|
break; |
|
|
|
default: |
|
break; |
|
} |
|
|
|
if (cpu_type) |
|
break; |
|
|
|
if (!boot_cpu_has(X86_FEATURE_ARCH_PERFMON)) |
|
return -ENODEV; |
|
|
|
/* use arch perfmon as fallback */ |
|
cpu_type = "i386/arch_perfmon"; |
|
model = &op_arch_perfmon_spec; |
|
break; |
|
|
|
default: |
|
return -ENODEV; |
|
} |
|
|
|
/* default values, can be overwritten by model */ |
|
ops->create_files = nmi_create_files; |
|
ops->setup = nmi_setup; |
|
ops->shutdown = nmi_shutdown; |
|
ops->start = nmi_start; |
|
ops->stop = nmi_stop; |
|
ops->cpu_type = cpu_type; |
|
|
|
if (model->init) |
|
ret = model->init(ops); |
|
if (ret) |
|
return ret; |
|
|
|
if (!model->num_virt_counters) |
|
model->num_virt_counters = model->num_counters; |
|
|
|
mux_init(ops); |
|
|
|
init_suspend_resume(); |
|
|
|
printk(KERN_INFO "oprofile: using NMI interrupt.\n"); |
|
return 0; |
|
} |
|
|
|
void op_nmi_exit(void) |
|
{ |
|
exit_suspend_resume(); |
|
}
|
|
|