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215 lines
4.7 KiB
215 lines
4.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright (c) 2018 Intel Corporation */ |
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#include "igc_mac.h" |
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#include "igc_nvm.h" |
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/** |
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* igc_poll_eerd_eewr_done - Poll for EEPROM read/write completion |
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* @hw: pointer to the HW structure |
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* @ee_reg: EEPROM flag for polling |
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* |
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* Polls the EEPROM status bit for either read or write completion based |
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* upon the value of 'ee_reg'. |
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*/ |
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static s32 igc_poll_eerd_eewr_done(struct igc_hw *hw, int ee_reg) |
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{ |
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s32 ret_val = -IGC_ERR_NVM; |
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u32 attempts = 100000; |
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u32 i, reg = 0; |
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for (i = 0; i < attempts; i++) { |
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if (ee_reg == IGC_NVM_POLL_READ) |
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reg = rd32(IGC_EERD); |
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else |
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reg = rd32(IGC_EEWR); |
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if (reg & IGC_NVM_RW_REG_DONE) { |
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ret_val = 0; |
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break; |
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} |
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udelay(5); |
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} |
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return ret_val; |
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} |
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/** |
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* igc_acquire_nvm - Generic request for access to EEPROM |
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* @hw: pointer to the HW structure |
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* |
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* Set the EEPROM access request bit and wait for EEPROM access grant bit. |
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* Return successful if access grant bit set, else clear the request for |
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* EEPROM access and return -IGC_ERR_NVM (-1). |
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*/ |
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s32 igc_acquire_nvm(struct igc_hw *hw) |
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{ |
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s32 timeout = IGC_NVM_GRANT_ATTEMPTS; |
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u32 eecd = rd32(IGC_EECD); |
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s32 ret_val = 0; |
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wr32(IGC_EECD, eecd | IGC_EECD_REQ); |
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eecd = rd32(IGC_EECD); |
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while (timeout) { |
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if (eecd & IGC_EECD_GNT) |
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break; |
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udelay(5); |
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eecd = rd32(IGC_EECD); |
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timeout--; |
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} |
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if (!timeout) { |
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eecd &= ~IGC_EECD_REQ; |
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wr32(IGC_EECD, eecd); |
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hw_dbg("Could not acquire NVM grant\n"); |
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ret_val = -IGC_ERR_NVM; |
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} |
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return ret_val; |
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} |
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/** |
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* igc_release_nvm - Release exclusive access to EEPROM |
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* @hw: pointer to the HW structure |
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* |
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* Stop any current commands to the EEPROM and clear the EEPROM request bit. |
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*/ |
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void igc_release_nvm(struct igc_hw *hw) |
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{ |
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u32 eecd; |
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eecd = rd32(IGC_EECD); |
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eecd &= ~IGC_EECD_REQ; |
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wr32(IGC_EECD, eecd); |
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} |
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/** |
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* igc_read_nvm_eerd - Reads EEPROM using EERD register |
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* @hw: pointer to the HW structure |
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* @offset: offset of word in the EEPROM to read |
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* @words: number of words to read |
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* @data: word read from the EEPROM |
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* |
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* Reads a 16 bit word from the EEPROM using the EERD register. |
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*/ |
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s32 igc_read_nvm_eerd(struct igc_hw *hw, u16 offset, u16 words, u16 *data) |
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{ |
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struct igc_nvm_info *nvm = &hw->nvm; |
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u32 i, eerd = 0; |
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s32 ret_val = 0; |
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/* A check for invalid values: offset too large, too many words, |
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* and not enough words. |
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*/ |
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if (offset >= nvm->word_size || (words > (nvm->word_size - offset)) || |
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words == 0) { |
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hw_dbg("nvm parameter(s) out of bounds\n"); |
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ret_val = -IGC_ERR_NVM; |
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goto out; |
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} |
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for (i = 0; i < words; i++) { |
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eerd = ((offset + i) << IGC_NVM_RW_ADDR_SHIFT) + |
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IGC_NVM_RW_REG_START; |
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wr32(IGC_EERD, eerd); |
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ret_val = igc_poll_eerd_eewr_done(hw, IGC_NVM_POLL_READ); |
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if (ret_val) |
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break; |
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data[i] = (rd32(IGC_EERD) >> IGC_NVM_RW_REG_DATA); |
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} |
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out: |
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return ret_val; |
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} |
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/** |
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* igc_read_mac_addr - Read device MAC address |
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* @hw: pointer to the HW structure |
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*/ |
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s32 igc_read_mac_addr(struct igc_hw *hw) |
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{ |
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u32 rar_high; |
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u32 rar_low; |
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u16 i; |
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rar_high = rd32(IGC_RAH(0)); |
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rar_low = rd32(IGC_RAL(0)); |
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for (i = 0; i < IGC_RAL_MAC_ADDR_LEN; i++) |
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hw->mac.perm_addr[i] = (u8)(rar_low >> (i * 8)); |
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for (i = 0; i < IGC_RAH_MAC_ADDR_LEN; i++) |
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hw->mac.perm_addr[i + 4] = (u8)(rar_high >> (i * 8)); |
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for (i = 0; i < ETH_ALEN; i++) |
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hw->mac.addr[i] = hw->mac.perm_addr[i]; |
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return 0; |
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} |
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/** |
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* igc_validate_nvm_checksum - Validate EEPROM checksum |
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* @hw: pointer to the HW structure |
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* |
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* Calculates the EEPROM checksum by reading/adding each word of the EEPROM |
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* and then verifies that the sum of the EEPROM is equal to 0xBABA. |
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*/ |
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s32 igc_validate_nvm_checksum(struct igc_hw *hw) |
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{ |
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u16 checksum = 0; |
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u16 i, nvm_data; |
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s32 ret_val = 0; |
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for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { |
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ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); |
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if (ret_val) { |
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hw_dbg("NVM Read Error\n"); |
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goto out; |
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} |
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checksum += nvm_data; |
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} |
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if (checksum != (u16)NVM_SUM) { |
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hw_dbg("NVM Checksum Invalid\n"); |
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ret_val = -IGC_ERR_NVM; |
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goto out; |
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} |
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out: |
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return ret_val; |
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} |
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/** |
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* igc_update_nvm_checksum - Update EEPROM checksum |
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* @hw: pointer to the HW structure |
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* |
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* Updates the EEPROM checksum by reading/adding each word of the EEPROM |
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* up to the checksum. Then calculates the EEPROM checksum and writes the |
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* value to the EEPROM. |
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*/ |
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s32 igc_update_nvm_checksum(struct igc_hw *hw) |
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{ |
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u16 checksum = 0; |
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u16 i, nvm_data; |
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s32 ret_val; |
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for (i = 0; i < NVM_CHECKSUM_REG; i++) { |
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ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); |
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if (ret_val) { |
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hw_dbg("NVM Read Error while updating checksum.\n"); |
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goto out; |
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} |
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checksum += nvm_data; |
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} |
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checksum = (u16)NVM_SUM - checksum; |
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ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); |
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if (ret_val) |
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hw_dbg("NVM Write Error while updating checksum.\n"); |
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out: |
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return ret_val; |
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}
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