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881 lines
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881 lines
25 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright (c) 2018 Intel Corporation */ |
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|
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#include <linux/pci.h> |
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#include <linux/delay.h> |
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|
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#include "igc_mac.h" |
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#include "igc_hw.h" |
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|
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/** |
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* igc_disable_pcie_master - Disables PCI-express master access |
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* @hw: pointer to the HW structure |
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* |
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* Returns 0 (0) if successful, else returns -10 |
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* (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused |
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* the master requests to be disabled. |
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* |
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* Disables PCI-Express master access and verifies there are no pending |
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* requests. |
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*/ |
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s32 igc_disable_pcie_master(struct igc_hw *hw) |
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{ |
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s32 timeout = MASTER_DISABLE_TIMEOUT; |
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s32 ret_val = 0; |
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u32 ctrl; |
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ctrl = rd32(IGC_CTRL); |
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ctrl |= IGC_CTRL_GIO_MASTER_DISABLE; |
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wr32(IGC_CTRL, ctrl); |
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|
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while (timeout) { |
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if (!(rd32(IGC_STATUS) & |
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IGC_STATUS_GIO_MASTER_ENABLE)) |
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break; |
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usleep_range(2000, 3000); |
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timeout--; |
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} |
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if (!timeout) { |
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hw_dbg("Master requests are pending.\n"); |
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ret_val = -IGC_ERR_MASTER_REQUESTS_PENDING; |
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goto out; |
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} |
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out: |
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return ret_val; |
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} |
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/** |
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* igc_init_rx_addrs - Initialize receive addresses |
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* @hw: pointer to the HW structure |
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* @rar_count: receive address registers |
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* |
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* Setup the receive address registers by setting the base receive address |
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* register to the devices MAC address and clearing all the other receive |
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* address registers to 0. |
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*/ |
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void igc_init_rx_addrs(struct igc_hw *hw, u16 rar_count) |
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{ |
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u8 mac_addr[ETH_ALEN] = {0}; |
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u32 i; |
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/* Setup the receive address */ |
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hw_dbg("Programming MAC Address into RAR[0]\n"); |
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hw->mac.ops.rar_set(hw, hw->mac.addr, 0); |
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/* Zero out the other (rar_entry_count - 1) receive addresses */ |
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hw_dbg("Clearing RAR[1-%u]\n", rar_count - 1); |
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for (i = 1; i < rar_count; i++) |
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hw->mac.ops.rar_set(hw, mac_addr, i); |
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} |
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/** |
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* igc_set_fc_watermarks - Set flow control high/low watermarks |
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* @hw: pointer to the HW structure |
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* |
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* Sets the flow control high/low threshold (watermark) registers. If |
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* flow control XON frame transmission is enabled, then set XON frame |
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* transmission as well. |
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*/ |
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static s32 igc_set_fc_watermarks(struct igc_hw *hw) |
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{ |
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u32 fcrtl = 0, fcrth = 0; |
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|
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/* Set the flow control receive threshold registers. Normally, |
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* these registers will be set to a default threshold that may be |
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* adjusted later by the driver's runtime code. However, if the |
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* ability to transmit pause frames is not enabled, then these |
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* registers will be set to 0. |
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*/ |
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if (hw->fc.current_mode & igc_fc_tx_pause) { |
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/* We need to set up the Receive Threshold high and low water |
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* marks as well as (optionally) enabling the transmission of |
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* XON frames. |
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*/ |
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fcrtl = hw->fc.low_water; |
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if (hw->fc.send_xon) |
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fcrtl |= IGC_FCRTL_XONE; |
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fcrth = hw->fc.high_water; |
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} |
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wr32(IGC_FCRTL, fcrtl); |
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wr32(IGC_FCRTH, fcrth); |
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return 0; |
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} |
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/** |
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* igc_setup_link - Setup flow control and link settings |
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* @hw: pointer to the HW structure |
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* |
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* Determines which flow control settings to use, then configures flow |
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* control. Calls the appropriate media-specific link configuration |
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* function. Assuming the adapter has a valid link partner, a valid link |
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* should be established. Assumes the hardware has previously been reset |
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* and the transmitter and receiver are not enabled. |
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*/ |
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s32 igc_setup_link(struct igc_hw *hw) |
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{ |
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s32 ret_val = 0; |
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|
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/* In the case of the phy reset being blocked, we already have a link. |
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* We do not need to set it up again. |
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*/ |
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if (igc_check_reset_block(hw)) |
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goto out; |
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/* If requested flow control is set to default, set flow control |
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* to the both 'rx' and 'tx' pause frames. |
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*/ |
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if (hw->fc.requested_mode == igc_fc_default) |
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hw->fc.requested_mode = igc_fc_full; |
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/* We want to save off the original Flow Control configuration just |
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* in case we get disconnected and then reconnected into a different |
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* hub or switch with different Flow Control capabilities. |
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*/ |
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hw->fc.current_mode = hw->fc.requested_mode; |
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hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); |
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/* Call the necessary media_type subroutine to configure the link. */ |
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ret_val = hw->mac.ops.setup_physical_interface(hw); |
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if (ret_val) |
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goto out; |
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/* Initialize the flow control address, type, and PAUSE timer |
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* registers to their default values. This is done even if flow |
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* control is disabled, because it does not hurt anything to |
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* initialize these registers. |
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*/ |
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hw_dbg("Initializing the Flow Control address, type and timer regs\n"); |
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wr32(IGC_FCT, FLOW_CONTROL_TYPE); |
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wr32(IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH); |
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wr32(IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW); |
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wr32(IGC_FCTTV, hw->fc.pause_time); |
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ret_val = igc_set_fc_watermarks(hw); |
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out: |
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return ret_val; |
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} |
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/** |
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* igc_force_mac_fc - Force the MAC's flow control settings |
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* @hw: pointer to the HW structure |
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* |
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* Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the |
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* device control register to reflect the adapter settings. TFCE and RFCE |
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* need to be explicitly set by software when a copper PHY is used because |
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* autonegotiation is managed by the PHY rather than the MAC. Software must |
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* also configure these bits when link is forced on a fiber connection. |
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*/ |
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s32 igc_force_mac_fc(struct igc_hw *hw) |
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{ |
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s32 ret_val = 0; |
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u32 ctrl; |
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ctrl = rd32(IGC_CTRL); |
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/* Because we didn't get link via the internal auto-negotiation |
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* mechanism (we either forced link or we got link via PHY |
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* auto-neg), we have to manually enable/disable transmit an |
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* receive flow control. |
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* |
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* The "Case" statement below enables/disable flow control |
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* according to the "hw->fc.current_mode" parameter. |
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* |
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* The possible values of the "fc" parameter are: |
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* 0: Flow control is completely disabled |
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* 1: Rx flow control is enabled (we can receive pause |
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* frames but not send pause frames). |
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* 2: Tx flow control is enabled (we can send pause frames |
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* frames but we do not receive pause frames). |
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* 3: Both Rx and TX flow control (symmetric) is enabled. |
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* other: No other values should be possible at this point. |
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*/ |
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hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); |
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switch (hw->fc.current_mode) { |
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case igc_fc_none: |
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ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE)); |
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break; |
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case igc_fc_rx_pause: |
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ctrl &= (~IGC_CTRL_TFCE); |
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ctrl |= IGC_CTRL_RFCE; |
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break; |
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case igc_fc_tx_pause: |
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ctrl &= (~IGC_CTRL_RFCE); |
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ctrl |= IGC_CTRL_TFCE; |
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break; |
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case igc_fc_full: |
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ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE); |
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break; |
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default: |
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hw_dbg("Flow control param set incorrectly\n"); |
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ret_val = -IGC_ERR_CONFIG; |
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goto out; |
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} |
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wr32(IGC_CTRL, ctrl); |
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out: |
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return ret_val; |
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} |
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/** |
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* igc_clear_hw_cntrs_base - Clear base hardware counters |
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* @hw: pointer to the HW structure |
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* |
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* Clears the base hardware counters by reading the counter registers. |
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*/ |
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void igc_clear_hw_cntrs_base(struct igc_hw *hw) |
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{ |
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rd32(IGC_CRCERRS); |
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rd32(IGC_MPC); |
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rd32(IGC_SCC); |
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rd32(IGC_ECOL); |
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rd32(IGC_MCC); |
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rd32(IGC_LATECOL); |
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rd32(IGC_COLC); |
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rd32(IGC_RERC); |
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rd32(IGC_DC); |
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rd32(IGC_RLEC); |
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rd32(IGC_XONRXC); |
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rd32(IGC_XONTXC); |
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rd32(IGC_XOFFRXC); |
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rd32(IGC_XOFFTXC); |
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rd32(IGC_FCRUC); |
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rd32(IGC_GPRC); |
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rd32(IGC_BPRC); |
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rd32(IGC_MPRC); |
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rd32(IGC_GPTC); |
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rd32(IGC_GORCL); |
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rd32(IGC_GORCH); |
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rd32(IGC_GOTCL); |
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rd32(IGC_GOTCH); |
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rd32(IGC_RNBC); |
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rd32(IGC_RUC); |
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rd32(IGC_RFC); |
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rd32(IGC_ROC); |
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rd32(IGC_RJC); |
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rd32(IGC_TORL); |
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rd32(IGC_TORH); |
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rd32(IGC_TOTL); |
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rd32(IGC_TOTH); |
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rd32(IGC_TPR); |
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rd32(IGC_TPT); |
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rd32(IGC_MPTC); |
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rd32(IGC_BPTC); |
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rd32(IGC_PRC64); |
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rd32(IGC_PRC127); |
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rd32(IGC_PRC255); |
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rd32(IGC_PRC511); |
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rd32(IGC_PRC1023); |
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rd32(IGC_PRC1522); |
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rd32(IGC_PTC64); |
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rd32(IGC_PTC127); |
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rd32(IGC_PTC255); |
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rd32(IGC_PTC511); |
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rd32(IGC_PTC1023); |
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rd32(IGC_PTC1522); |
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rd32(IGC_ALGNERRC); |
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rd32(IGC_RXERRC); |
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rd32(IGC_TNCRS); |
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rd32(IGC_HTDPMC); |
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rd32(IGC_TSCTC); |
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rd32(IGC_MGTPRC); |
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rd32(IGC_MGTPDC); |
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rd32(IGC_MGTPTC); |
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rd32(IGC_IAC); |
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rd32(IGC_RPTHC); |
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rd32(IGC_TLPIC); |
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rd32(IGC_RLPIC); |
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rd32(IGC_HGPTC); |
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rd32(IGC_RXDMTC); |
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rd32(IGC_HGORCL); |
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rd32(IGC_HGORCH); |
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rd32(IGC_HGOTCL); |
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rd32(IGC_HGOTCH); |
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rd32(IGC_LENERRS); |
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} |
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/** |
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* igc_rar_set - Set receive address register |
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* @hw: pointer to the HW structure |
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* @addr: pointer to the receive address |
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* @index: receive address array register |
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* |
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* Sets the receive address array register at index to the address passed |
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* in by addr. |
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*/ |
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void igc_rar_set(struct igc_hw *hw, u8 *addr, u32 index) |
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{ |
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u32 rar_low, rar_high; |
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|
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/* HW expects these in little endian so we reverse the byte order |
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* from network order (big endian) to little endian |
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*/ |
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rar_low = ((u32)addr[0] | |
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((u32)addr[1] << 8) | |
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((u32)addr[2] << 16) | ((u32)addr[3] << 24)); |
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rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); |
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/* If MAC address zero, no need to set the AV bit */ |
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if (rar_low || rar_high) |
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rar_high |= IGC_RAH_AV; |
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/* Some bridges will combine consecutive 32-bit writes into |
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* a single burst write, which will malfunction on some parts. |
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* The flushes avoid this. |
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*/ |
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wr32(IGC_RAL(index), rar_low); |
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wrfl(); |
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wr32(IGC_RAH(index), rar_high); |
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wrfl(); |
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} |
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/** |
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* igc_check_for_copper_link - Check for link (Copper) |
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* @hw: pointer to the HW structure |
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* |
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* Checks to see of the link status of the hardware has changed. If a |
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* change in link status has been detected, then we read the PHY registers |
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* to get the current speed/duplex if link exists. |
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*/ |
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s32 igc_check_for_copper_link(struct igc_hw *hw) |
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{ |
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struct igc_mac_info *mac = &hw->mac; |
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bool link = false; |
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s32 ret_val; |
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|
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/* We only want to go out to the PHY registers to see if Auto-Neg |
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* has completed and/or if our link status has changed. The |
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* get_link_status flag is set upon receiving a Link Status |
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* Change or Rx Sequence Error interrupt. |
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*/ |
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if (!mac->get_link_status) { |
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ret_val = 0; |
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goto out; |
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} |
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/* First we want to see if the MII Status Register reports |
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* link. If so, then we want to get the current speed/duplex |
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* of the PHY. |
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*/ |
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ret_val = igc_phy_has_link(hw, 1, 0, &link); |
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if (ret_val) |
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goto out; |
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if (!link) |
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goto out; /* No link detected */ |
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mac->get_link_status = false; |
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/* Check if there was DownShift, must be checked |
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* immediately after link-up |
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*/ |
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igc_check_downshift(hw); |
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/* If we are forcing speed/duplex, then we simply return since |
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* we have already determined whether we have link or not. |
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*/ |
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if (!mac->autoneg) { |
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ret_val = -IGC_ERR_CONFIG; |
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goto out; |
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} |
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/* Auto-Neg is enabled. Auto Speed Detection takes care |
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* of MAC speed/duplex configuration. So we only need to |
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* configure Collision Distance in the MAC. |
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*/ |
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igc_config_collision_dist(hw); |
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|
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/* Configure Flow Control now that Auto-Neg has completed. |
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* First, we need to restore the desired flow control |
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* settings because we may have had to re-autoneg with a |
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* different link partner. |
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*/ |
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ret_val = igc_config_fc_after_link_up(hw); |
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if (ret_val) |
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hw_dbg("Error configuring flow control\n"); |
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out: |
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/* Now that we are aware of our link settings, we can set the LTR |
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* thresholds. |
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*/ |
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ret_val = igc_set_ltr_i225(hw, link); |
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return ret_val; |
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} |
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/** |
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* igc_config_collision_dist - Configure collision distance |
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* @hw: pointer to the HW structure |
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* |
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* Configures the collision distance to the default value and is used |
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* during link setup. Currently no func pointer exists and all |
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* implementations are handled in the generic version of this function. |
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*/ |
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void igc_config_collision_dist(struct igc_hw *hw) |
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{ |
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u32 tctl; |
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tctl = rd32(IGC_TCTL); |
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tctl &= ~IGC_TCTL_COLD; |
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tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT; |
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wr32(IGC_TCTL, tctl); |
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wrfl(); |
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} |
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/** |
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* igc_config_fc_after_link_up - Configures flow control after link |
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* @hw: pointer to the HW structure |
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* |
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* Checks the status of auto-negotiation after link up to ensure that the |
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* speed and duplex were not forced. If the link needed to be forced, then |
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* flow control needs to be forced also. If auto-negotiation is enabled |
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* and did not fail, then we configure flow control based on our link |
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* partner. |
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*/ |
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s32 igc_config_fc_after_link_up(struct igc_hw *hw) |
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{ |
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u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; |
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struct igc_mac_info *mac = &hw->mac; |
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u16 speed, duplex; |
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s32 ret_val = 0; |
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|
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/* Check for the case where we have fiber media and auto-neg failed |
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* so we had to force link. In this case, we need to force the |
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* configuration of the MAC to match the "fc" parameter. |
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*/ |
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if (mac->autoneg_failed) |
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ret_val = igc_force_mac_fc(hw); |
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if (ret_val) { |
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hw_dbg("Error forcing flow control settings\n"); |
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goto out; |
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} |
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|
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/* Check for the case where we have copper media and auto-neg is |
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* enabled. In this case, we need to check and see if Auto-Neg |
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* has completed, and if so, how the PHY and link partner has |
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* flow control configured. |
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*/ |
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if (mac->autoneg) { |
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/* Read the MII Status Register and check to see if AutoNeg |
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* has completed. We read this twice because this reg has |
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* some "sticky" (latched) bits. |
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*/ |
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ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, |
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&mii_status_reg); |
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if (ret_val) |
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goto out; |
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ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, |
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&mii_status_reg); |
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if (ret_val) |
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goto out; |
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|
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if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { |
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hw_dbg("Copper PHY and Auto Neg has not completed.\n"); |
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goto out; |
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} |
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|
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/* The AutoNeg process has completed, so we now need to |
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* read both the Auto Negotiation Advertisement |
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* Register (Address 4) and the Auto_Negotiation Base |
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* Page Ability Register (Address 5) to determine how |
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* flow control was negotiated. |
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*/ |
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ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, |
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&mii_nway_adv_reg); |
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if (ret_val) |
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goto out; |
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ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, |
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&mii_nway_lp_ability_reg); |
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if (ret_val) |
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goto out; |
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/* Two bits in the Auto Negotiation Advertisement Register |
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* (Address 4) and two bits in the Auto Negotiation Base |
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* Page Ability Register (Address 5) determine flow control |
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* for both the PHY and the link partner. The following |
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* table, taken out of the IEEE 802.3ab/D6.0 dated March 25, |
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* 1999, describes these PAUSE resolution bits and how flow |
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* control is determined based upon these settings. |
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* NOTE: DC = Don't Care |
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* |
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* LOCAL DEVICE | LINK PARTNER |
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* PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution |
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*-------|---------|-------|---------|-------------------- |
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* 0 | 0 | DC | DC | igc_fc_none |
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* 0 | 1 | 0 | DC | igc_fc_none |
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* 0 | 1 | 1 | 0 | igc_fc_none |
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* 0 | 1 | 1 | 1 | igc_fc_tx_pause |
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* 1 | 0 | 0 | DC | igc_fc_none |
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* 1 | DC | 1 | DC | igc_fc_full |
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* 1 | 1 | 0 | 0 | igc_fc_none |
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* 1 | 1 | 0 | 1 | igc_fc_rx_pause |
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* |
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* Are both PAUSE bits set to 1? If so, this implies |
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* Symmetric Flow Control is enabled at both ends. The |
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* ASM_DIR bits are irrelevant per the spec. |
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* |
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* For Symmetric Flow Control: |
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* |
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* LOCAL DEVICE | LINK PARTNER |
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* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
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*-------|---------|-------|---------|-------------------- |
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* 1 | DC | 1 | DC | IGC_fc_full |
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* |
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*/ |
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if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
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(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { |
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/* Now we need to check if the user selected RX ONLY |
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* of pause frames. In this case, we had to advertise |
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* FULL flow control because we could not advertise RX |
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* ONLY. Hence, we must now check to see if we need to |
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* turn OFF the TRANSMISSION of PAUSE frames. |
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*/ |
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if (hw->fc.requested_mode == igc_fc_full) { |
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hw->fc.current_mode = igc_fc_full; |
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hw_dbg("Flow Control = FULL.\n"); |
|
} else { |
|
hw->fc.current_mode = igc_fc_rx_pause; |
|
hw_dbg("Flow Control = RX PAUSE frames only.\n"); |
|
} |
|
} |
|
|
|
/* For receiving PAUSE frames ONLY. |
|
* |
|
* LOCAL DEVICE | LINK PARTNER |
|
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
*-------|---------|-------|---------|-------------------- |
|
* 0 | 1 | 1 | 1 | igc_fc_tx_pause |
|
*/ |
|
else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
(mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
|
(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
|
(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
|
hw->fc.current_mode = igc_fc_tx_pause; |
|
hw_dbg("Flow Control = TX PAUSE frames only.\n"); |
|
} |
|
/* For transmitting PAUSE frames ONLY. |
|
* |
|
* LOCAL DEVICE | LINK PARTNER |
|
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
|
*-------|---------|-------|---------|-------------------- |
|
* 1 | 1 | 0 | 1 | igc_fc_rx_pause |
|
*/ |
|
else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
|
(mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
|
!(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
|
(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
|
hw->fc.current_mode = igc_fc_rx_pause; |
|
hw_dbg("Flow Control = RX PAUSE frames only.\n"); |
|
} |
|
/* Per the IEEE spec, at this point flow control should be |
|
* disabled. However, we want to consider that we could |
|
* be connected to a legacy switch that doesn't advertise |
|
* desired flow control, but can be forced on the link |
|
* partner. So if we advertised no flow control, that is |
|
* what we will resolve to. If we advertised some kind of |
|
* receive capability (Rx Pause Only or Full Flow Control) |
|
* and the link partner advertised none, we will configure |
|
* ourselves to enable Rx Flow Control only. We can do |
|
* this safely for two reasons: If the link partner really |
|
* didn't want flow control enabled, and we enable Rx, no |
|
* harm done since we won't be receiving any PAUSE frames |
|
* anyway. If the intent on the link partner was to have |
|
* flow control enabled, then by us enabling RX only, we |
|
* can at least receive pause frames and process them. |
|
* This is a good idea because in most cases, since we are |
|
* predominantly a server NIC, more times than not we will |
|
* be asked to delay transmission of packets than asking |
|
* our link partner to pause transmission of frames. |
|
*/ |
|
else if ((hw->fc.requested_mode == igc_fc_none) || |
|
(hw->fc.requested_mode == igc_fc_tx_pause) || |
|
(hw->fc.strict_ieee)) { |
|
hw->fc.current_mode = igc_fc_none; |
|
hw_dbg("Flow Control = NONE.\n"); |
|
} else { |
|
hw->fc.current_mode = igc_fc_rx_pause; |
|
hw_dbg("Flow Control = RX PAUSE frames only.\n"); |
|
} |
|
|
|
/* Now we need to do one last check... If we auto- |
|
* negotiated to HALF DUPLEX, flow control should not be |
|
* enabled per IEEE 802.3 spec. |
|
*/ |
|
ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex); |
|
if (ret_val) { |
|
hw_dbg("Error getting link speed and duplex\n"); |
|
goto out; |
|
} |
|
|
|
if (duplex == HALF_DUPLEX) |
|
hw->fc.current_mode = igc_fc_none; |
|
|
|
/* Now we call a subroutine to actually force the MAC |
|
* controller to use the correct flow control settings. |
|
*/ |
|
ret_val = igc_force_mac_fc(hw); |
|
if (ret_val) { |
|
hw_dbg("Error forcing flow control settings\n"); |
|
goto out; |
|
} |
|
} |
|
|
|
out: |
|
return ret_val; |
|
} |
|
|
|
/** |
|
* igc_get_auto_rd_done - Check for auto read completion |
|
* @hw: pointer to the HW structure |
|
* |
|
* Check EEPROM for Auto Read done bit. |
|
*/ |
|
s32 igc_get_auto_rd_done(struct igc_hw *hw) |
|
{ |
|
s32 ret_val = 0; |
|
s32 i = 0; |
|
|
|
while (i < AUTO_READ_DONE_TIMEOUT) { |
|
if (rd32(IGC_EECD) & IGC_EECD_AUTO_RD) |
|
break; |
|
usleep_range(1000, 2000); |
|
i++; |
|
} |
|
|
|
if (i == AUTO_READ_DONE_TIMEOUT) { |
|
hw_dbg("Auto read by HW from NVM has not completed.\n"); |
|
ret_val = -IGC_ERR_RESET; |
|
goto out; |
|
} |
|
|
|
out: |
|
return ret_val; |
|
} |
|
|
|
/** |
|
* igc_get_speed_and_duplex_copper - Retrieve current speed/duplex |
|
* @hw: pointer to the HW structure |
|
* @speed: stores the current speed |
|
* @duplex: stores the current duplex |
|
* |
|
* Read the status register for the current speed/duplex and store the current |
|
* speed and duplex for copper connections. |
|
*/ |
|
s32 igc_get_speed_and_duplex_copper(struct igc_hw *hw, u16 *speed, |
|
u16 *duplex) |
|
{ |
|
u32 status; |
|
|
|
status = rd32(IGC_STATUS); |
|
if (status & IGC_STATUS_SPEED_1000) { |
|
/* For I225, STATUS will indicate 1G speed in both 1 Gbps |
|
* and 2.5 Gbps link modes. An additional bit is used |
|
* to differentiate between 1 Gbps and 2.5 Gbps. |
|
*/ |
|
if (hw->mac.type == igc_i225 && |
|
(status & IGC_STATUS_SPEED_2500)) { |
|
*speed = SPEED_2500; |
|
hw_dbg("2500 Mbs, "); |
|
} else { |
|
*speed = SPEED_1000; |
|
hw_dbg("1000 Mbs, "); |
|
} |
|
} else if (status & IGC_STATUS_SPEED_100) { |
|
*speed = SPEED_100; |
|
hw_dbg("100 Mbs, "); |
|
} else { |
|
*speed = SPEED_10; |
|
hw_dbg("10 Mbs, "); |
|
} |
|
|
|
if (status & IGC_STATUS_FD) { |
|
*duplex = FULL_DUPLEX; |
|
hw_dbg("Full Duplex\n"); |
|
} else { |
|
*duplex = HALF_DUPLEX; |
|
hw_dbg("Half Duplex\n"); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* igc_put_hw_semaphore - Release hardware semaphore |
|
* @hw: pointer to the HW structure |
|
* |
|
* Release hardware semaphore used to access the PHY or NVM |
|
*/ |
|
void igc_put_hw_semaphore(struct igc_hw *hw) |
|
{ |
|
u32 swsm; |
|
|
|
swsm = rd32(IGC_SWSM); |
|
|
|
swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI); |
|
|
|
wr32(IGC_SWSM, swsm); |
|
} |
|
|
|
/** |
|
* igc_enable_mng_pass_thru - Enable processing of ARP's |
|
* @hw: pointer to the HW structure |
|
* |
|
* Verifies the hardware needs to leave interface enabled so that frames can |
|
* be directed to and from the management interface. |
|
*/ |
|
bool igc_enable_mng_pass_thru(struct igc_hw *hw) |
|
{ |
|
bool ret_val = false; |
|
u32 fwsm, factps; |
|
u32 manc; |
|
|
|
if (!hw->mac.asf_firmware_present) |
|
goto out; |
|
|
|
manc = rd32(IGC_MANC); |
|
|
|
if (!(manc & IGC_MANC_RCV_TCO_EN)) |
|
goto out; |
|
|
|
if (hw->mac.arc_subsystem_valid) { |
|
fwsm = rd32(IGC_FWSM); |
|
factps = rd32(IGC_FACTPS); |
|
|
|
if (!(factps & IGC_FACTPS_MNGCG) && |
|
((fwsm & IGC_FWSM_MODE_MASK) == |
|
(igc_mng_mode_pt << IGC_FWSM_MODE_SHIFT))) { |
|
ret_val = true; |
|
goto out; |
|
} |
|
} else { |
|
if ((manc & IGC_MANC_SMBUS_EN) && |
|
!(manc & IGC_MANC_ASF_EN)) { |
|
ret_val = true; |
|
goto out; |
|
} |
|
} |
|
|
|
out: |
|
return ret_val; |
|
} |
|
|
|
/** |
|
* igc_hash_mc_addr - Generate a multicast hash value |
|
* @hw: pointer to the HW structure |
|
* @mc_addr: pointer to a multicast address |
|
* |
|
* Generates a multicast address hash value which is used to determine |
|
* the multicast filter table array address and new table value. See |
|
* igc_mta_set() |
|
**/ |
|
static u32 igc_hash_mc_addr(struct igc_hw *hw, u8 *mc_addr) |
|
{ |
|
u32 hash_value, hash_mask; |
|
u8 bit_shift = 0; |
|
|
|
/* Register count multiplied by bits per register */ |
|
hash_mask = (hw->mac.mta_reg_count * 32) - 1; |
|
|
|
/* For a mc_filter_type of 0, bit_shift is the number of left-shifts |
|
* where 0xFF would still fall within the hash mask. |
|
*/ |
|
while (hash_mask >> bit_shift != 0xFF) |
|
bit_shift++; |
|
|
|
/* The portion of the address that is used for the hash table |
|
* is determined by the mc_filter_type setting. |
|
* The algorithm is such that there is a total of 8 bits of shifting. |
|
* The bit_shift for a mc_filter_type of 0 represents the number of |
|
* left-shifts where the MSB of mc_addr[5] would still fall within |
|
* the hash_mask. Case 0 does this exactly. Since there are a total |
|
* of 8 bits of shifting, then mc_addr[4] will shift right the |
|
* remaining number of bits. Thus 8 - bit_shift. The rest of the |
|
* cases are a variation of this algorithm...essentially raising the |
|
* number of bits to shift mc_addr[5] left, while still keeping the |
|
* 8-bit shifting total. |
|
* |
|
* For example, given the following Destination MAC Address and an |
|
* MTA register count of 128 (thus a 4096-bit vector and 0xFFF mask), |
|
* we can see that the bit_shift for case 0 is 4. These are the hash |
|
* values resulting from each mc_filter_type... |
|
* [0] [1] [2] [3] [4] [5] |
|
* 01 AA 00 12 34 56 |
|
* LSB MSB |
|
* |
|
* case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 |
|
* case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 |
|
* case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 |
|
* case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 |
|
*/ |
|
switch (hw->mac.mc_filter_type) { |
|
default: |
|
case 0: |
|
break; |
|
case 1: |
|
bit_shift += 1; |
|
break; |
|
case 2: |
|
bit_shift += 2; |
|
break; |
|
case 3: |
|
bit_shift += 4; |
|
break; |
|
} |
|
|
|
hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | |
|
(((u16)mc_addr[5]) << bit_shift))); |
|
|
|
return hash_value; |
|
} |
|
|
|
/** |
|
* igc_update_mc_addr_list - Update Multicast addresses |
|
* @hw: pointer to the HW structure |
|
* @mc_addr_list: array of multicast addresses to program |
|
* @mc_addr_count: number of multicast addresses to program |
|
* |
|
* Updates entire Multicast Table Array. |
|
* The caller must have a packed mc_addr_list of multicast addresses. |
|
**/ |
|
void igc_update_mc_addr_list(struct igc_hw *hw, |
|
u8 *mc_addr_list, u32 mc_addr_count) |
|
{ |
|
u32 hash_value, hash_bit, hash_reg; |
|
int i; |
|
|
|
/* clear mta_shadow */ |
|
memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); |
|
|
|
/* update mta_shadow from mc_addr_list */ |
|
for (i = 0; (u32)i < mc_addr_count; i++) { |
|
hash_value = igc_hash_mc_addr(hw, mc_addr_list); |
|
|
|
hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); |
|
hash_bit = hash_value & 0x1F; |
|
|
|
hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit); |
|
mc_addr_list += ETH_ALEN; |
|
} |
|
|
|
/* replace the entire MTA table */ |
|
for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) |
|
array_wr32(IGC_MTA, i, hw->mac.mta_shadow[i]); |
|
wrfl(); |
|
}
|
|
|