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645 lines
16 KiB
645 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright (c) 2018 Intel Corporation */ |
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#include <linux/delay.h> |
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#include "igc_hw.h" |
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/** |
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* igc_acquire_nvm_i225 - Acquire exclusive access to EEPROM |
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* @hw: pointer to the HW structure |
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* |
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* Acquire the necessary semaphores for exclusive access to the EEPROM. |
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* Set the EEPROM access request bit and wait for EEPROM access grant bit. |
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* Return successful if access grant bit set, else clear the request for |
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* EEPROM access and return -IGC_ERR_NVM (-1). |
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*/ |
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static s32 igc_acquire_nvm_i225(struct igc_hw *hw) |
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{ |
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return igc_acquire_swfw_sync_i225(hw, IGC_SWFW_EEP_SM); |
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} |
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/** |
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* igc_release_nvm_i225 - Release exclusive access to EEPROM |
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* @hw: pointer to the HW structure |
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* |
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* Stop any current commands to the EEPROM and clear the EEPROM request bit, |
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* then release the semaphores acquired. |
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*/ |
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static void igc_release_nvm_i225(struct igc_hw *hw) |
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{ |
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igc_release_swfw_sync_i225(hw, IGC_SWFW_EEP_SM); |
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} |
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/** |
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* igc_get_hw_semaphore_i225 - Acquire hardware semaphore |
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* @hw: pointer to the HW structure |
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* |
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* Acquire the HW semaphore to access the PHY or NVM |
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*/ |
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static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw) |
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{ |
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s32 timeout = hw->nvm.word_size + 1; |
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s32 i = 0; |
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u32 swsm; |
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/* Get the SW semaphore */ |
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while (i < timeout) { |
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swsm = rd32(IGC_SWSM); |
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if (!(swsm & IGC_SWSM_SMBI)) |
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break; |
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usleep_range(500, 600); |
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i++; |
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} |
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if (i == timeout) { |
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/* In rare circumstances, the SW semaphore may already be held |
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* unintentionally. Clear the semaphore once before giving up. |
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*/ |
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if (hw->dev_spec._base.clear_semaphore_once) { |
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hw->dev_spec._base.clear_semaphore_once = false; |
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igc_put_hw_semaphore(hw); |
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for (i = 0; i < timeout; i++) { |
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swsm = rd32(IGC_SWSM); |
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if (!(swsm & IGC_SWSM_SMBI)) |
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break; |
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usleep_range(500, 600); |
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} |
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} |
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/* If we do not have the semaphore here, we have to give up. */ |
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if (i == timeout) { |
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hw_dbg("Driver can't access device - SMBI bit is set.\n"); |
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return -IGC_ERR_NVM; |
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} |
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} |
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/* Get the FW semaphore. */ |
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for (i = 0; i < timeout; i++) { |
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swsm = rd32(IGC_SWSM); |
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wr32(IGC_SWSM, swsm | IGC_SWSM_SWESMBI); |
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/* Semaphore acquired if bit latched */ |
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if (rd32(IGC_SWSM) & IGC_SWSM_SWESMBI) |
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break; |
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usleep_range(500, 600); |
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} |
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if (i == timeout) { |
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/* Release semaphores */ |
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igc_put_hw_semaphore(hw); |
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hw_dbg("Driver can't access the NVM\n"); |
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return -IGC_ERR_NVM; |
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} |
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return 0; |
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} |
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/** |
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* igc_acquire_swfw_sync_i225 - Acquire SW/FW semaphore |
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* @hw: pointer to the HW structure |
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* @mask: specifies which semaphore to acquire |
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* |
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* Acquire the SW/FW semaphore to access the PHY or NVM. The mask |
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* will also specify which port we're acquiring the lock for. |
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*/ |
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s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask) |
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{ |
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s32 i = 0, timeout = 200; |
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u32 fwmask = mask << 16; |
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u32 swmask = mask; |
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s32 ret_val = 0; |
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u32 swfw_sync; |
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while (i < timeout) { |
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if (igc_get_hw_semaphore_i225(hw)) { |
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ret_val = -IGC_ERR_SWFW_SYNC; |
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goto out; |
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} |
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swfw_sync = rd32(IGC_SW_FW_SYNC); |
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if (!(swfw_sync & (fwmask | swmask))) |
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break; |
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/* Firmware currently using resource (fwmask) */ |
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igc_put_hw_semaphore(hw); |
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mdelay(5); |
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i++; |
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} |
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if (i == timeout) { |
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hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); |
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ret_val = -IGC_ERR_SWFW_SYNC; |
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goto out; |
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} |
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swfw_sync |= swmask; |
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wr32(IGC_SW_FW_SYNC, swfw_sync); |
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igc_put_hw_semaphore(hw); |
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out: |
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return ret_val; |
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} |
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/** |
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* igc_release_swfw_sync_i225 - Release SW/FW semaphore |
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* @hw: pointer to the HW structure |
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* @mask: specifies which semaphore to acquire |
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* |
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* Release the SW/FW semaphore used to access the PHY or NVM. The mask |
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* will also specify which port we're releasing the lock for. |
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*/ |
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void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask) |
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{ |
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u32 swfw_sync; |
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while (igc_get_hw_semaphore_i225(hw)) |
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; /* Empty */ |
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swfw_sync = rd32(IGC_SW_FW_SYNC); |
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swfw_sync &= ~mask; |
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wr32(IGC_SW_FW_SYNC, swfw_sync); |
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igc_put_hw_semaphore(hw); |
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} |
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/** |
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* igc_read_nvm_srrd_i225 - Reads Shadow Ram using EERD register |
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* @hw: pointer to the HW structure |
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* @offset: offset of word in the Shadow Ram to read |
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* @words: number of words to read |
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* @data: word read from the Shadow Ram |
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* |
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* Reads a 16 bit word from the Shadow Ram using the EERD register. |
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* Uses necessary synchronization semaphores. |
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*/ |
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static s32 igc_read_nvm_srrd_i225(struct igc_hw *hw, u16 offset, u16 words, |
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u16 *data) |
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{ |
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s32 status = 0; |
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u16 i, count; |
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/* We cannot hold synchronization semaphores for too long, |
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* because of forceful takeover procedure. However it is more efficient |
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* to read in bursts than synchronizing access for each word. |
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*/ |
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for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) { |
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count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ? |
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IGC_EERD_EEWR_MAX_COUNT : (words - i); |
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status = hw->nvm.ops.acquire(hw); |
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if (status) |
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break; |
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status = igc_read_nvm_eerd(hw, offset, count, data + i); |
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hw->nvm.ops.release(hw); |
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if (status) |
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break; |
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} |
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return status; |
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} |
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/** |
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* igc_write_nvm_srwr - Write to Shadow Ram using EEWR |
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* @hw: pointer to the HW structure |
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* @offset: offset within the Shadow Ram to be written to |
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* @words: number of words to write |
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* @data: 16 bit word(s) to be written to the Shadow Ram |
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* |
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* Writes data to Shadow Ram at offset using EEWR register. |
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* |
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* If igc_update_nvm_checksum is not called after this function , the |
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* Shadow Ram will most likely contain an invalid checksum. |
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*/ |
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static s32 igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words, |
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u16 *data) |
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{ |
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struct igc_nvm_info *nvm = &hw->nvm; |
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s32 ret_val = -IGC_ERR_NVM; |
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u32 attempts = 100000; |
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u32 i, k, eewr = 0; |
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/* A check for invalid values: offset too large, too many words, |
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* too many words for the offset, and not enough words. |
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*/ |
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if (offset >= nvm->word_size || (words > (nvm->word_size - offset)) || |
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words == 0) { |
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hw_dbg("nvm parameter(s) out of bounds\n"); |
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return ret_val; |
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} |
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for (i = 0; i < words; i++) { |
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ret_val = -IGC_ERR_NVM; |
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eewr = ((offset + i) << IGC_NVM_RW_ADDR_SHIFT) | |
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(data[i] << IGC_NVM_RW_REG_DATA) | |
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IGC_NVM_RW_REG_START; |
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wr32(IGC_SRWR, eewr); |
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for (k = 0; k < attempts; k++) { |
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if (IGC_NVM_RW_REG_DONE & |
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rd32(IGC_SRWR)) { |
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ret_val = 0; |
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break; |
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} |
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udelay(5); |
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} |
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if (ret_val) { |
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hw_dbg("Shadow RAM write EEWR timed out\n"); |
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break; |
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} |
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} |
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return ret_val; |
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} |
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/** |
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* igc_write_nvm_srwr_i225 - Write to Shadow RAM using EEWR |
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* @hw: pointer to the HW structure |
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* @offset: offset within the Shadow RAM to be written to |
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* @words: number of words to write |
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* @data: 16 bit word(s) to be written to the Shadow RAM |
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* |
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* Writes data to Shadow RAM at offset using EEWR register. |
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* |
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* If igc_update_nvm_checksum is not called after this function , the |
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* data will not be committed to FLASH and also Shadow RAM will most likely |
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* contain an invalid checksum. |
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* |
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* If error code is returned, data and Shadow RAM may be inconsistent - buffer |
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* partially written. |
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*/ |
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static s32 igc_write_nvm_srwr_i225(struct igc_hw *hw, u16 offset, u16 words, |
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u16 *data) |
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{ |
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s32 status = 0; |
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u16 i, count; |
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/* We cannot hold synchronization semaphores for too long, |
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* because of forceful takeover procedure. However it is more efficient |
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* to write in bursts than synchronizing access for each word. |
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*/ |
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for (i = 0; i < words; i += IGC_EERD_EEWR_MAX_COUNT) { |
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count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ? |
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IGC_EERD_EEWR_MAX_COUNT : (words - i); |
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status = hw->nvm.ops.acquire(hw); |
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if (status) |
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break; |
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status = igc_write_nvm_srwr(hw, offset, count, data + i); |
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hw->nvm.ops.release(hw); |
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if (status) |
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break; |
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} |
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return status; |
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} |
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/** |
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* igc_validate_nvm_checksum_i225 - Validate EEPROM checksum |
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* @hw: pointer to the HW structure |
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* |
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* Calculates the EEPROM checksum by reading/adding each word of the EEPROM |
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* and then verifies that the sum of the EEPROM is equal to 0xBABA. |
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*/ |
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static s32 igc_validate_nvm_checksum_i225(struct igc_hw *hw) |
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{ |
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s32 (*read_op_ptr)(struct igc_hw *hw, u16 offset, u16 count, |
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u16 *data); |
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s32 status = 0; |
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status = hw->nvm.ops.acquire(hw); |
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if (status) |
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goto out; |
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/* Replace the read function with semaphore grabbing with |
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* the one that skips this for a while. |
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* We have semaphore taken already here. |
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*/ |
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read_op_ptr = hw->nvm.ops.read; |
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hw->nvm.ops.read = igc_read_nvm_eerd; |
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status = igc_validate_nvm_checksum(hw); |
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/* Revert original read operation. */ |
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hw->nvm.ops.read = read_op_ptr; |
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hw->nvm.ops.release(hw); |
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out: |
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return status; |
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} |
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/** |
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* igc_pool_flash_update_done_i225 - Pool FLUDONE status |
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* @hw: pointer to the HW structure |
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*/ |
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static s32 igc_pool_flash_update_done_i225(struct igc_hw *hw) |
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{ |
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s32 ret_val = -IGC_ERR_NVM; |
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u32 i, reg; |
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for (i = 0; i < IGC_FLUDONE_ATTEMPTS; i++) { |
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reg = rd32(IGC_EECD); |
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if (reg & IGC_EECD_FLUDONE_I225) { |
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ret_val = 0; |
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break; |
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} |
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udelay(5); |
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} |
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return ret_val; |
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} |
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/** |
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* igc_update_flash_i225 - Commit EEPROM to the flash |
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* @hw: pointer to the HW structure |
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*/ |
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static s32 igc_update_flash_i225(struct igc_hw *hw) |
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{ |
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s32 ret_val = 0; |
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u32 flup; |
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ret_val = igc_pool_flash_update_done_i225(hw); |
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if (ret_val == -IGC_ERR_NVM) { |
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hw_dbg("Flash update time out\n"); |
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goto out; |
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} |
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flup = rd32(IGC_EECD) | IGC_EECD_FLUPD_I225; |
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wr32(IGC_EECD, flup); |
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ret_val = igc_pool_flash_update_done_i225(hw); |
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if (ret_val) |
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hw_dbg("Flash update time out\n"); |
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else |
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hw_dbg("Flash update complete\n"); |
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out: |
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return ret_val; |
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} |
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/** |
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* igc_update_nvm_checksum_i225 - Update EEPROM checksum |
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* @hw: pointer to the HW structure |
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* |
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* Updates the EEPROM checksum by reading/adding each word of the EEPROM |
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* up to the checksum. Then calculates the EEPROM checksum and writes the |
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* value to the EEPROM. Next commit EEPROM data onto the Flash. |
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*/ |
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static s32 igc_update_nvm_checksum_i225(struct igc_hw *hw) |
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{ |
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u16 checksum = 0; |
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s32 ret_val = 0; |
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u16 i, nvm_data; |
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/* Read the first word from the EEPROM. If this times out or fails, do |
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* not continue or we could be in for a very long wait while every |
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* EEPROM read fails |
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*/ |
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ret_val = igc_read_nvm_eerd(hw, 0, 1, &nvm_data); |
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if (ret_val) { |
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hw_dbg("EEPROM read failed\n"); |
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goto out; |
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} |
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ret_val = hw->nvm.ops.acquire(hw); |
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if (ret_val) |
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goto out; |
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/* Do not use hw->nvm.ops.write, hw->nvm.ops.read |
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* because we do not want to take the synchronization |
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* semaphores twice here. |
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*/ |
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for (i = 0; i < NVM_CHECKSUM_REG; i++) { |
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ret_val = igc_read_nvm_eerd(hw, i, 1, &nvm_data); |
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if (ret_val) { |
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hw->nvm.ops.release(hw); |
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hw_dbg("NVM Read Error while updating checksum.\n"); |
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goto out; |
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} |
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checksum += nvm_data; |
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} |
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checksum = (u16)NVM_SUM - checksum; |
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ret_val = igc_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1, |
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&checksum); |
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if (ret_val) { |
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hw->nvm.ops.release(hw); |
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hw_dbg("NVM Write Error while updating checksum.\n"); |
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goto out; |
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} |
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hw->nvm.ops.release(hw); |
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ret_val = igc_update_flash_i225(hw); |
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out: |
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return ret_val; |
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} |
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/** |
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* igc_get_flash_presence_i225 - Check if flash device is detected |
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* @hw: pointer to the HW structure |
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*/ |
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bool igc_get_flash_presence_i225(struct igc_hw *hw) |
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{ |
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bool ret_val = false; |
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u32 eec = 0; |
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eec = rd32(IGC_EECD); |
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if (eec & IGC_EECD_FLASH_DETECTED_I225) |
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ret_val = true; |
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return ret_val; |
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} |
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/** |
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* igc_init_nvm_params_i225 - Init NVM func ptrs. |
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* @hw: pointer to the HW structure |
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*/ |
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s32 igc_init_nvm_params_i225(struct igc_hw *hw) |
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{ |
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struct igc_nvm_info *nvm = &hw->nvm; |
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nvm->ops.acquire = igc_acquire_nvm_i225; |
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nvm->ops.release = igc_release_nvm_i225; |
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/* NVM Function Pointers */ |
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if (igc_get_flash_presence_i225(hw)) { |
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hw->nvm.type = igc_nvm_flash_hw; |
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nvm->ops.read = igc_read_nvm_srrd_i225; |
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nvm->ops.write = igc_write_nvm_srwr_i225; |
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nvm->ops.validate = igc_validate_nvm_checksum_i225; |
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nvm->ops.update = igc_update_nvm_checksum_i225; |
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} else { |
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hw->nvm.type = igc_nvm_invm; |
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nvm->ops.read = igc_read_nvm_eerd; |
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nvm->ops.write = NULL; |
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nvm->ops.validate = NULL; |
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nvm->ops.update = NULL; |
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} |
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return 0; |
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} |
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/** |
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* igc_set_eee_i225 - Enable/disable EEE support |
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* @hw: pointer to the HW structure |
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* @adv2p5G: boolean flag enabling 2.5G EEE advertisement |
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* @adv1G: boolean flag enabling 1G EEE advertisement |
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* @adv100M: boolean flag enabling 100M EEE advertisement |
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* |
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* Enable/disable EEE based on setting in dev_spec structure. |
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**/ |
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s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G, |
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bool adv100M) |
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{ |
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u32 ipcnfg, eeer; |
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ipcnfg = rd32(IGC_IPCNFG); |
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eeer = rd32(IGC_EEER); |
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/* enable or disable per user setting */ |
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if (hw->dev_spec._base.eee_enable) { |
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u32 eee_su = rd32(IGC_EEE_SU); |
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if (adv100M) |
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ipcnfg |= IGC_IPCNFG_EEE_100M_AN; |
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else |
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ipcnfg &= ~IGC_IPCNFG_EEE_100M_AN; |
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if (adv1G) |
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ipcnfg |= IGC_IPCNFG_EEE_1G_AN; |
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else |
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ipcnfg &= ~IGC_IPCNFG_EEE_1G_AN; |
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if (adv2p5G) |
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ipcnfg |= IGC_IPCNFG_EEE_2_5G_AN; |
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else |
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ipcnfg &= ~IGC_IPCNFG_EEE_2_5G_AN; |
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eeer |= (IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN | |
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IGC_EEER_LPI_FC); |
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/* This bit should not be set in normal operation. */ |
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if (eee_su & IGC_EEE_SU_LPI_CLK_STP) |
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hw_dbg("LPI Clock Stop Bit should not be set!\n"); |
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} else { |
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ipcnfg &= ~(IGC_IPCNFG_EEE_2_5G_AN | IGC_IPCNFG_EEE_1G_AN | |
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IGC_IPCNFG_EEE_100M_AN); |
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eeer &= ~(IGC_EEER_TX_LPI_EN | IGC_EEER_RX_LPI_EN | |
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IGC_EEER_LPI_FC); |
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} |
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wr32(IGC_IPCNFG, ipcnfg); |
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wr32(IGC_EEER, eeer); |
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rd32(IGC_IPCNFG); |
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rd32(IGC_EEER); |
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return IGC_SUCCESS; |
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} |
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/* igc_set_ltr_i225 - Set Latency Tolerance Reporting thresholds |
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* @hw: pointer to the HW structure |
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* @link: bool indicating link status |
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* |
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* Set the LTR thresholds based on the link speed (Mbps), EEE, and DMAC |
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* settings, otherwise specify that there is no LTR requirement. |
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*/ |
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s32 igc_set_ltr_i225(struct igc_hw *hw, bool link) |
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{ |
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u32 tw_system, ltrc, ltrv, ltr_min, ltr_max, scale_min, scale_max; |
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u16 speed, duplex; |
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s32 size; |
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|
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/* If we do not have link, LTR thresholds are zero. */ |
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if (link) { |
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hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex); |
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|
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/* Check if using copper interface with EEE enabled or if the |
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* link speed is 10 Mbps. |
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*/ |
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if (hw->dev_spec._base.eee_enable && |
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speed != SPEED_10) { |
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/* EEE enabled, so send LTRMAX threshold. */ |
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ltrc = rd32(IGC_LTRC) | |
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IGC_LTRC_EEEMS_EN; |
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wr32(IGC_LTRC, ltrc); |
|
|
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/* Calculate tw_system (nsec). */ |
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if (speed == SPEED_100) { |
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tw_system = ((rd32(IGC_EEE_SU) & |
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IGC_TW_SYSTEM_100_MASK) >> |
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IGC_TW_SYSTEM_100_SHIFT) * 500; |
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} else { |
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tw_system = (rd32(IGC_EEE_SU) & |
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IGC_TW_SYSTEM_1000_MASK) * 500; |
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} |
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} else { |
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tw_system = 0; |
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} |
|
|
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/* Get the Rx packet buffer size. */ |
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size = rd32(IGC_RXPBS) & |
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IGC_RXPBS_SIZE_I225_MASK; |
|
|
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/* Calculations vary based on DMAC settings. */ |
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if (rd32(IGC_DMACR) & IGC_DMACR_DMAC_EN) { |
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size -= (rd32(IGC_DMACR) & |
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IGC_DMACR_DMACTHR_MASK) >> |
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IGC_DMACR_DMACTHR_SHIFT; |
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/* Convert size to bits. */ |
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size *= 1024 * 8; |
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} else { |
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/* Convert size to bytes, subtract the MTU, and then |
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* convert the size to bits. |
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*/ |
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size *= 1024; |
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size *= 8; |
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} |
|
|
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if (size < 0) { |
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hw_dbg("Invalid effective Rx buffer size %d\n", |
|
size); |
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return -IGC_ERR_CONFIG; |
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} |
|
|
|
/* Calculate the thresholds. Since speed is in Mbps, simplify |
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* the calculation by multiplying size/speed by 1000 for result |
|
* to be in nsec before dividing by the scale in nsec. Set the |
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* scale such that the LTR threshold fits in the register. |
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*/ |
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ltr_min = (1000 * size) / speed; |
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ltr_max = ltr_min + tw_system; |
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scale_min = (ltr_min / 1024) < 1024 ? IGC_LTRMINV_SCALE_1024 : |
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IGC_LTRMINV_SCALE_32768; |
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scale_max = (ltr_max / 1024) < 1024 ? IGC_LTRMAXV_SCALE_1024 : |
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IGC_LTRMAXV_SCALE_32768; |
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ltr_min /= scale_min == IGC_LTRMINV_SCALE_1024 ? 1024 : 32768; |
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ltr_min -= 1; |
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ltr_max /= scale_max == IGC_LTRMAXV_SCALE_1024 ? 1024 : 32768; |
|
ltr_max -= 1; |
|
|
|
/* Only write the LTR thresholds if they differ from before. */ |
|
ltrv = rd32(IGC_LTRMINV); |
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if (ltr_min != (ltrv & IGC_LTRMINV_LTRV_MASK)) { |
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ltrv = IGC_LTRMINV_LSNP_REQ | ltr_min | |
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(scale_min << IGC_LTRMINV_SCALE_SHIFT); |
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wr32(IGC_LTRMINV, ltrv); |
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} |
|
|
|
ltrv = rd32(IGC_LTRMAXV); |
|
if (ltr_max != (ltrv & IGC_LTRMAXV_LTRV_MASK)) { |
|
ltrv = IGC_LTRMAXV_LSNP_REQ | ltr_max | |
|
(scale_min << IGC_LTRMAXV_SCALE_SHIFT); |
|
wr32(IGC_LTRMAXV, ltrv); |
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} |
|
} |
|
|
|
return IGC_SUCCESS; |
|
}
|
|
|