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298 lines
5.8 KiB
298 lines
5.8 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* Copyright (c) 2018 Intel Corporation */ |
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#ifndef _IGC_HW_H_ |
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#define _IGC_HW_H_ |
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#include <linux/types.h> |
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#include <linux/if_ether.h> |
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#include <linux/netdevice.h> |
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#include "igc_regs.h" |
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#include "igc_defines.h" |
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#include "igc_mac.h" |
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#include "igc_phy.h" |
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#include "igc_nvm.h" |
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#include "igc_i225.h" |
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#include "igc_base.h" |
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#define IGC_DEV_ID_I225_LM 0x15F2 |
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#define IGC_DEV_ID_I225_V 0x15F3 |
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#define IGC_DEV_ID_I225_I 0x15F8 |
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#define IGC_DEV_ID_I220_V 0x15F7 |
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#define IGC_DEV_ID_I225_K 0x3100 |
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#define IGC_DEV_ID_I225_K2 0x3101 |
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#define IGC_DEV_ID_I225_LMVP 0x5502 |
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#define IGC_DEV_ID_I226_K 0x5504 |
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#define IGC_DEV_ID_I225_IT 0x0D9F |
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#define IGC_DEV_ID_I226_LM 0x125B |
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#define IGC_DEV_ID_I226_V 0x125C |
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#define IGC_DEV_ID_I226_IT 0x125D |
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#define IGC_DEV_ID_I221_V 0x125E |
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#define IGC_DEV_ID_I226_BLANK_NVM 0x125F |
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#define IGC_DEV_ID_I225_BLANK_NVM 0x15FD |
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/* Function pointers for the MAC. */ |
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struct igc_mac_operations { |
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s32 (*check_for_link)(struct igc_hw *hw); |
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s32 (*reset_hw)(struct igc_hw *hw); |
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s32 (*init_hw)(struct igc_hw *hw); |
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s32 (*setup_physical_interface)(struct igc_hw *hw); |
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void (*rar_set)(struct igc_hw *hw, u8 *address, u32 index); |
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s32 (*read_mac_addr)(struct igc_hw *hw); |
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s32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed, |
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u16 *duplex); |
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s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask); |
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void (*release_swfw_sync)(struct igc_hw *hw, u16 mask); |
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}; |
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enum igc_mac_type { |
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igc_undefined = 0, |
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igc_i225, |
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igc_num_macs /* List is 1-based, so subtract 1 for true count. */ |
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}; |
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enum igc_phy_type { |
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igc_phy_unknown = 0, |
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igc_phy_none, |
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igc_phy_i225, |
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}; |
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enum igc_media_type { |
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igc_media_type_unknown = 0, |
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igc_media_type_copper = 1, |
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igc_num_media_types |
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}; |
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enum igc_nvm_type { |
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igc_nvm_unknown = 0, |
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igc_nvm_eeprom_spi, |
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igc_nvm_flash_hw, |
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igc_nvm_invm, |
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}; |
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struct igc_info { |
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s32 (*get_invariants)(struct igc_hw *hw); |
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struct igc_mac_operations *mac_ops; |
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const struct igc_phy_operations *phy_ops; |
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struct igc_nvm_operations *nvm_ops; |
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}; |
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extern const struct igc_info igc_base_info; |
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struct igc_mac_info { |
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struct igc_mac_operations ops; |
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u8 addr[ETH_ALEN]; |
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u8 perm_addr[ETH_ALEN]; |
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enum igc_mac_type type; |
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u32 mc_filter_type; |
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u16 mta_reg_count; |
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u16 uta_reg_count; |
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u32 mta_shadow[MAX_MTA_REG]; |
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u16 rar_entry_count; |
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u8 forced_speed_duplex; |
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bool asf_firmware_present; |
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bool arc_subsystem_valid; |
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bool autoneg; |
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bool autoneg_failed; |
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bool get_link_status; |
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}; |
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struct igc_nvm_operations { |
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s32 (*acquire)(struct igc_hw *hw); |
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s32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); |
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void (*release)(struct igc_hw *hw); |
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s32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); |
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s32 (*update)(struct igc_hw *hw); |
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s32 (*validate)(struct igc_hw *hw); |
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}; |
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struct igc_phy_operations { |
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s32 (*acquire)(struct igc_hw *hw); |
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s32 (*check_reset_block)(struct igc_hw *hw); |
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s32 (*force_speed_duplex)(struct igc_hw *hw); |
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s32 (*get_phy_info)(struct igc_hw *hw); |
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s32 (*read_reg)(struct igc_hw *hw, u32 address, u16 *data); |
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void (*release)(struct igc_hw *hw); |
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s32 (*reset)(struct igc_hw *hw); |
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s32 (*write_reg)(struct igc_hw *hw, u32 address, u16 data); |
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}; |
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struct igc_nvm_info { |
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struct igc_nvm_operations ops; |
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enum igc_nvm_type type; |
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u16 word_size; |
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u16 delay_usec; |
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u16 address_bits; |
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u16 opcode_bits; |
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u16 page_size; |
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}; |
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struct igc_phy_info { |
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struct igc_phy_operations ops; |
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enum igc_phy_type type; |
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u32 addr; |
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u32 id; |
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u32 reset_delay_us; /* in usec */ |
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u32 revision; |
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enum igc_media_type media_type; |
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u16 autoneg_advertised; |
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u16 autoneg_mask; |
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u8 mdix; |
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bool is_mdix; |
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bool speed_downgraded; |
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bool autoneg_wait_to_complete; |
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}; |
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struct igc_bus_info { |
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u16 func; |
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u16 pci_cmd_word; |
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}; |
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enum igc_fc_mode { |
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igc_fc_none = 0, |
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igc_fc_rx_pause, |
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igc_fc_tx_pause, |
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igc_fc_full, |
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igc_fc_default = 0xFF |
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}; |
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struct igc_fc_info { |
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u32 high_water; /* Flow control high-water mark */ |
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u32 low_water; /* Flow control low-water mark */ |
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u16 pause_time; /* Flow control pause timer */ |
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bool send_xon; /* Flow control send XON */ |
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bool strict_ieee; /* Strict IEEE mode */ |
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enum igc_fc_mode current_mode; /* Type of flow control */ |
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enum igc_fc_mode requested_mode; |
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}; |
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struct igc_dev_spec_base { |
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bool clear_semaphore_once; |
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bool eee_enable; |
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}; |
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struct igc_hw { |
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void *back; |
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u8 __iomem *hw_addr; |
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unsigned long io_base; |
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struct igc_mac_info mac; |
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struct igc_fc_info fc; |
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struct igc_nvm_info nvm; |
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struct igc_phy_info phy; |
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struct igc_bus_info bus; |
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union { |
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struct igc_dev_spec_base _base; |
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} dev_spec; |
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u16 device_id; |
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u16 subsystem_vendor_id; |
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u16 subsystem_device_id; |
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u16 vendor_id; |
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u8 revision_id; |
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}; |
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/* Statistics counters collected by the MAC */ |
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struct igc_hw_stats { |
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u64 crcerrs; |
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u64 algnerrc; |
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u64 symerrs; |
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u64 rxerrc; |
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u64 mpc; |
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u64 scc; |
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u64 ecol; |
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u64 mcc; |
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u64 latecol; |
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u64 colc; |
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u64 dc; |
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u64 tncrs; |
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u64 sec; |
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u64 cexterr; |
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u64 rlec; |
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u64 xonrxc; |
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u64 xontxc; |
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u64 xoffrxc; |
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u64 xofftxc; |
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u64 fcruc; |
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u64 prc64; |
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u64 prc127; |
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u64 prc255; |
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u64 prc511; |
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u64 prc1023; |
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u64 prc1522; |
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u64 tlpic; |
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u64 rlpic; |
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u64 gprc; |
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u64 bprc; |
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u64 mprc; |
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u64 gptc; |
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u64 gorc; |
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u64 gotc; |
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u64 rnbc; |
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u64 ruc; |
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u64 rfc; |
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u64 roc; |
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u64 rjc; |
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u64 mgprc; |
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u64 mgpdc; |
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u64 mgptc; |
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u64 tor; |
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u64 tot; |
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u64 tpr; |
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u64 tpt; |
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u64 ptc64; |
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u64 ptc127; |
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u64 ptc255; |
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u64 ptc511; |
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u64 ptc1023; |
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u64 ptc1522; |
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u64 mptc; |
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u64 bptc; |
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u64 tsctc; |
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u64 tsctfc; |
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u64 iac; |
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u64 htdpmc; |
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u64 rpthc; |
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u64 hgptc; |
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u64 hgorc; |
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u64 hgotc; |
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u64 lenerrs; |
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u64 scvpc; |
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u64 hrmpc; |
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u64 doosync; |
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u64 o2bgptc; |
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u64 o2bspc; |
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u64 b2ospc; |
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u64 b2ogprc; |
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}; |
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struct net_device *igc_get_hw_dev(struct igc_hw *hw); |
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#define hw_dbg(format, arg...) \ |
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netdev_dbg(igc_get_hw_dev(hw), format, ##arg) |
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s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); |
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s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); |
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void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); |
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void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); |
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#endif /* _IGC_HW_H_ */
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