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90 lines
2.6 KiB
90 lines
2.6 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* Copyright (c) 2018 Intel Corporation */ |
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#ifndef _IGC_BASE_H_ |
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#define _IGC_BASE_H_ |
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/* forward declaration */ |
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void igc_rx_fifo_flush_base(struct igc_hw *hw); |
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void igc_power_down_phy_copper_base(struct igc_hw *hw); |
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/* Transmit Descriptor - Advanced */ |
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union igc_adv_tx_desc { |
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struct { |
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__le64 buffer_addr; /* Address of descriptor's data buf */ |
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__le32 cmd_type_len; |
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__le32 olinfo_status; |
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} read; |
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struct { |
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__le64 rsvd; /* Reserved */ |
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__le32 nxtseq_seed; |
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__le32 status; |
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} wb; |
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}; |
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/* Context descriptors */ |
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struct igc_adv_tx_context_desc { |
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__le32 vlan_macip_lens; |
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__le32 launch_time; |
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__le32 type_tucmd_mlhl; |
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__le32 mss_l4len_idx; |
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}; |
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/* Adv Transmit Descriptor Config Masks */ |
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#define IGC_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */ |
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#define IGC_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ |
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#define IGC_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ |
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#define IGC_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ |
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#define IGC_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ |
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#define IGC_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ |
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#define IGC_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ |
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#define IGC_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ |
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#define IGC_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ |
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#define IGC_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ |
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#define IGC_RAR_ENTRIES 16 |
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/* Receive Descriptor - Advanced */ |
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union igc_adv_rx_desc { |
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struct { |
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__le64 pkt_addr; /* Packet buffer address */ |
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__le64 hdr_addr; /* Header buffer address */ |
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} read; |
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struct { |
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struct { |
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union { |
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__le32 data; |
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struct { |
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__le16 pkt_info; /*RSS type, Pkt type*/ |
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/* Split Header, header buffer len */ |
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__le16 hdr_info; |
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} hs_rss; |
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} lo_dword; |
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union { |
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__le32 rss; /* RSS Hash */ |
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struct { |
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__le16 ip_id; /* IP id */ |
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__le16 csum; /* Packet Checksum */ |
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} csum_ip; |
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} hi_dword; |
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} lower; |
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struct { |
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__le32 status_error; /* ext status/error */ |
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__le16 length; /* Packet length */ |
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__le16 vlan; /* VLAN tag */ |
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} upper; |
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} wb; /* writeback */ |
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}; |
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/* Additional Transmit Descriptor Control definitions */ |
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#define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ |
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/* Additional Receive Descriptor Control definitions */ |
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#define IGC_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */ |
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/* SRRCTL bit definitions */ |
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#define IGC_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ |
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#define IGC_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ |
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#define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 |
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#endif /* _IGC_BASE_H */
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