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593 lines
16 KiB
593 lines
16 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* Copyright (c) 2018 Intel Corporation */ |
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#ifndef _IGC_H_ |
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#define _IGC_H_ |
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#include <linux/kobject.h> |
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#include <linux/pci.h> |
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#include <linux/netdevice.h> |
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#include <linux/vmalloc.h> |
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#include <linux/ethtool.h> |
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#include <linux/sctp.h> |
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#include <linux/ptp_clock_kernel.h> |
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#include <linux/timecounter.h> |
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#include <linux/net_tstamp.h> |
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#include "igc_hw.h" |
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void igc_ethtool_set_ops(struct net_device *); |
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/* Transmit and receive queues */ |
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#define IGC_MAX_RX_QUEUES 4 |
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#define IGC_MAX_TX_QUEUES 4 |
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#define MAX_Q_VECTORS 8 |
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#define MAX_STD_JUMBO_FRAME_SIZE 9216 |
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#define MAX_ETYPE_FILTER 8 |
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#define IGC_RETA_SIZE 128 |
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/* SDP support */ |
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#define IGC_N_EXTTS 2 |
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#define IGC_N_PEROUT 2 |
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#define IGC_N_SDP 4 |
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enum igc_mac_filter_type { |
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IGC_MAC_FILTER_TYPE_DST = 0, |
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IGC_MAC_FILTER_TYPE_SRC |
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}; |
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struct igc_tx_queue_stats { |
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u64 packets; |
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u64 bytes; |
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u64 restart_queue; |
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u64 restart_queue2; |
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}; |
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struct igc_rx_queue_stats { |
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u64 packets; |
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u64 bytes; |
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u64 drops; |
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u64 csum_err; |
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u64 alloc_failed; |
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}; |
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struct igc_rx_packet_stats { |
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u64 ipv4_packets; /* IPv4 headers processed */ |
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u64 ipv4e_packets; /* IPv4E headers with extensions processed */ |
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u64 ipv6_packets; /* IPv6 headers processed */ |
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u64 ipv6e_packets; /* IPv6E headers with extensions processed */ |
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u64 tcp_packets; /* TCP headers processed */ |
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u64 udp_packets; /* UDP headers processed */ |
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u64 sctp_packets; /* SCTP headers processed */ |
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u64 nfs_packets; /* NFS headers processe */ |
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u64 other_packets; |
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}; |
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struct igc_ring_container { |
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struct igc_ring *ring; /* pointer to linked list of rings */ |
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unsigned int total_bytes; /* total bytes processed this int */ |
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unsigned int total_packets; /* total packets processed this int */ |
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u16 work_limit; /* total work allowed per interrupt */ |
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u8 count; /* total number of rings in vector */ |
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u8 itr; /* current ITR setting for ring */ |
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}; |
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struct igc_ring { |
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struct igc_q_vector *q_vector; /* backlink to q_vector */ |
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struct net_device *netdev; /* back pointer to net_device */ |
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struct device *dev; /* device for dma mapping */ |
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union { /* array of buffer info structs */ |
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struct igc_tx_buffer *tx_buffer_info; |
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struct igc_rx_buffer *rx_buffer_info; |
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}; |
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void *desc; /* descriptor ring memory */ |
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unsigned long flags; /* ring specific flags */ |
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void __iomem *tail; /* pointer to ring tail register */ |
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dma_addr_t dma; /* phys address of the ring */ |
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unsigned int size; /* length of desc. ring in bytes */ |
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u16 count; /* number of desc. in the ring */ |
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u8 queue_index; /* logical index of the ring*/ |
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u8 reg_idx; /* physical index of the ring */ |
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bool launchtime_enable; /* true if LaunchTime is enabled */ |
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u32 start_time; |
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u32 end_time; |
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/* everything past this point are written often */ |
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u16 next_to_clean; |
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u16 next_to_use; |
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u16 next_to_alloc; |
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union { |
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/* TX */ |
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struct { |
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struct igc_tx_queue_stats tx_stats; |
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struct u64_stats_sync tx_syncp; |
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struct u64_stats_sync tx_syncp2; |
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}; |
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/* RX */ |
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struct { |
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struct igc_rx_queue_stats rx_stats; |
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struct igc_rx_packet_stats pkt_stats; |
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struct u64_stats_sync rx_syncp; |
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struct sk_buff *skb; |
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}; |
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}; |
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struct xdp_rxq_info xdp_rxq; |
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} ____cacheline_internodealigned_in_smp; |
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/* Board specific private data structure */ |
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struct igc_adapter { |
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struct net_device *netdev; |
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struct ethtool_eee eee; |
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u16 eee_advert; |
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unsigned long state; |
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unsigned int flags; |
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unsigned int num_q_vectors; |
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struct msix_entry *msix_entries; |
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/* TX */ |
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u16 tx_work_limit; |
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u32 tx_timeout_count; |
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int num_tx_queues; |
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struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; |
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/* RX */ |
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int num_rx_queues; |
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struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; |
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struct timer_list watchdog_timer; |
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struct timer_list dma_err_timer; |
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struct timer_list phy_info_timer; |
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u32 wol; |
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u32 en_mng_pt; |
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u16 link_speed; |
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u16 link_duplex; |
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u8 port_num; |
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u8 __iomem *io_addr; |
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/* Interrupt Throttle Rate */ |
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u32 rx_itr_setting; |
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u32 tx_itr_setting; |
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struct work_struct reset_task; |
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struct work_struct watchdog_task; |
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struct work_struct dma_err_task; |
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bool fc_autoneg; |
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u8 tx_timeout_factor; |
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int msg_enable; |
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u32 max_frame_size; |
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u32 min_frame_size; |
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ktime_t base_time; |
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ktime_t cycle_time; |
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/* OS defined structs */ |
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struct pci_dev *pdev; |
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/* lock for statistics */ |
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spinlock_t stats64_lock; |
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struct rtnl_link_stats64 stats64; |
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/* structs defined in igc_hw.h */ |
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struct igc_hw hw; |
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struct igc_hw_stats stats; |
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struct igc_q_vector *q_vector[MAX_Q_VECTORS]; |
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u32 eims_enable_mask; |
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u32 eims_other; |
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u16 tx_ring_count; |
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u16 rx_ring_count; |
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u32 tx_hwtstamp_timeouts; |
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u32 tx_hwtstamp_skipped; |
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u32 rx_hwtstamp_cleared; |
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u32 rss_queues; |
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u32 rss_indir_tbl_init; |
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/* Any access to elements in nfc_rule_list is protected by the |
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* nfc_rule_lock. |
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*/ |
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struct mutex nfc_rule_lock; |
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struct list_head nfc_rule_list; |
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unsigned int nfc_rule_count; |
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u8 rss_indir_tbl[IGC_RETA_SIZE]; |
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unsigned long link_check_timeout; |
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struct igc_info ei; |
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u32 test_icr; |
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struct ptp_clock *ptp_clock; |
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struct ptp_clock_info ptp_caps; |
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struct work_struct ptp_tx_work; |
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struct sk_buff *ptp_tx_skb; |
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struct hwtstamp_config tstamp_config; |
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unsigned long ptp_tx_start; |
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unsigned int ptp_flags; |
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/* System time value lock */ |
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spinlock_t tmreg_lock; |
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struct cyclecounter cc; |
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struct timecounter tc; |
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struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */ |
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ktime_t ptp_reset_start; /* Reset time in clock mono */ |
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char fw_version[32]; |
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struct bpf_prog *xdp_prog; |
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bool pps_sys_wrap_on; |
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struct ptp_pin_desc sdp_config[IGC_N_SDP]; |
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struct { |
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struct timespec64 start; |
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struct timespec64 period; |
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} perout[IGC_N_PEROUT]; |
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}; |
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void igc_up(struct igc_adapter *adapter); |
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void igc_down(struct igc_adapter *adapter); |
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int igc_open(struct net_device *netdev); |
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int igc_close(struct net_device *netdev); |
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int igc_setup_tx_resources(struct igc_ring *ring); |
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int igc_setup_rx_resources(struct igc_ring *ring); |
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void igc_free_tx_resources(struct igc_ring *ring); |
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void igc_free_rx_resources(struct igc_ring *ring); |
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unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); |
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void igc_set_flag_queue_pairs(struct igc_adapter *adapter, |
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const u32 max_rss_queues); |
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int igc_reinit_queues(struct igc_adapter *adapter); |
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void igc_write_rss_indir_tbl(struct igc_adapter *adapter); |
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bool igc_has_link(struct igc_adapter *adapter); |
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void igc_reset(struct igc_adapter *adapter); |
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int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx); |
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void igc_update_stats(struct igc_adapter *adapter); |
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/* igc_dump declarations */ |
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void igc_rings_dump(struct igc_adapter *adapter); |
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void igc_regs_dump(struct igc_adapter *adapter); |
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extern char igc_driver_name[]; |
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#define IGC_REGS_LEN 740 |
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/* flags controlling PTP/1588 function */ |
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#define IGC_PTP_ENABLED BIT(0) |
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/* Flags definitions */ |
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#define IGC_FLAG_HAS_MSI BIT(0) |
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#define IGC_FLAG_QUEUE_PAIRS BIT(3) |
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#define IGC_FLAG_DMAC BIT(4) |
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#define IGC_FLAG_PTP BIT(8) |
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#define IGC_FLAG_WOL_SUPPORTED BIT(8) |
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#define IGC_FLAG_NEED_LINK_UPDATE BIT(9) |
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#define IGC_FLAG_MEDIA_RESET BIT(10) |
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#define IGC_FLAG_MAS_ENABLE BIT(12) |
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#define IGC_FLAG_HAS_MSIX BIT(13) |
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#define IGC_FLAG_EEE BIT(14) |
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#define IGC_FLAG_VLAN_PROMISC BIT(15) |
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#define IGC_FLAG_RX_LEGACY BIT(16) |
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#define IGC_FLAG_TSN_QBV_ENABLED BIT(17) |
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#define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) |
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#define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) |
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#define IGC_MRQC_ENABLE_RSS_MQ 0x00000002 |
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#define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 |
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#define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 |
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/* Interrupt defines */ |
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#define IGC_START_ITR 648 /* ~6000 ints/sec */ |
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#define IGC_4K_ITR 980 |
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#define IGC_20K_ITR 196 |
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#define IGC_70K_ITR 56 |
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#define IGC_DEFAULT_ITR 3 /* dynamic */ |
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#define IGC_MAX_ITR_USECS 10000 |
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#define IGC_MIN_ITR_USECS 10 |
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#define NON_Q_VECTORS 1 |
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#define MAX_MSIX_ENTRIES 10 |
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/* TX/RX descriptor defines */ |
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#define IGC_DEFAULT_TXD 256 |
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#define IGC_DEFAULT_TX_WORK 128 |
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#define IGC_MIN_TXD 80 |
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#define IGC_MAX_TXD 4096 |
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#define IGC_DEFAULT_RXD 256 |
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#define IGC_MIN_RXD 80 |
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#define IGC_MAX_RXD 4096 |
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/* Supported Rx Buffer Sizes */ |
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#define IGC_RXBUFFER_256 256 |
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#define IGC_RXBUFFER_2048 2048 |
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#define IGC_RXBUFFER_3072 3072 |
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#define AUTO_ALL_MODES 0 |
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#define IGC_RX_HDR_LEN IGC_RXBUFFER_256 |
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/* Transmit and receive latency (for PTP timestamps) */ |
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#define IGC_I225_TX_LATENCY_10 240 |
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#define IGC_I225_TX_LATENCY_100 58 |
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#define IGC_I225_TX_LATENCY_1000 80 |
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#define IGC_I225_TX_LATENCY_2500 1325 |
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#define IGC_I225_RX_LATENCY_10 6450 |
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#define IGC_I225_RX_LATENCY_100 185 |
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#define IGC_I225_RX_LATENCY_1000 300 |
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#define IGC_I225_RX_LATENCY_2500 1485 |
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/* RX and TX descriptor control thresholds. |
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* PTHRESH - MAC will consider prefetch if it has fewer than this number of |
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* descriptors available in its onboard memory. |
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* Setting this to 0 disables RX descriptor prefetch. |
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* HTHRESH - MAC will only prefetch if there are at least this many descriptors |
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* available in host memory. |
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* If PTHRESH is 0, this should also be 0. |
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* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back |
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* descriptors until either it has this many to write back, or the |
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* ITR timer expires. |
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*/ |
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#define IGC_RX_PTHRESH 8 |
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#define IGC_RX_HTHRESH 8 |
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#define IGC_TX_PTHRESH 8 |
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#define IGC_TX_HTHRESH 1 |
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#define IGC_RX_WTHRESH 4 |
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#define IGC_TX_WTHRESH 16 |
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#define IGC_RX_DMA_ATTR \ |
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(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) |
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#define IGC_TS_HDR_LEN 16 |
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#define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) |
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#if (PAGE_SIZE < 8192) |
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#define IGC_MAX_FRAME_BUILD_SKB \ |
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(SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) |
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#else |
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#define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) |
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#endif |
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/* How many Rx Buffers do we bundle into one write to the hardware ? */ |
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#define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ |
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/* VLAN info */ |
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#define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 |
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/* igc_test_staterr - tests bits within Rx descriptor status and error fields */ |
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static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, |
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const u32 stat_err_bits) |
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{ |
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return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); |
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} |
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enum igc_state_t { |
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__IGC_TESTING, |
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__IGC_RESETTING, |
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__IGC_DOWN, |
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__IGC_PTP_TX_IN_PROGRESS, |
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}; |
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enum igc_tx_flags { |
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/* cmd_type flags */ |
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IGC_TX_FLAGS_VLAN = 0x01, |
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IGC_TX_FLAGS_TSO = 0x02, |
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IGC_TX_FLAGS_TSTAMP = 0x04, |
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/* olinfo flags */ |
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IGC_TX_FLAGS_IPV4 = 0x10, |
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IGC_TX_FLAGS_CSUM = 0x20, |
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IGC_TX_FLAGS_XDP = 0x100, |
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}; |
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enum igc_boards { |
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board_base, |
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}; |
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/* The largest size we can write to the descriptor is 65535. In order to |
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* maintain a power of two alignment we have to limit ourselves to 32K. |
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*/ |
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#define IGC_MAX_TXD_PWR 15 |
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#define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) |
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/* Tx Descriptors needed, worst case */ |
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#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) |
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#define DESC_NEEDED (MAX_SKB_FRAGS + 4) |
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/* wrapper around a pointer to a socket buffer, |
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* so a DMA handle can be stored along with the buffer |
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*/ |
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struct igc_tx_buffer { |
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union igc_adv_tx_desc *next_to_watch; |
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unsigned long time_stamp; |
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union { |
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struct sk_buff *skb; |
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struct xdp_frame *xdpf; |
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}; |
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unsigned int bytecount; |
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u16 gso_segs; |
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__be16 protocol; |
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DEFINE_DMA_UNMAP_ADDR(dma); |
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DEFINE_DMA_UNMAP_LEN(len); |
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u32 tx_flags; |
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}; |
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struct igc_rx_buffer { |
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dma_addr_t dma; |
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struct page *page; |
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#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) |
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__u32 page_offset; |
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#else |
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__u16 page_offset; |
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#endif |
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__u16 pagecnt_bias; |
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}; |
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struct igc_q_vector { |
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struct igc_adapter *adapter; /* backlink */ |
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void __iomem *itr_register; |
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u32 eims_value; /* EIMS mask value */ |
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u16 itr_val; |
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u8 set_itr; |
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struct igc_ring_container rx, tx; |
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struct napi_struct napi; |
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struct rcu_head rcu; /* to avoid race with update stats on free */ |
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char name[IFNAMSIZ + 9]; |
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struct net_device poll_dev; |
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/* for dynamic allocation of rings associated with this q_vector */ |
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struct igc_ring ring[] ____cacheline_internodealigned_in_smp; |
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}; |
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enum igc_filter_match_flags { |
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IGC_FILTER_FLAG_ETHER_TYPE = 0x1, |
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IGC_FILTER_FLAG_VLAN_TCI = 0x2, |
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IGC_FILTER_FLAG_SRC_MAC_ADDR = 0x4, |
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IGC_FILTER_FLAG_DST_MAC_ADDR = 0x8, |
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}; |
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struct igc_nfc_filter { |
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u8 match_flags; |
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u16 etype; |
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u16 vlan_tci; |
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u8 src_addr[ETH_ALEN]; |
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u8 dst_addr[ETH_ALEN]; |
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}; |
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struct igc_nfc_rule { |
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struct list_head list; |
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struct igc_nfc_filter filter; |
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u32 location; |
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u16 action; |
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}; |
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/* IGC supports a total of 32 NFC rules: 16 MAC address based,, 8 VLAN priority |
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* based, and 8 ethertype based. |
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*/ |
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#define IGC_MAX_RXNFC_RULES 32 |
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/* igc_desc_unused - calculate if we have unused descriptors */ |
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static inline u16 igc_desc_unused(const struct igc_ring *ring) |
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{ |
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u16 ntc = ring->next_to_clean; |
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u16 ntu = ring->next_to_use; |
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return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; |
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} |
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static inline s32 igc_get_phy_info(struct igc_hw *hw) |
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{ |
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if (hw->phy.ops.get_phy_info) |
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return hw->phy.ops.get_phy_info(hw); |
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return 0; |
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} |
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static inline s32 igc_reset_phy(struct igc_hw *hw) |
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{ |
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if (hw->phy.ops.reset) |
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return hw->phy.ops.reset(hw); |
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return 0; |
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} |
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static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) |
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{ |
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return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); |
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} |
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enum igc_ring_flags_t { |
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IGC_RING_FLAG_RX_3K_BUFFER, |
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IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, |
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IGC_RING_FLAG_RX_SCTP_CSUM, |
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IGC_RING_FLAG_RX_LB_VLAN_BSWAP, |
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IGC_RING_FLAG_TX_CTX_IDX, |
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IGC_RING_FLAG_TX_DETECT_HANG |
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}; |
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#define ring_uses_large_buffer(ring) \ |
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test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) |
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#define set_ring_uses_large_buffer(ring) \ |
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set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) |
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#define clear_ring_uses_large_buffer(ring) \ |
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clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) |
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#define ring_uses_build_skb(ring) \ |
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test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) |
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static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) |
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{ |
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#if (PAGE_SIZE < 8192) |
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if (ring_uses_large_buffer(ring)) |
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return IGC_RXBUFFER_3072; |
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if (ring_uses_build_skb(ring)) |
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return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; |
|
#endif |
|
return IGC_RXBUFFER_2048; |
|
} |
|
|
|
static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) |
|
{ |
|
#if (PAGE_SIZE < 8192) |
|
if (ring_uses_large_buffer(ring)) |
|
return 1; |
|
#endif |
|
return 0; |
|
} |
|
|
|
static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) |
|
{ |
|
if (hw->phy.ops.read_reg) |
|
return hw->phy.ops.read_reg(hw, offset, data); |
|
|
|
return 0; |
|
} |
|
|
|
void igc_reinit_locked(struct igc_adapter *); |
|
struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter, |
|
u32 location); |
|
int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); |
|
void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule); |
|
|
|
void igc_ptp_init(struct igc_adapter *adapter); |
|
void igc_ptp_reset(struct igc_adapter *adapter); |
|
void igc_ptp_suspend(struct igc_adapter *adapter); |
|
void igc_ptp_stop(struct igc_adapter *adapter); |
|
ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf); |
|
int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); |
|
int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); |
|
void igc_ptp_tx_hang(struct igc_adapter *adapter); |
|
void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts); |
|
|
|
#define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) |
|
|
|
#define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) |
|
|
|
#define IGC_RX_DESC(R, i) \ |
|
(&(((union igc_adv_rx_desc *)((R)->desc))[i])) |
|
#define IGC_TX_DESC(R, i) \ |
|
(&(((union igc_adv_tx_desc *)((R)->desc))[i])) |
|
#define IGC_TX_CTXTDESC(R, i) \ |
|
(&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) |
|
|
|
#endif /* _IGC_H_ */
|
|
|