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457 lines
10 KiB
457 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Sharp QM1D1C0042 8PSK tuner driver |
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* |
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* Copyright (C) 2014 Akihiro Tsukada <[email protected]> |
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*/ |
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|
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/* |
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* NOTICE: |
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* As the disclosed information on the chip is very limited, |
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* this driver lacks some features, including chip config like IF freq. |
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* It assumes that users of this driver (such as a PCI bridge of |
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* DTV receiver cards) know the relevant info and |
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* configure the chip via I2C if necessary. |
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* |
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* Currently, PT3 driver is the only one that uses this driver, |
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* and contains init/config code in its firmware. |
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* Thus some part of the code might be dependent on PT3 specific config. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/math64.h> |
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#include "qm1d1c0042.h" |
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#define QM1D1C0042_NUM_REGS 0x20 |
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#define QM1D1C0042_NUM_REG_ROWS 2 |
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static const u8 |
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reg_initval[QM1D1C0042_NUM_REG_ROWS][QM1D1C0042_NUM_REGS] = { { |
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0x48, 0x1c, 0xa0, 0x10, 0xbc, 0xc5, 0x20, 0x33, |
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0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, |
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0x00, 0xff, 0xf3, 0x00, 0x2a, 0x64, 0xa6, 0x86, |
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0x8c, 0xcf, 0xb8, 0xf1, 0xa8, 0xf2, 0x89, 0x00 |
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}, { |
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0x68, 0x1c, 0xc0, 0x10, 0xbc, 0xc1, 0x11, 0x33, |
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0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, |
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0x00, 0xff, 0xf3, 0x00, 0x3f, 0x25, 0x5c, 0xd6, |
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0x55, 0xcf, 0x95, 0xf6, 0x36, 0xf2, 0x09, 0x00 |
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} |
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}; |
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static int reg_index; |
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static const struct qm1d1c0042_config default_cfg = { |
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.xtal_freq = 16000, |
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.lpf = 1, |
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.fast_srch = 0, |
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.lpf_wait = 20, |
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.fast_srch_wait = 4, |
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.normal_srch_wait = 15, |
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}; |
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struct qm1d1c0042_state { |
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struct qm1d1c0042_config cfg; |
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struct i2c_client *i2c; |
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u8 regs[QM1D1C0042_NUM_REGS]; |
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}; |
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static struct qm1d1c0042_state *cfg_to_state(struct qm1d1c0042_config *c) |
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{ |
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return container_of(c, struct qm1d1c0042_state, cfg); |
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} |
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static int reg_write(struct qm1d1c0042_state *state, u8 reg, u8 val) |
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{ |
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u8 wbuf[2] = { reg, val }; |
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int ret; |
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ret = i2c_master_send(state->i2c, wbuf, sizeof(wbuf)); |
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if (ret >= 0 && ret < sizeof(wbuf)) |
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ret = -EIO; |
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return (ret == sizeof(wbuf)) ? 0 : ret; |
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} |
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static int reg_read(struct qm1d1c0042_state *state, u8 reg, u8 *val) |
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{ |
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struct i2c_msg msgs[2] = { |
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{ |
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.addr = state->i2c->addr, |
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.flags = 0, |
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.buf = ®, |
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.len = 1, |
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}, |
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{ |
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.addr = state->i2c->addr, |
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.flags = I2C_M_RD, |
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.buf = val, |
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.len = 1, |
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}, |
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}; |
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int ret; |
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ret = i2c_transfer(state->i2c->adapter, msgs, ARRAY_SIZE(msgs)); |
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if (ret >= 0 && ret < ARRAY_SIZE(msgs)) |
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ret = -EIO; |
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return (ret == ARRAY_SIZE(msgs)) ? 0 : ret; |
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} |
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static int qm1d1c0042_set_srch_mode(struct qm1d1c0042_state *state, bool fast) |
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{ |
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if (fast) |
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state->regs[0x03] |= 0x01; /* set fast search mode */ |
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else |
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state->regs[0x03] &= ~0x01 & 0xff; |
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return reg_write(state, 0x03, state->regs[0x03]); |
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} |
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static int qm1d1c0042_wakeup(struct qm1d1c0042_state *state) |
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{ |
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int ret; |
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state->regs[0x01] |= 1 << 3; /* BB_Reg_enable */ |
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state->regs[0x01] &= (~(1 << 0)) & 0xff; /* NORMAL (wake-up) */ |
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state->regs[0x05] &= (~(1 << 3)) & 0xff; /* pfd_rst NORMAL */ |
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ret = reg_write(state, 0x01, state->regs[0x01]); |
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if (ret == 0) |
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ret = reg_write(state, 0x05, state->regs[0x05]); |
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if (ret < 0) |
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dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n", |
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__func__, state->cfg.fe->dvb->num, state->cfg.fe->id); |
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return ret; |
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} |
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/* tuner_ops */ |
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static int qm1d1c0042_set_config(struct dvb_frontend *fe, void *priv_cfg) |
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{ |
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struct qm1d1c0042_state *state; |
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struct qm1d1c0042_config *cfg; |
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state = fe->tuner_priv; |
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cfg = priv_cfg; |
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if (cfg->fe) |
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state->cfg.fe = cfg->fe; |
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if (cfg->xtal_freq != QM1D1C0042_CFG_XTAL_DFLT) |
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dev_warn(&state->i2c->dev, |
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"(%s) changing xtal_freq not supported. ", __func__); |
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state->cfg.xtal_freq = default_cfg.xtal_freq; |
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state->cfg.lpf = cfg->lpf; |
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state->cfg.fast_srch = cfg->fast_srch; |
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if (cfg->lpf_wait != QM1D1C0042_CFG_WAIT_DFLT) |
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state->cfg.lpf_wait = cfg->lpf_wait; |
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else |
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state->cfg.lpf_wait = default_cfg.lpf_wait; |
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if (cfg->fast_srch_wait != QM1D1C0042_CFG_WAIT_DFLT) |
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state->cfg.fast_srch_wait = cfg->fast_srch_wait; |
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else |
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state->cfg.fast_srch_wait = default_cfg.fast_srch_wait; |
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if (cfg->normal_srch_wait != QM1D1C0042_CFG_WAIT_DFLT) |
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state->cfg.normal_srch_wait = cfg->normal_srch_wait; |
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else |
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state->cfg.normal_srch_wait = default_cfg.normal_srch_wait; |
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return 0; |
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} |
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/* divisor, vco_band parameters */ |
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/* {maxfreq, param1(band?), param2(div?) */ |
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static const u32 conv_table[9][3] = { |
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{ 2151000, 1, 7 }, |
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{ 1950000, 1, 6 }, |
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{ 1800000, 1, 5 }, |
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{ 1600000, 1, 4 }, |
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{ 1450000, 1, 3 }, |
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{ 1250000, 1, 2 }, |
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{ 1200000, 0, 7 }, |
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{ 975000, 0, 6 }, |
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{ 950000, 0, 0 } |
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}; |
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static int qm1d1c0042_set_params(struct dvb_frontend *fe) |
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{ |
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struct qm1d1c0042_state *state; |
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u32 freq; |
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int i, ret; |
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u8 val, mask; |
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u32 a, sd; |
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s32 b; |
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state = fe->tuner_priv; |
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freq = fe->dtv_property_cache.frequency; |
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state->regs[0x08] &= 0xf0; |
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state->regs[0x08] |= 0x09; |
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state->regs[0x13] &= 0x9f; |
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state->regs[0x13] |= 0x20; |
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/* div2/vco_band */ |
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val = state->regs[0x02] & 0x0f; |
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for (i = 0; i < 8; i++) |
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if (freq < conv_table[i][0] && freq >= conv_table[i + 1][0]) { |
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val |= conv_table[i][1] << 7; |
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val |= conv_table[i][2] << 4; |
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break; |
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} |
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ret = reg_write(state, 0x02, val); |
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if (ret < 0) |
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return ret; |
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a = DIV_ROUND_CLOSEST(freq, state->cfg.xtal_freq); |
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state->regs[0x06] &= 0x40; |
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state->regs[0x06] |= (a - 12) / 4; |
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ret = reg_write(state, 0x06, state->regs[0x06]); |
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if (ret < 0) |
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return ret; |
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state->regs[0x07] &= 0xf0; |
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state->regs[0x07] |= (a - 4 * ((a - 12) / 4 + 1) - 5) & 0x0f; |
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ret = reg_write(state, 0x07, state->regs[0x07]); |
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if (ret < 0) |
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return ret; |
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/* LPF */ |
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val = state->regs[0x08]; |
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if (state->cfg.lpf) { |
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/* LPF_CLK, LPF_FC */ |
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val &= 0xf0; |
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val |= 0x02; |
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} |
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ret = reg_write(state, 0x08, val); |
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if (ret < 0) |
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return ret; |
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/* |
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* b = (freq / state->cfg.xtal_freq - a) << 20; |
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* sd = b (b >= 0) |
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* 1<<22 + b (b < 0) |
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*/ |
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b = (s32)div64_s64(((s64) freq) << 20, state->cfg.xtal_freq) |
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- (((s64) a) << 20); |
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if (b >= 0) |
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sd = b; |
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else |
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sd = (1 << 22) + b; |
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state->regs[0x09] &= 0xc0; |
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state->regs[0x09] |= (sd >> 16) & 0x3f; |
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state->regs[0x0a] = (sd >> 8) & 0xff; |
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state->regs[0x0b] = sd & 0xff; |
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ret = reg_write(state, 0x09, state->regs[0x09]); |
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if (ret == 0) |
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ret = reg_write(state, 0x0a, state->regs[0x0a]); |
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if (ret == 0) |
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ret = reg_write(state, 0x0b, state->regs[0x0b]); |
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if (ret != 0) |
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return ret; |
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if (!state->cfg.lpf) { |
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/* CSEL_Offset */ |
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ret = reg_write(state, 0x13, state->regs[0x13]); |
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if (ret < 0) |
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return ret; |
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} |
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/* VCO_TM, LPF_TM */ |
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mask = state->cfg.lpf ? 0x3f : 0x7f; |
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val = state->regs[0x0c] & mask; |
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ret = reg_write(state, 0x0c, val); |
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if (ret < 0) |
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return ret; |
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usleep_range(2000, 3000); |
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val = state->regs[0x0c] | ~mask; |
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ret = reg_write(state, 0x0c, val); |
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if (ret < 0) |
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return ret; |
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if (state->cfg.lpf) |
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msleep(state->cfg.lpf_wait); |
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else if (state->regs[0x03] & 0x01) |
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msleep(state->cfg.fast_srch_wait); |
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else |
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msleep(state->cfg.normal_srch_wait); |
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if (state->cfg.lpf) { |
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/* LPF_FC */ |
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ret = reg_write(state, 0x08, 0x09); |
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if (ret < 0) |
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return ret; |
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/* CSEL_Offset */ |
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ret = reg_write(state, 0x13, state->regs[0x13]); |
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if (ret < 0) |
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return ret; |
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} |
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return 0; |
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} |
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static int qm1d1c0042_sleep(struct dvb_frontend *fe) |
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{ |
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struct qm1d1c0042_state *state; |
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int ret; |
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state = fe->tuner_priv; |
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state->regs[0x01] &= (~(1 << 3)) & 0xff; /* BB_Reg_disable */ |
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state->regs[0x01] |= 1 << 0; /* STDBY */ |
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state->regs[0x05] |= 1 << 3; /* pfd_rst STANDBY */ |
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ret = reg_write(state, 0x05, state->regs[0x05]); |
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if (ret == 0) |
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ret = reg_write(state, 0x01, state->regs[0x01]); |
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if (ret < 0) |
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dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n", |
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__func__, fe->dvb->num, fe->id); |
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return ret; |
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} |
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static int qm1d1c0042_init(struct dvb_frontend *fe) |
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{ |
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struct qm1d1c0042_state *state; |
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u8 val; |
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int i, ret; |
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state = fe->tuner_priv; |
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reg_write(state, 0x01, 0x0c); |
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reg_write(state, 0x01, 0x0c); |
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ret = reg_write(state, 0x01, 0x0c); /* soft reset on */ |
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if (ret < 0) |
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goto failed; |
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usleep_range(2000, 3000); |
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ret = reg_write(state, 0x01, 0x1c); /* soft reset off */ |
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if (ret < 0) |
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goto failed; |
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/* check ID and choose initial registers corresponding ID */ |
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ret = reg_read(state, 0x00, &val); |
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if (ret < 0) |
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goto failed; |
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for (reg_index = 0; reg_index < QM1D1C0042_NUM_REG_ROWS; |
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reg_index++) { |
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if (val == reg_initval[reg_index][0x00]) |
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break; |
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} |
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if (reg_index >= QM1D1C0042_NUM_REG_ROWS) { |
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ret = -EINVAL; |
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goto failed; |
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} |
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memcpy(state->regs, reg_initval[reg_index], QM1D1C0042_NUM_REGS); |
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usleep_range(2000, 3000); |
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state->regs[0x0c] |= 0x40; |
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ret = reg_write(state, 0x0c, state->regs[0x0c]); |
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if (ret < 0) |
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goto failed; |
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msleep(state->cfg.lpf_wait); |
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/* set all writable registers */ |
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for (i = 1; i <= 0x0c ; i++) { |
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ret = reg_write(state, i, state->regs[i]); |
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if (ret < 0) |
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goto failed; |
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} |
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for (i = 0x11; i < QM1D1C0042_NUM_REGS; i++) { |
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ret = reg_write(state, i, state->regs[i]); |
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if (ret < 0) |
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goto failed; |
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} |
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ret = qm1d1c0042_wakeup(state); |
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if (ret < 0) |
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goto failed; |
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ret = qm1d1c0042_set_srch_mode(state, state->cfg.fast_srch); |
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if (ret < 0) |
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goto failed; |
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return ret; |
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failed: |
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dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n", |
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__func__, fe->dvb->num, fe->id); |
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return ret; |
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} |
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/* I2C driver functions */ |
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static const struct dvb_tuner_ops qm1d1c0042_ops = { |
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.info = { |
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.name = "Sharp QM1D1C0042", |
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.frequency_min_hz = 950 * MHz, |
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.frequency_max_hz = 2150 * MHz, |
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}, |
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.init = qm1d1c0042_init, |
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.sleep = qm1d1c0042_sleep, |
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.set_config = qm1d1c0042_set_config, |
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.set_params = qm1d1c0042_set_params, |
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}; |
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static int qm1d1c0042_probe(struct i2c_client *client, |
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const struct i2c_device_id *id) |
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{ |
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struct qm1d1c0042_state *state; |
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struct qm1d1c0042_config *cfg; |
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struct dvb_frontend *fe; |
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state = kzalloc(sizeof(*state), GFP_KERNEL); |
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if (!state) |
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return -ENOMEM; |
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state->i2c = client; |
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cfg = client->dev.platform_data; |
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fe = cfg->fe; |
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fe->tuner_priv = state; |
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qm1d1c0042_set_config(fe, cfg); |
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memcpy(&fe->ops.tuner_ops, &qm1d1c0042_ops, sizeof(qm1d1c0042_ops)); |
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i2c_set_clientdata(client, &state->cfg); |
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dev_info(&client->dev, "Sharp QM1D1C0042 attached.\n"); |
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return 0; |
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} |
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static int qm1d1c0042_remove(struct i2c_client *client) |
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{ |
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struct qm1d1c0042_state *state; |
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state = cfg_to_state(i2c_get_clientdata(client)); |
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state->cfg.fe->tuner_priv = NULL; |
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kfree(state); |
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return 0; |
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} |
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static const struct i2c_device_id qm1d1c0042_id[] = { |
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{"qm1d1c0042", 0}, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(i2c, qm1d1c0042_id); |
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static struct i2c_driver qm1d1c0042_driver = { |
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.driver = { |
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.name = "qm1d1c0042", |
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}, |
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.probe = qm1d1c0042_probe, |
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.remove = qm1d1c0042_remove, |
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.id_table = qm1d1c0042_id, |
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}; |
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module_i2c_driver(qm1d1c0042_driver); |
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MODULE_DESCRIPTION("Sharp QM1D1C0042 tuner"); |
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MODULE_AUTHOR("Akihiro TSUKADA"); |
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MODULE_LICENSE("GPL");
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