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1221 lines
33 KiB
1221 lines
33 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* winbond-cir.c - Driver for the Consumer IR functionality of Winbond |
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* SuperI/O chips. |
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* |
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* Currently supports the Winbond WPCD376i chip (PNP id WEC1022), but |
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* could probably support others (Winbond WEC102X, NatSemi, etc) |
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* with minor modifications. |
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* |
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* Original Author: David Härdeman <[email protected]> |
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* Copyright (C) 2012 Sean Young <[email protected]> |
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* Copyright (C) 2009 - 2011 David Härdeman <[email protected]> |
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* |
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* Dedicated to my daughter Matilda, without whose loving attention this |
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* driver would have been finished in half the time and with a fraction |
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* of the bugs. |
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* |
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* Written using: |
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* o Winbond WPCD376I datasheet helpfully provided by Jesse Barnes at Intel |
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* o NatSemi PC87338/PC97338 datasheet (for the serial port stuff) |
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* o DSDT dumps |
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* |
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* Supported features: |
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* o IR Receive |
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* o IR Transmit |
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* o Wake-On-CIR functionality |
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* o Carrier detection |
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*/ |
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|
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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|
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#include <linux/module.h> |
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#include <linux/pnp.h> |
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#include <linux/interrupt.h> |
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#include <linux/timer.h> |
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#include <linux/leds.h> |
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#include <linux/spinlock.h> |
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#include <linux/pci_ids.h> |
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#include <linux/io.h> |
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#include <linux/bitrev.h> |
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#include <linux/slab.h> |
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#include <linux/wait.h> |
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#include <linux/sched.h> |
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#include <media/rc-core.h> |
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#define DRVNAME "winbond-cir" |
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|
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/* CEIR Wake-Up Registers, relative to data->wbase */ |
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#define WBCIR_REG_WCEIR_CTL 0x03 /* CEIR Receiver Control */ |
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#define WBCIR_REG_WCEIR_STS 0x04 /* CEIR Receiver Status */ |
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#define WBCIR_REG_WCEIR_EV_EN 0x05 /* CEIR Receiver Event Enable */ |
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#define WBCIR_REG_WCEIR_CNTL 0x06 /* CEIR Receiver Counter Low */ |
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#define WBCIR_REG_WCEIR_CNTH 0x07 /* CEIR Receiver Counter High */ |
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#define WBCIR_REG_WCEIR_INDEX 0x08 /* CEIR Receiver Index */ |
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#define WBCIR_REG_WCEIR_DATA 0x09 /* CEIR Receiver Data */ |
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#define WBCIR_REG_WCEIR_CSL 0x0A /* CEIR Re. Compare Strlen */ |
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#define WBCIR_REG_WCEIR_CFG1 0x0B /* CEIR Re. Configuration 1 */ |
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#define WBCIR_REG_WCEIR_CFG2 0x0C /* CEIR Re. Configuration 2 */ |
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|
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/* CEIR Enhanced Functionality Registers, relative to data->ebase */ |
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#define WBCIR_REG_ECEIR_CTS 0x00 /* Enhanced IR Control Status */ |
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#define WBCIR_REG_ECEIR_CCTL 0x01 /* Infrared Counter Control */ |
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#define WBCIR_REG_ECEIR_CNT_LO 0x02 /* Infrared Counter LSB */ |
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#define WBCIR_REG_ECEIR_CNT_HI 0x03 /* Infrared Counter MSB */ |
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#define WBCIR_REG_ECEIR_IREM 0x04 /* Infrared Emitter Status */ |
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|
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/* SP3 Banked Registers, relative to data->sbase */ |
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#define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */ |
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/* Bank 0 */ |
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#define WBCIR_REG_SP3_RXDATA 0x00 /* FIFO RX data (r) */ |
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#define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */ |
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#define WBCIR_REG_SP3_IER 0x01 /* Interrupt Enable */ |
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#define WBCIR_REG_SP3_EIR 0x02 /* Event Identification (r) */ |
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#define WBCIR_REG_SP3_FCR 0x02 /* FIFO Control (w) */ |
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#define WBCIR_REG_SP3_MCR 0x04 /* Mode Control */ |
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#define WBCIR_REG_SP3_LSR 0x05 /* Link Status */ |
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#define WBCIR_REG_SP3_MSR 0x06 /* Modem Status */ |
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#define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */ |
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/* Bank 2 */ |
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#define WBCIR_REG_SP3_BGDL 0x00 /* Baud Divisor LSB */ |
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#define WBCIR_REG_SP3_BGDH 0x01 /* Baud Divisor MSB */ |
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#define WBCIR_REG_SP3_EXCR1 0x02 /* Extended Control 1 */ |
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#define WBCIR_REG_SP3_EXCR2 0x04 /* Extended Control 2 */ |
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#define WBCIR_REG_SP3_TXFLV 0x06 /* TX FIFO Level */ |
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#define WBCIR_REG_SP3_RXFLV 0x07 /* RX FIFO Level */ |
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/* Bank 3 */ |
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#define WBCIR_REG_SP3_MRID 0x00 /* Module Identification */ |
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#define WBCIR_REG_SP3_SH_LCR 0x01 /* LCR Shadow */ |
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#define WBCIR_REG_SP3_SH_FCR 0x02 /* FCR Shadow */ |
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/* Bank 4 */ |
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#define WBCIR_REG_SP3_IRCR1 0x02 /* Infrared Control 1 */ |
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/* Bank 5 */ |
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#define WBCIR_REG_SP3_IRCR2 0x04 /* Infrared Control 2 */ |
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/* Bank 6 */ |
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#define WBCIR_REG_SP3_IRCR3 0x00 /* Infrared Control 3 */ |
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#define WBCIR_REG_SP3_SIR_PW 0x02 /* SIR Pulse Width */ |
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/* Bank 7 */ |
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#define WBCIR_REG_SP3_IRRXDC 0x00 /* IR RX Demod Control */ |
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#define WBCIR_REG_SP3_IRTXMC 0x01 /* IR TX Mod Control */ |
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#define WBCIR_REG_SP3_RCCFG 0x02 /* CEIR Config */ |
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#define WBCIR_REG_SP3_IRCFG1 0x04 /* Infrared Config 1 */ |
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#define WBCIR_REG_SP3_IRCFG4 0x07 /* Infrared Config 4 */ |
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/* |
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* Magic values follow |
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*/ |
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|
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/* No interrupts for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ |
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#define WBCIR_IRQ_NONE 0x00 |
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/* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ |
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#define WBCIR_IRQ_RX 0x01 |
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/* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ |
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#define WBCIR_IRQ_TX_LOW 0x02 |
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/* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ |
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#define WBCIR_IRQ_ERR 0x04 |
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/* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */ |
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#define WBCIR_IRQ_TX_EMPTY 0x20 |
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/* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */ |
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#define WBCIR_LED_ENABLE 0x80 |
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/* RX data available bit for WBCIR_REG_SP3_LSR */ |
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#define WBCIR_RX_AVAIL 0x01 |
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/* RX data overrun error bit for WBCIR_REG_SP3_LSR */ |
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#define WBCIR_RX_OVERRUN 0x02 |
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/* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */ |
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#define WBCIR_TX_EOT 0x04 |
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/* RX disable bit for WBCIR_REG_SP3_ASCR */ |
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#define WBCIR_RX_DISABLE 0x20 |
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/* TX data underrun error bit for WBCIR_REG_SP3_ASCR */ |
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#define WBCIR_TX_UNDERRUN 0x40 |
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/* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */ |
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#define WBCIR_EXT_ENABLE 0x01 |
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/* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */ |
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#define WBCIR_REGSEL_COMPARE 0x10 |
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/* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */ |
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#define WBCIR_REGSEL_MASK 0x20 |
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/* Starting address of selected register in WBCIR_REG_WCEIR_INDEX */ |
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#define WBCIR_REG_ADDR0 0x00 |
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/* Enable carrier counter */ |
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#define WBCIR_CNTR_EN 0x01 |
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/* Reset carrier counter */ |
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#define WBCIR_CNTR_R 0x02 |
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/* Invert TX */ |
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#define WBCIR_IRTX_INV 0x04 |
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/* Receiver oversampling */ |
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#define WBCIR_RX_T_OV 0x40 |
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|
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/* Valid banks for the SP3 UART */ |
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enum wbcir_bank { |
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WBCIR_BANK_0 = 0x00, |
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WBCIR_BANK_1 = 0x80, |
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WBCIR_BANK_2 = 0xE0, |
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WBCIR_BANK_3 = 0xE4, |
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WBCIR_BANK_4 = 0xE8, |
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WBCIR_BANK_5 = 0xEC, |
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WBCIR_BANK_6 = 0xF0, |
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WBCIR_BANK_7 = 0xF4, |
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}; |
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/* Supported power-on IR Protocols */ |
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enum wbcir_protocol { |
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IR_PROTOCOL_RC5 = 0x0, |
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IR_PROTOCOL_NEC = 0x1, |
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IR_PROTOCOL_RC6 = 0x2, |
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}; |
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/* Possible states for IR reception */ |
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enum wbcir_rxstate { |
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WBCIR_RXSTATE_INACTIVE = 0, |
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WBCIR_RXSTATE_ACTIVE, |
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WBCIR_RXSTATE_ERROR |
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}; |
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/* Possible states for IR transmission */ |
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enum wbcir_txstate { |
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WBCIR_TXSTATE_INACTIVE = 0, |
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WBCIR_TXSTATE_ACTIVE, |
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WBCIR_TXSTATE_ERROR |
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}; |
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/* Misc */ |
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#define WBCIR_NAME "Winbond CIR" |
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#define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */ |
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#define WBCIR_ID_CHIP 0x04 /* Chip ID for the WPCD376I */ |
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#define WAKEUP_IOMEM_LEN 0x10 /* Wake-Up I/O Reg Len */ |
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#define EHFUNC_IOMEM_LEN 0x10 /* Enhanced Func I/O Reg Len */ |
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#define SP_IOMEM_LEN 0x08 /* Serial Port 3 (IR) Reg Len */ |
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/* Per-device data */ |
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struct wbcir_data { |
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spinlock_t spinlock; |
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struct rc_dev *dev; |
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struct led_classdev led; |
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unsigned long wbase; /* Wake-Up Baseaddr */ |
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unsigned long ebase; /* Enhanced Func. Baseaddr */ |
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unsigned long sbase; /* Serial Port Baseaddr */ |
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unsigned int irq; /* Serial Port IRQ */ |
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u8 irqmask; |
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/* RX state */ |
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enum wbcir_rxstate rxstate; |
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int carrier_report_enabled; |
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u32 pulse_duration; |
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/* TX state */ |
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enum wbcir_txstate txstate; |
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u32 txlen; |
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u32 txoff; |
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u32 *txbuf; |
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u8 txmask; |
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u32 txcarrier; |
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}; |
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static bool invert; /* default = 0 */ |
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module_param(invert, bool, 0444); |
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MODULE_PARM_DESC(invert, "Invert the signal from the IR receiver"); |
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static bool txandrx; /* default = 0 */ |
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module_param(txandrx, bool, 0444); |
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MODULE_PARM_DESC(txandrx, "Allow simultaneous TX and RX"); |
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/***************************************************************************** |
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* |
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* UTILITY FUNCTIONS |
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* |
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*****************************************************************************/ |
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/* Caller needs to hold wbcir_lock */ |
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static void |
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wbcir_set_bits(unsigned long addr, u8 bits, u8 mask) |
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{ |
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u8 val; |
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val = inb(addr); |
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val = ((val & ~mask) | (bits & mask)); |
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outb(val, addr); |
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} |
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/* Selects the register bank for the serial port */ |
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static inline void |
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wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank) |
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{ |
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outb(bank, data->sbase + WBCIR_REG_SP3_BSR); |
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} |
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static inline void |
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wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask) |
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{ |
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if (data->irqmask == irqmask) |
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return; |
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wbcir_select_bank(data, WBCIR_BANK_0); |
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outb(irqmask, data->sbase + WBCIR_REG_SP3_IER); |
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data->irqmask = irqmask; |
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} |
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static enum led_brightness |
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wbcir_led_brightness_get(struct led_classdev *led_cdev) |
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{ |
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struct wbcir_data *data = container_of(led_cdev, |
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struct wbcir_data, |
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led); |
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if (inb(data->ebase + WBCIR_REG_ECEIR_CTS) & WBCIR_LED_ENABLE) |
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return LED_FULL; |
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else |
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return LED_OFF; |
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} |
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static void |
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wbcir_led_brightness_set(struct led_classdev *led_cdev, |
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enum led_brightness brightness) |
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{ |
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struct wbcir_data *data = container_of(led_cdev, |
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struct wbcir_data, |
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led); |
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wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, |
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brightness == LED_OFF ? 0x00 : WBCIR_LED_ENABLE, |
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WBCIR_LED_ENABLE); |
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} |
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/* Manchester encodes bits to RC6 message cells (see wbcir_shutdown) */ |
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static u8 |
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wbcir_to_rc6cells(u8 val) |
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{ |
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u8 coded = 0x00; |
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int i; |
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val &= 0x0F; |
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for (i = 0; i < 4; i++) { |
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if (val & 0x01) |
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coded |= 0x02 << (i * 2); |
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else |
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coded |= 0x01 << (i * 2); |
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val >>= 1; |
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} |
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return coded; |
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} |
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|
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/***************************************************************************** |
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* |
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* INTERRUPT FUNCTIONS |
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* |
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*****************************************************************************/ |
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static void |
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wbcir_carrier_report(struct wbcir_data *data) |
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{ |
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unsigned counter = inb(data->ebase + WBCIR_REG_ECEIR_CNT_LO) | |
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inb(data->ebase + WBCIR_REG_ECEIR_CNT_HI) << 8; |
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|
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if (counter > 0 && counter < 0xffff) { |
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struct ir_raw_event ev = { |
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.carrier_report = 1, |
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.carrier = DIV_ROUND_CLOSEST(counter * 1000000u, |
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data->pulse_duration) |
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}; |
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ir_raw_event_store(data->dev, &ev); |
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} |
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/* reset and restart the counter */ |
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data->pulse_duration = 0; |
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wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R, |
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WBCIR_CNTR_EN | WBCIR_CNTR_R); |
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wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_EN, |
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WBCIR_CNTR_EN | WBCIR_CNTR_R); |
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} |
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static void |
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wbcir_idle_rx(struct rc_dev *dev, bool idle) |
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{ |
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struct wbcir_data *data = dev->priv; |
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if (!idle && data->rxstate == WBCIR_RXSTATE_INACTIVE) |
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data->rxstate = WBCIR_RXSTATE_ACTIVE; |
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if (idle && data->rxstate != WBCIR_RXSTATE_INACTIVE) { |
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data->rxstate = WBCIR_RXSTATE_INACTIVE; |
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if (data->carrier_report_enabled) |
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wbcir_carrier_report(data); |
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|
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/* Tell hardware to go idle by setting RXINACTIVE */ |
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outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR); |
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} |
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} |
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static void |
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wbcir_irq_rx(struct wbcir_data *data, struct pnp_dev *device) |
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{ |
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u8 irdata; |
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struct ir_raw_event rawir = {}; |
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|
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/* Since RXHDLEV is set, at least 8 bytes are in the FIFO */ |
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while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL) { |
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irdata = inb(data->sbase + WBCIR_REG_SP3_RXDATA); |
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if (data->rxstate == WBCIR_RXSTATE_ERROR) |
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continue; |
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rawir.duration = ((irdata & 0x7F) + 1) * |
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(data->carrier_report_enabled ? 2 : 10); |
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rawir.pulse = irdata & 0x80 ? false : true; |
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if (rawir.pulse) |
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data->pulse_duration += rawir.duration; |
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ir_raw_event_store_with_filter(data->dev, &rawir); |
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} |
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ir_raw_event_handle(data->dev); |
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} |
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static void |
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wbcir_irq_tx(struct wbcir_data *data) |
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{ |
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unsigned int space; |
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unsigned int used; |
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u8 bytes[16]; |
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u8 byte; |
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|
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if (!data->txbuf) |
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return; |
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switch (data->txstate) { |
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case WBCIR_TXSTATE_INACTIVE: |
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/* TX FIFO empty */ |
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space = 16; |
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break; |
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case WBCIR_TXSTATE_ACTIVE: |
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/* TX FIFO low (3 bytes or less) */ |
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space = 13; |
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break; |
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case WBCIR_TXSTATE_ERROR: |
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space = 0; |
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break; |
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default: |
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return; |
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} |
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|
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/* |
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* TX data is run-length coded in bytes: YXXXXXXX |
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* Y = space (1) or pulse (0) |
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* X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us) |
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*/ |
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for (used = 0; used < space && data->txoff != data->txlen; used++) { |
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if (data->txbuf[data->txoff] == 0) { |
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data->txoff++; |
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continue; |
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} |
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byte = min((u32)0x80, data->txbuf[data->txoff]); |
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data->txbuf[data->txoff] -= byte; |
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byte--; |
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byte |= (data->txoff % 2 ? 0x80 : 0x00); /* pulse/space */ |
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bytes[used] = byte; |
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} |
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|
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while (data->txoff != data->txlen && data->txbuf[data->txoff] == 0) |
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data->txoff++; |
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|
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if (used == 0) { |
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/* Finished */ |
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if (data->txstate == WBCIR_TXSTATE_ERROR) |
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/* Clear TX underrun bit */ |
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outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR); |
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wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR); |
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kfree(data->txbuf); |
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data->txbuf = NULL; |
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data->txstate = WBCIR_TXSTATE_INACTIVE; |
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} else if (data->txoff == data->txlen) { |
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/* At the end of transmission, tell the hw before last byte */ |
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outsb(data->sbase + WBCIR_REG_SP3_TXDATA, bytes, used - 1); |
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outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR); |
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outb(bytes[used - 1], data->sbase + WBCIR_REG_SP3_TXDATA); |
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wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR | |
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WBCIR_IRQ_TX_EMPTY); |
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} else { |
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/* More data to follow... */ |
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outsb(data->sbase + WBCIR_REG_SP3_RXDATA, bytes, used); |
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if (data->txstate == WBCIR_TXSTATE_INACTIVE) { |
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wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR | |
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WBCIR_IRQ_TX_LOW); |
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data->txstate = WBCIR_TXSTATE_ACTIVE; |
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} |
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} |
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} |
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|
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static irqreturn_t |
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wbcir_irq_handler(int irqno, void *cookie) |
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{ |
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struct pnp_dev *device = cookie; |
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struct wbcir_data *data = pnp_get_drvdata(device); |
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unsigned long flags; |
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u8 status; |
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|
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spin_lock_irqsave(&data->spinlock, flags); |
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wbcir_select_bank(data, WBCIR_BANK_0); |
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status = inb(data->sbase + WBCIR_REG_SP3_EIR); |
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status &= data->irqmask; |
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|
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if (!status) { |
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spin_unlock_irqrestore(&data->spinlock, flags); |
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return IRQ_NONE; |
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} |
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|
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if (status & WBCIR_IRQ_ERR) { |
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/* RX overflow? (read clears bit) */ |
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if (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_OVERRUN) { |
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data->rxstate = WBCIR_RXSTATE_ERROR; |
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ir_raw_event_reset(data->dev); |
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} |
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|
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/* TX underflow? */ |
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if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN) |
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data->txstate = WBCIR_TXSTATE_ERROR; |
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} |
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|
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if (status & WBCIR_IRQ_RX) |
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wbcir_irq_rx(data, device); |
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|
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if (status & (WBCIR_IRQ_TX_LOW | WBCIR_IRQ_TX_EMPTY)) |
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wbcir_irq_tx(data); |
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|
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spin_unlock_irqrestore(&data->spinlock, flags); |
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return IRQ_HANDLED; |
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} |
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|
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/***************************************************************************** |
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* |
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* RC-CORE INTERFACE FUNCTIONS |
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* |
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*****************************************************************************/ |
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|
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static int |
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wbcir_set_carrier_report(struct rc_dev *dev, int enable) |
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{ |
|
struct wbcir_data *data = dev->priv; |
|
unsigned long flags; |
|
|
|
spin_lock_irqsave(&data->spinlock, flags); |
|
|
|
if (data->carrier_report_enabled == enable) { |
|
spin_unlock_irqrestore(&data->spinlock, flags); |
|
return 0; |
|
} |
|
|
|
data->pulse_duration = 0; |
|
wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, WBCIR_CNTR_R, |
|
WBCIR_CNTR_EN | WBCIR_CNTR_R); |
|
|
|
if (enable && data->dev->idle) |
|
wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CCTL, |
|
WBCIR_CNTR_EN, WBCIR_CNTR_EN | WBCIR_CNTR_R); |
|
|
|
/* Set a higher sampling resolution if carrier reports are enabled */ |
|
wbcir_select_bank(data, WBCIR_BANK_2); |
|
data->dev->rx_resolution = enable ? 2 : 10; |
|
outb(enable ? 0x03 : 0x0f, data->sbase + WBCIR_REG_SP3_BGDL); |
|
outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH); |
|
|
|
/* Enable oversampling if carrier reports are enabled */ |
|
wbcir_select_bank(data, WBCIR_BANK_7); |
|
wbcir_set_bits(data->sbase + WBCIR_REG_SP3_RCCFG, |
|
enable ? WBCIR_RX_T_OV : 0, WBCIR_RX_T_OV); |
|
|
|
data->carrier_report_enabled = enable; |
|
spin_unlock_irqrestore(&data->spinlock, flags); |
|
|
|
return 0; |
|
} |
|
|
|
static int |
|
wbcir_txcarrier(struct rc_dev *dev, u32 carrier) |
|
{ |
|
struct wbcir_data *data = dev->priv; |
|
unsigned long flags; |
|
u8 val; |
|
u32 freq; |
|
|
|
freq = DIV_ROUND_CLOSEST(carrier, 1000); |
|
if (freq < 30 || freq > 60) |
|
return -EINVAL; |
|
|
|
switch (freq) { |
|
case 58: |
|
case 59: |
|
case 60: |
|
val = freq - 58; |
|
freq *= 1000; |
|
break; |
|
case 57: |
|
val = freq - 27; |
|
freq = 56900; |
|
break; |
|
default: |
|
val = freq - 27; |
|
freq *= 1000; |
|
break; |
|
} |
|
|
|
spin_lock_irqsave(&data->spinlock, flags); |
|
if (data->txstate != WBCIR_TXSTATE_INACTIVE) { |
|
spin_unlock_irqrestore(&data->spinlock, flags); |
|
return -EBUSY; |
|
} |
|
|
|
if (data->txcarrier != freq) { |
|
wbcir_select_bank(data, WBCIR_BANK_7); |
|
wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F); |
|
data->txcarrier = freq; |
|
} |
|
|
|
spin_unlock_irqrestore(&data->spinlock, flags); |
|
return 0; |
|
} |
|
|
|
static int |
|
wbcir_txmask(struct rc_dev *dev, u32 mask) |
|
{ |
|
struct wbcir_data *data = dev->priv; |
|
unsigned long flags; |
|
u8 val; |
|
|
|
/* return the number of transmitters */ |
|
if (mask > 15) |
|
return 4; |
|
|
|
/* Four outputs, only one output can be enabled at a time */ |
|
switch (mask) { |
|
case 0x1: |
|
val = 0x0; |
|
break; |
|
case 0x2: |
|
val = 0x1; |
|
break; |
|
case 0x4: |
|
val = 0x2; |
|
break; |
|
case 0x8: |
|
val = 0x3; |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
spin_lock_irqsave(&data->spinlock, flags); |
|
if (data->txstate != WBCIR_TXSTATE_INACTIVE) { |
|
spin_unlock_irqrestore(&data->spinlock, flags); |
|
return -EBUSY; |
|
} |
|
|
|
if (data->txmask != mask) { |
|
wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c); |
|
data->txmask = mask; |
|
} |
|
|
|
spin_unlock_irqrestore(&data->spinlock, flags); |
|
return 0; |
|
} |
|
|
|
static int |
|
wbcir_tx(struct rc_dev *dev, unsigned *b, unsigned count) |
|
{ |
|
struct wbcir_data *data = dev->priv; |
|
unsigned *buf; |
|
unsigned i; |
|
unsigned long flags; |
|
|
|
buf = kmalloc_array(count, sizeof(*b), GFP_KERNEL); |
|
if (!buf) |
|
return -ENOMEM; |
|
|
|
/* Convert values to multiples of 10us */ |
|
for (i = 0; i < count; i++) |
|
buf[i] = DIV_ROUND_CLOSEST(b[i], 10); |
|
|
|
/* Not sure if this is possible, but better safe than sorry */ |
|
spin_lock_irqsave(&data->spinlock, flags); |
|
if (data->txstate != WBCIR_TXSTATE_INACTIVE) { |
|
spin_unlock_irqrestore(&data->spinlock, flags); |
|
kfree(buf); |
|
return -EBUSY; |
|
} |
|
|
|
/* Fill the TX fifo once, the irq handler will do the rest */ |
|
data->txbuf = buf; |
|
data->txlen = count; |
|
data->txoff = 0; |
|
wbcir_irq_tx(data); |
|
|
|
/* We're done */ |
|
spin_unlock_irqrestore(&data->spinlock, flags); |
|
return count; |
|
} |
|
|
|
/***************************************************************************** |
|
* |
|
* SETUP/INIT/SUSPEND/RESUME FUNCTIONS |
|
* |
|
*****************************************************************************/ |
|
|
|
static void |
|
wbcir_shutdown(struct pnp_dev *device) |
|
{ |
|
struct device *dev = &device->dev; |
|
struct wbcir_data *data = pnp_get_drvdata(device); |
|
struct rc_dev *rc = data->dev; |
|
bool do_wake = true; |
|
u8 match[11]; |
|
u8 mask[11]; |
|
u8 rc6_csl = 0; |
|
u8 proto; |
|
u32 wake_sc = rc->scancode_wakeup_filter.data; |
|
u32 mask_sc = rc->scancode_wakeup_filter.mask; |
|
int i; |
|
|
|
memset(match, 0, sizeof(match)); |
|
memset(mask, 0, sizeof(mask)); |
|
|
|
if (!mask_sc || !device_may_wakeup(dev)) { |
|
do_wake = false; |
|
goto finish; |
|
} |
|
|
|
switch (rc->wakeup_protocol) { |
|
case RC_PROTO_RC5: |
|
/* Mask = 13 bits, ex toggle */ |
|
mask[0] = (mask_sc & 0x003f); |
|
mask[0] |= (mask_sc & 0x0300) >> 2; |
|
mask[1] = (mask_sc & 0x1c00) >> 10; |
|
if (mask_sc & 0x0040) /* 2nd start bit */ |
|
match[1] |= 0x10; |
|
|
|
match[0] = (wake_sc & 0x003F); /* 6 command bits */ |
|
match[0] |= (wake_sc & 0x0300) >> 2; /* 2 address bits */ |
|
match[1] = (wake_sc & 0x1c00) >> 10; /* 3 address bits */ |
|
if (!(wake_sc & 0x0040)) /* 2nd start bit */ |
|
match[1] |= 0x10; |
|
|
|
proto = IR_PROTOCOL_RC5; |
|
break; |
|
|
|
case RC_PROTO_NEC: |
|
mask[1] = bitrev8(mask_sc); |
|
mask[0] = mask[1]; |
|
mask[3] = bitrev8(mask_sc >> 8); |
|
mask[2] = mask[3]; |
|
|
|
match[1] = bitrev8(wake_sc); |
|
match[0] = ~match[1]; |
|
match[3] = bitrev8(wake_sc >> 8); |
|
match[2] = ~match[3]; |
|
|
|
proto = IR_PROTOCOL_NEC; |
|
break; |
|
|
|
case RC_PROTO_NECX: |
|
mask[1] = bitrev8(mask_sc); |
|
mask[0] = mask[1]; |
|
mask[2] = bitrev8(mask_sc >> 8); |
|
mask[3] = bitrev8(mask_sc >> 16); |
|
|
|
match[1] = bitrev8(wake_sc); |
|
match[0] = ~match[1]; |
|
match[2] = bitrev8(wake_sc >> 8); |
|
match[3] = bitrev8(wake_sc >> 16); |
|
|
|
proto = IR_PROTOCOL_NEC; |
|
break; |
|
|
|
case RC_PROTO_NEC32: |
|
mask[0] = bitrev8(mask_sc); |
|
mask[1] = bitrev8(mask_sc >> 8); |
|
mask[2] = bitrev8(mask_sc >> 16); |
|
mask[3] = bitrev8(mask_sc >> 24); |
|
|
|
match[0] = bitrev8(wake_sc); |
|
match[1] = bitrev8(wake_sc >> 8); |
|
match[2] = bitrev8(wake_sc >> 16); |
|
match[3] = bitrev8(wake_sc >> 24); |
|
|
|
proto = IR_PROTOCOL_NEC; |
|
break; |
|
|
|
case RC_PROTO_RC6_0: |
|
/* Command */ |
|
match[0] = wbcir_to_rc6cells(wake_sc >> 0); |
|
mask[0] = wbcir_to_rc6cells(mask_sc >> 0); |
|
match[1] = wbcir_to_rc6cells(wake_sc >> 4); |
|
mask[1] = wbcir_to_rc6cells(mask_sc >> 4); |
|
|
|
/* Address */ |
|
match[2] = wbcir_to_rc6cells(wake_sc >> 8); |
|
mask[2] = wbcir_to_rc6cells(mask_sc >> 8); |
|
match[3] = wbcir_to_rc6cells(wake_sc >> 12); |
|
mask[3] = wbcir_to_rc6cells(mask_sc >> 12); |
|
|
|
/* Header */ |
|
match[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */ |
|
mask[4] = 0xF0; |
|
match[5] = 0x09; /* start bit = 1, mode2 = 0 */ |
|
mask[5] = 0x0F; |
|
|
|
rc6_csl = 44; |
|
proto = IR_PROTOCOL_RC6; |
|
break; |
|
|
|
case RC_PROTO_RC6_6A_24: |
|
case RC_PROTO_RC6_6A_32: |
|
case RC_PROTO_RC6_MCE: |
|
i = 0; |
|
|
|
/* Command */ |
|
match[i] = wbcir_to_rc6cells(wake_sc >> 0); |
|
mask[i++] = wbcir_to_rc6cells(mask_sc >> 0); |
|
match[i] = wbcir_to_rc6cells(wake_sc >> 4); |
|
mask[i++] = wbcir_to_rc6cells(mask_sc >> 4); |
|
|
|
/* Address + Toggle */ |
|
match[i] = wbcir_to_rc6cells(wake_sc >> 8); |
|
mask[i++] = wbcir_to_rc6cells(mask_sc >> 8); |
|
match[i] = wbcir_to_rc6cells(wake_sc >> 12); |
|
mask[i++] = wbcir_to_rc6cells(mask_sc >> 12); |
|
|
|
/* Customer bits 7 - 0 */ |
|
match[i] = wbcir_to_rc6cells(wake_sc >> 16); |
|
mask[i++] = wbcir_to_rc6cells(mask_sc >> 16); |
|
|
|
if (rc->wakeup_protocol == RC_PROTO_RC6_6A_20) { |
|
rc6_csl = 52; |
|
} else { |
|
match[i] = wbcir_to_rc6cells(wake_sc >> 20); |
|
mask[i++] = wbcir_to_rc6cells(mask_sc >> 20); |
|
|
|
if (rc->wakeup_protocol == RC_PROTO_RC6_6A_24) { |
|
rc6_csl = 60; |
|
} else { |
|
/* Customer range bit and bits 15 - 8 */ |
|
match[i] = wbcir_to_rc6cells(wake_sc >> 24); |
|
mask[i++] = wbcir_to_rc6cells(mask_sc >> 24); |
|
match[i] = wbcir_to_rc6cells(wake_sc >> 28); |
|
mask[i++] = wbcir_to_rc6cells(mask_sc >> 28); |
|
rc6_csl = 76; |
|
} |
|
} |
|
|
|
/* Header */ |
|
match[i] = 0x93; /* mode1 = mode0 = 1, submode = 0 */ |
|
mask[i++] = 0xFF; |
|
match[i] = 0x0A; /* start bit = 1, mode2 = 1 */ |
|
mask[i++] = 0x0F; |
|
proto = IR_PROTOCOL_RC6; |
|
break; |
|
default: |
|
do_wake = false; |
|
break; |
|
} |
|
|
|
finish: |
|
if (do_wake) { |
|
/* Set compare and compare mask */ |
|
wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX, |
|
WBCIR_REGSEL_COMPARE | WBCIR_REG_ADDR0, |
|
0x3F); |
|
outsb(data->wbase + WBCIR_REG_WCEIR_DATA, match, 11); |
|
wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX, |
|
WBCIR_REGSEL_MASK | WBCIR_REG_ADDR0, |
|
0x3F); |
|
outsb(data->wbase + WBCIR_REG_WCEIR_DATA, mask, 11); |
|
|
|
/* RC6 Compare String Len */ |
|
outb(rc6_csl, data->wbase + WBCIR_REG_WCEIR_CSL); |
|
|
|
/* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ |
|
wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); |
|
|
|
/* Clear BUFF_EN, Clear END_EN, Set MATCH_EN */ |
|
wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x01, 0x07); |
|
|
|
/* Set CEIR_EN */ |
|
wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, |
|
(proto << 4) | 0x01, 0x31); |
|
|
|
} else { |
|
/* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */ |
|
wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); |
|
|
|
/* Clear CEIR_EN */ |
|
wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01); |
|
} |
|
|
|
/* |
|
* ACPI will set the HW disable bit for SP3 which means that the |
|
* output signals are left in an undefined state which may cause |
|
* spurious interrupts which we need to ignore until the hardware |
|
* is reinitialized. |
|
*/ |
|
wbcir_set_irqmask(data, WBCIR_IRQ_NONE); |
|
disable_irq(data->irq); |
|
} |
|
|
|
/* |
|
* Wakeup handling is done on shutdown. |
|
*/ |
|
static int |
|
wbcir_set_wakeup_filter(struct rc_dev *rc, struct rc_scancode_filter *filter) |
|
{ |
|
return 0; |
|
} |
|
|
|
static int |
|
wbcir_suspend(struct pnp_dev *device, pm_message_t state) |
|
{ |
|
struct wbcir_data *data = pnp_get_drvdata(device); |
|
led_classdev_suspend(&data->led); |
|
wbcir_shutdown(device); |
|
return 0; |
|
} |
|
|
|
static void |
|
wbcir_init_hw(struct wbcir_data *data) |
|
{ |
|
/* Disable interrupts */ |
|
wbcir_set_irqmask(data, WBCIR_IRQ_NONE); |
|
|
|
/* Set RX_INV, Clear CEIR_EN (needed for the led) */ |
|
wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, invert ? 8 : 0, 0x09); |
|
|
|
/* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ |
|
wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); |
|
|
|
/* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */ |
|
wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); |
|
|
|
/* Set RC5 cell time to correspond to 36 kHz */ |
|
wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CFG1, 0x4A, 0x7F); |
|
|
|
/* Set IRTX_INV */ |
|
if (invert) |
|
outb(WBCIR_IRTX_INV, data->ebase + WBCIR_REG_ECEIR_CCTL); |
|
else |
|
outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL); |
|
|
|
/* |
|
* Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1, |
|
* set SP3_IRRX_SW to binary 01, helpfully not documented |
|
*/ |
|
outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS); |
|
data->txmask = 0x1; |
|
|
|
/* Enable extended mode */ |
|
wbcir_select_bank(data, WBCIR_BANK_2); |
|
outb(WBCIR_EXT_ENABLE, data->sbase + WBCIR_REG_SP3_EXCR1); |
|
|
|
/* |
|
* Configure baud generator, IR data will be sampled at |
|
* a bitrate of: (24Mhz * prescaler) / (divisor * 16). |
|
* |
|
* The ECIR registers include a flag to change the |
|
* 24Mhz clock freq to 48Mhz. |
|
* |
|
* It's not documented in the specs, but fifo levels |
|
* other than 16 seems to be unsupported. |
|
*/ |
|
|
|
/* prescaler 1.0, tx/rx fifo lvl 16 */ |
|
outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2); |
|
|
|
/* Set baud divisor to sample every 10 us */ |
|
outb(0x0f, data->sbase + WBCIR_REG_SP3_BGDL); |
|
outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH); |
|
|
|
/* Set CEIR mode */ |
|
wbcir_select_bank(data, WBCIR_BANK_0); |
|
outb(0xC0, data->sbase + WBCIR_REG_SP3_MCR); |
|
inb(data->sbase + WBCIR_REG_SP3_LSR); /* Clear LSR */ |
|
inb(data->sbase + WBCIR_REG_SP3_MSR); /* Clear MSR */ |
|
|
|
/* Disable RX demod, enable run-length enc/dec, set freq span */ |
|
wbcir_select_bank(data, WBCIR_BANK_7); |
|
outb(0x90, data->sbase + WBCIR_REG_SP3_RCCFG); |
|
|
|
/* Disable timer */ |
|
wbcir_select_bank(data, WBCIR_BANK_4); |
|
outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR1); |
|
|
|
/* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */ |
|
wbcir_select_bank(data, WBCIR_BANK_5); |
|
outb(txandrx ? 0x03 : 0x02, data->sbase + WBCIR_REG_SP3_IRCR2); |
|
|
|
/* Disable CRC */ |
|
wbcir_select_bank(data, WBCIR_BANK_6); |
|
outb(0x20, data->sbase + WBCIR_REG_SP3_IRCR3); |
|
|
|
/* Set RX demodulation freq, not really used */ |
|
wbcir_select_bank(data, WBCIR_BANK_7); |
|
outb(0xF2, data->sbase + WBCIR_REG_SP3_IRRXDC); |
|
|
|
/* Set TX modulation, 36kHz, 7us pulse width */ |
|
outb(0x69, data->sbase + WBCIR_REG_SP3_IRTXMC); |
|
data->txcarrier = 36000; |
|
|
|
/* Set invert and pin direction */ |
|
if (invert) |
|
outb(0x10, data->sbase + WBCIR_REG_SP3_IRCFG4); |
|
else |
|
outb(0x00, data->sbase + WBCIR_REG_SP3_IRCFG4); |
|
|
|
/* Set FIFO thresholds (RX = 8, TX = 3), reset RX/TX */ |
|
wbcir_select_bank(data, WBCIR_BANK_0); |
|
outb(0x97, data->sbase + WBCIR_REG_SP3_FCR); |
|
|
|
/* Clear AUX status bits */ |
|
outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR); |
|
|
|
/* Clear RX state */ |
|
data->rxstate = WBCIR_RXSTATE_INACTIVE; |
|
wbcir_idle_rx(data->dev, true); |
|
|
|
/* Clear TX state */ |
|
if (data->txstate == WBCIR_TXSTATE_ACTIVE) { |
|
kfree(data->txbuf); |
|
data->txbuf = NULL; |
|
data->txstate = WBCIR_TXSTATE_INACTIVE; |
|
} |
|
|
|
/* Enable interrupts */ |
|
wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR); |
|
} |
|
|
|
static int |
|
wbcir_resume(struct pnp_dev *device) |
|
{ |
|
struct wbcir_data *data = pnp_get_drvdata(device); |
|
|
|
wbcir_init_hw(data); |
|
ir_raw_event_reset(data->dev); |
|
enable_irq(data->irq); |
|
led_classdev_resume(&data->led); |
|
|
|
return 0; |
|
} |
|
|
|
static int |
|
wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id) |
|
{ |
|
struct device *dev = &device->dev; |
|
struct wbcir_data *data; |
|
int err; |
|
|
|
if (!(pnp_port_len(device, 0) == EHFUNC_IOMEM_LEN && |
|
pnp_port_len(device, 1) == WAKEUP_IOMEM_LEN && |
|
pnp_port_len(device, 2) == SP_IOMEM_LEN)) { |
|
dev_err(dev, "Invalid resources\n"); |
|
return -ENODEV; |
|
} |
|
|
|
data = kzalloc(sizeof(*data), GFP_KERNEL); |
|
if (!data) { |
|
err = -ENOMEM; |
|
goto exit; |
|
} |
|
|
|
pnp_set_drvdata(device, data); |
|
|
|
spin_lock_init(&data->spinlock); |
|
data->ebase = pnp_port_start(device, 0); |
|
data->wbase = pnp_port_start(device, 1); |
|
data->sbase = pnp_port_start(device, 2); |
|
data->irq = pnp_irq(device, 0); |
|
|
|
if (data->wbase == 0 || data->ebase == 0 || |
|
data->sbase == 0 || data->irq == -1) { |
|
err = -ENODEV; |
|
dev_err(dev, "Invalid resources\n"); |
|
goto exit_free_data; |
|
} |
|
|
|
dev_dbg(&device->dev, "Found device (w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n", |
|
data->wbase, data->ebase, data->sbase, data->irq); |
|
|
|
data->led.name = "cir::activity"; |
|
data->led.default_trigger = "rc-feedback"; |
|
data->led.brightness_set = wbcir_led_brightness_set; |
|
data->led.brightness_get = wbcir_led_brightness_get; |
|
err = led_classdev_register(&device->dev, &data->led); |
|
if (err) |
|
goto exit_free_data; |
|
|
|
data->dev = rc_allocate_device(RC_DRIVER_IR_RAW); |
|
if (!data->dev) { |
|
err = -ENOMEM; |
|
goto exit_unregister_led; |
|
} |
|
|
|
data->dev->driver_name = DRVNAME; |
|
data->dev->device_name = WBCIR_NAME; |
|
data->dev->input_phys = "wbcir/cir0"; |
|
data->dev->input_id.bustype = BUS_HOST; |
|
data->dev->input_id.vendor = PCI_VENDOR_ID_WINBOND; |
|
data->dev->input_id.product = WBCIR_ID_FAMILY; |
|
data->dev->input_id.version = WBCIR_ID_CHIP; |
|
data->dev->map_name = RC_MAP_RC6_MCE; |
|
data->dev->s_idle = wbcir_idle_rx; |
|
data->dev->s_carrier_report = wbcir_set_carrier_report; |
|
data->dev->s_tx_mask = wbcir_txmask; |
|
data->dev->s_tx_carrier = wbcir_txcarrier; |
|
data->dev->tx_ir = wbcir_tx; |
|
data->dev->priv = data; |
|
data->dev->dev.parent = &device->dev; |
|
data->dev->min_timeout = 1; |
|
data->dev->timeout = IR_DEFAULT_TIMEOUT; |
|
data->dev->max_timeout = 10 * IR_DEFAULT_TIMEOUT; |
|
data->dev->rx_resolution = 2; |
|
data->dev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; |
|
data->dev->allowed_wakeup_protocols = RC_PROTO_BIT_NEC | |
|
RC_PROTO_BIT_NECX | RC_PROTO_BIT_NEC32 | RC_PROTO_BIT_RC5 | |
|
RC_PROTO_BIT_RC6_0 | RC_PROTO_BIT_RC6_6A_20 | |
|
RC_PROTO_BIT_RC6_6A_24 | RC_PROTO_BIT_RC6_6A_32 | |
|
RC_PROTO_BIT_RC6_MCE; |
|
data->dev->wakeup_protocol = RC_PROTO_RC6_MCE; |
|
data->dev->scancode_wakeup_filter.data = 0x800f040c; |
|
data->dev->scancode_wakeup_filter.mask = 0xffff7fff; |
|
data->dev->s_wakeup_filter = wbcir_set_wakeup_filter; |
|
|
|
err = rc_register_device(data->dev); |
|
if (err) |
|
goto exit_free_rc; |
|
|
|
if (!request_region(data->wbase, WAKEUP_IOMEM_LEN, DRVNAME)) { |
|
dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", |
|
data->wbase, data->wbase + WAKEUP_IOMEM_LEN - 1); |
|
err = -EBUSY; |
|
goto exit_unregister_device; |
|
} |
|
|
|
if (!request_region(data->ebase, EHFUNC_IOMEM_LEN, DRVNAME)) { |
|
dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", |
|
data->ebase, data->ebase + EHFUNC_IOMEM_LEN - 1); |
|
err = -EBUSY; |
|
goto exit_release_wbase; |
|
} |
|
|
|
if (!request_region(data->sbase, SP_IOMEM_LEN, DRVNAME)) { |
|
dev_err(dev, "Region 0x%lx-0x%lx already in use!\n", |
|
data->sbase, data->sbase + SP_IOMEM_LEN - 1); |
|
err = -EBUSY; |
|
goto exit_release_ebase; |
|
} |
|
|
|
err = request_irq(data->irq, wbcir_irq_handler, |
|
0, DRVNAME, device); |
|
if (err) { |
|
dev_err(dev, "Failed to claim IRQ %u\n", data->irq); |
|
err = -EBUSY; |
|
goto exit_release_sbase; |
|
} |
|
|
|
device_init_wakeup(&device->dev, 1); |
|
|
|
wbcir_init_hw(data); |
|
|
|
return 0; |
|
|
|
exit_release_sbase: |
|
release_region(data->sbase, SP_IOMEM_LEN); |
|
exit_release_ebase: |
|
release_region(data->ebase, EHFUNC_IOMEM_LEN); |
|
exit_release_wbase: |
|
release_region(data->wbase, WAKEUP_IOMEM_LEN); |
|
exit_unregister_device: |
|
rc_unregister_device(data->dev); |
|
data->dev = NULL; |
|
exit_free_rc: |
|
rc_free_device(data->dev); |
|
exit_unregister_led: |
|
led_classdev_unregister(&data->led); |
|
exit_free_data: |
|
kfree(data); |
|
pnp_set_drvdata(device, NULL); |
|
exit: |
|
return err; |
|
} |
|
|
|
static void |
|
wbcir_remove(struct pnp_dev *device) |
|
{ |
|
struct wbcir_data *data = pnp_get_drvdata(device); |
|
|
|
/* Disable interrupts */ |
|
wbcir_set_irqmask(data, WBCIR_IRQ_NONE); |
|
free_irq(data->irq, device); |
|
|
|
/* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */ |
|
wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17); |
|
|
|
/* Clear CEIR_EN */ |
|
wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01); |
|
|
|
/* Clear BUFF_EN, END_EN, MATCH_EN */ |
|
wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07); |
|
|
|
rc_unregister_device(data->dev); |
|
|
|
led_classdev_unregister(&data->led); |
|
|
|
/* This is ok since &data->led isn't actually used */ |
|
wbcir_led_brightness_set(&data->led, LED_OFF); |
|
|
|
release_region(data->wbase, WAKEUP_IOMEM_LEN); |
|
release_region(data->ebase, EHFUNC_IOMEM_LEN); |
|
release_region(data->sbase, SP_IOMEM_LEN); |
|
|
|
kfree(data); |
|
|
|
pnp_set_drvdata(device, NULL); |
|
} |
|
|
|
static const struct pnp_device_id wbcir_ids[] = { |
|
{ "WEC1022", 0 }, |
|
{ "", 0 } |
|
}; |
|
MODULE_DEVICE_TABLE(pnp, wbcir_ids); |
|
|
|
static struct pnp_driver wbcir_driver = { |
|
.name = DRVNAME, |
|
.id_table = wbcir_ids, |
|
.probe = wbcir_probe, |
|
.remove = wbcir_remove, |
|
.suspend = wbcir_suspend, |
|
.resume = wbcir_resume, |
|
.shutdown = wbcir_shutdown |
|
}; |
|
|
|
static int __init |
|
wbcir_init(void) |
|
{ |
|
int ret; |
|
|
|
ret = pnp_register_driver(&wbcir_driver); |
|
if (ret) |
|
pr_err("Unable to register driver\n"); |
|
|
|
return ret; |
|
} |
|
|
|
static void __exit |
|
wbcir_exit(void) |
|
{ |
|
pnp_unregister_driver(&wbcir_driver); |
|
} |
|
|
|
module_init(wbcir_init); |
|
module_exit(wbcir_exit); |
|
|
|
MODULE_AUTHOR("David Härdeman <[email protected]>"); |
|
MODULE_DESCRIPTION("Winbond SuperI/O Consumer IR Driver"); |
|
MODULE_LICENSE("GPL");
|
|
|