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355 lines
9.5 KiB
355 lines
9.5 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* ispcsiphy.c |
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* |
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* TI OMAP3 ISP - CSI PHY module |
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* |
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* Copyright (C) 2010 Nokia Corporation |
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* Copyright (C) 2009 Texas Instruments, Inc. |
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* |
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* Contacts: Laurent Pinchart <[email protected]> |
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* Sakari Ailus <[email protected]> |
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*/ |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/regmap.h> |
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#include <linux/regulator/consumer.h> |
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#include "isp.h" |
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#include "ispreg.h" |
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#include "ispcsiphy.h" |
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static void csiphy_routing_cfg_3630(struct isp_csiphy *phy, |
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enum isp_interface_type iface, |
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bool ccp2_strobe) |
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{ |
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u32 reg; |
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u32 shift, mode; |
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regmap_read(phy->isp->syscon, phy->isp->syscon_offset, ®); |
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switch (iface) { |
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default: |
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/* Should not happen in practice, but let's keep the compiler happy. */ |
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case ISP_INTERFACE_CCP2B_PHY1: |
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reg &= ~OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2; |
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shift = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY1_SHIFT; |
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break; |
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case ISP_INTERFACE_CSI2C_PHY1: |
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shift = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY1_SHIFT; |
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mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY; |
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break; |
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case ISP_INTERFACE_CCP2B_PHY2: |
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reg |= OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2; |
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shift = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY2_SHIFT; |
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break; |
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case ISP_INTERFACE_CSI2A_PHY2: |
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shift = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY2_SHIFT; |
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mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY; |
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break; |
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} |
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/* Select data/clock or data/strobe mode for CCP2 */ |
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if (iface == ISP_INTERFACE_CCP2B_PHY1 || |
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iface == ISP_INTERFACE_CCP2B_PHY2) { |
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if (ccp2_strobe) |
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mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_STROBE; |
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else |
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mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_CLOCK; |
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} |
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reg &= ~(OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_MASK << shift); |
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reg |= mode << shift; |
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regmap_write(phy->isp->syscon, phy->isp->syscon_offset, reg); |
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} |
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static void csiphy_routing_cfg_3430(struct isp_csiphy *phy, u32 iface, bool on, |
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bool ccp2_strobe) |
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{ |
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u32 csirxfe = OMAP343X_CONTROL_CSIRXFE_PWRDNZ |
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| OMAP343X_CONTROL_CSIRXFE_RESET; |
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/* Only the CCP2B on PHY1 is configurable. */ |
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if (iface != ISP_INTERFACE_CCP2B_PHY1) |
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return; |
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if (!on) { |
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regmap_write(phy->isp->syscon, phy->isp->syscon_offset, 0); |
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return; |
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} |
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if (ccp2_strobe) |
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csirxfe |= OMAP343X_CONTROL_CSIRXFE_SELFORM; |
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regmap_write(phy->isp->syscon, phy->isp->syscon_offset, csirxfe); |
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} |
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/* |
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* Configure OMAP 3 CSI PHY routing. |
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* @phy: relevant phy device |
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* @iface: ISP_INTERFACE_* |
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* @on: power on or off |
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* @ccp2_strobe: false: data/clock, true: data/strobe |
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* |
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* Note that the underlying routing configuration registers are part of the |
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* control (SCM) register space and part of the CORE power domain on both 3430 |
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* and 3630, so they will not hold their contents in off-mode. This isn't an |
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* issue since the MPU power domain is forced on whilst the ISP is in use. |
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*/ |
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static void csiphy_routing_cfg(struct isp_csiphy *phy, |
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enum isp_interface_type iface, bool on, |
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bool ccp2_strobe) |
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{ |
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if (phy->isp->phy_type == ISP_PHY_TYPE_3630 && on) |
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return csiphy_routing_cfg_3630(phy, iface, ccp2_strobe); |
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if (phy->isp->phy_type == ISP_PHY_TYPE_3430) |
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return csiphy_routing_cfg_3430(phy, iface, on, ccp2_strobe); |
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} |
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/* |
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* csiphy_power_autoswitch_enable |
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* @enable: Sets or clears the autoswitch function enable flag. |
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*/ |
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static void csiphy_power_autoswitch_enable(struct isp_csiphy *phy, bool enable) |
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{ |
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isp_reg_clr_set(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG, |
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ISPCSI2_PHY_CFG_PWR_AUTO, |
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enable ? ISPCSI2_PHY_CFG_PWR_AUTO : 0); |
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} |
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/* |
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* csiphy_set_power |
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* @power: Power state to be set. |
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* |
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* Returns 0 if successful, or -EBUSY if the retry count is exceeded. |
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*/ |
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static int csiphy_set_power(struct isp_csiphy *phy, u32 power) |
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{ |
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u32 reg; |
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u8 retry_count; |
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isp_reg_clr_set(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG, |
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ISPCSI2_PHY_CFG_PWR_CMD_MASK, power); |
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retry_count = 0; |
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do { |
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udelay(50); |
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reg = isp_reg_readl(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG) & |
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ISPCSI2_PHY_CFG_PWR_STATUS_MASK; |
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if (reg != power >> 2) |
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retry_count++; |
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} while ((reg != power >> 2) && (retry_count < 100)); |
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if (retry_count == 100) { |
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dev_err(phy->isp->dev, "CSI2 CIO set power failed!\n"); |
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return -EBUSY; |
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} |
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return 0; |
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} |
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/* |
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* TCLK values are OK at their reset values |
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*/ |
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#define TCLK_TERM 0 |
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#define TCLK_MISS 1 |
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#define TCLK_SETTLE 14 |
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static int omap3isp_csiphy_config(struct isp_csiphy *phy) |
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{ |
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struct isp_pipeline *pipe = to_isp_pipeline(phy->entity); |
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struct isp_bus_cfg *buscfg = v4l2_subdev_to_bus_cfg(pipe->external); |
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struct isp_csiphy_lanes_cfg *lanes; |
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int csi2_ddrclk_khz; |
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unsigned int num_data_lanes, used_lanes = 0; |
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unsigned int i; |
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u32 reg; |
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if (buscfg->interface == ISP_INTERFACE_CCP2B_PHY1 |
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|| buscfg->interface == ISP_INTERFACE_CCP2B_PHY2) { |
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lanes = &buscfg->bus.ccp2.lanecfg; |
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num_data_lanes = 1; |
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} else { |
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lanes = &buscfg->bus.csi2.lanecfg; |
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num_data_lanes = buscfg->bus.csi2.num_data_lanes; |
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} |
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if (num_data_lanes > phy->num_data_lanes) |
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return -EINVAL; |
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/* Clock and data lanes verification */ |
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for (i = 0; i < num_data_lanes; i++) { |
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if (lanes->data[i].pol > 1 || lanes->data[i].pos > 3) |
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return -EINVAL; |
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if (used_lanes & (1 << lanes->data[i].pos)) |
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return -EINVAL; |
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used_lanes |= 1 << lanes->data[i].pos; |
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} |
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if (lanes->clk.pol > 1 || lanes->clk.pos > 3) |
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return -EINVAL; |
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if (lanes->clk.pos == 0 || used_lanes & (1 << lanes->clk.pos)) |
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return -EINVAL; |
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/* |
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* The PHY configuration is lost in off mode, that's not an |
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* issue since the MPU power domain is forced on whilst the |
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* ISP is in use. |
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*/ |
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csiphy_routing_cfg(phy, buscfg->interface, true, |
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buscfg->bus.ccp2.phy_layer); |
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/* DPHY timing configuration */ |
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/* CSI-2 is DDR and we only count used lanes. */ |
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csi2_ddrclk_khz = pipe->external_rate / 1000 |
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/ (2 * hweight32(used_lanes)) * pipe->external_width; |
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reg = isp_reg_readl(phy->isp, phy->phy_regs, ISPCSIPHY_REG0); |
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reg &= ~(ISPCSIPHY_REG0_THS_TERM_MASK | |
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ISPCSIPHY_REG0_THS_SETTLE_MASK); |
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/* THS_TERM: Programmed value = ceil(12.5 ns/DDRClk period) - 1. */ |
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reg |= (DIV_ROUND_UP(25 * csi2_ddrclk_khz, 2000000) - 1) |
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<< ISPCSIPHY_REG0_THS_TERM_SHIFT; |
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/* THS_SETTLE: Programmed value = ceil(90 ns/DDRClk period) + 3. */ |
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reg |= (DIV_ROUND_UP(90 * csi2_ddrclk_khz, 1000000) + 3) |
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<< ISPCSIPHY_REG0_THS_SETTLE_SHIFT; |
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isp_reg_writel(phy->isp, reg, phy->phy_regs, ISPCSIPHY_REG0); |
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reg = isp_reg_readl(phy->isp, phy->phy_regs, ISPCSIPHY_REG1); |
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reg &= ~(ISPCSIPHY_REG1_TCLK_TERM_MASK | |
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ISPCSIPHY_REG1_TCLK_MISS_MASK | |
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ISPCSIPHY_REG1_TCLK_SETTLE_MASK); |
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reg |= TCLK_TERM << ISPCSIPHY_REG1_TCLK_TERM_SHIFT; |
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reg |= TCLK_MISS << ISPCSIPHY_REG1_TCLK_MISS_SHIFT; |
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reg |= TCLK_SETTLE << ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT; |
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isp_reg_writel(phy->isp, reg, phy->phy_regs, ISPCSIPHY_REG1); |
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/* DPHY lane configuration */ |
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reg = isp_reg_readl(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG); |
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for (i = 0; i < num_data_lanes; i++) { |
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reg &= ~(ISPCSI2_PHY_CFG_DATA_POL_MASK(i + 1) | |
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ISPCSI2_PHY_CFG_DATA_POSITION_MASK(i + 1)); |
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reg |= (lanes->data[i].pol << |
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ISPCSI2_PHY_CFG_DATA_POL_SHIFT(i + 1)); |
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reg |= (lanes->data[i].pos << |
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ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(i + 1)); |
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} |
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reg &= ~(ISPCSI2_PHY_CFG_CLOCK_POL_MASK | |
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ISPCSI2_PHY_CFG_CLOCK_POSITION_MASK); |
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reg |= lanes->clk.pol << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT; |
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reg |= lanes->clk.pos << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT; |
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isp_reg_writel(phy->isp, reg, phy->cfg_regs, ISPCSI2_PHY_CFG); |
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return 0; |
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} |
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int omap3isp_csiphy_acquire(struct isp_csiphy *phy, struct media_entity *entity) |
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{ |
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int rval; |
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if (phy->vdd == NULL) { |
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dev_err(phy->isp->dev, |
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"Power regulator for CSI PHY not available\n"); |
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return -ENODEV; |
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} |
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mutex_lock(&phy->mutex); |
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rval = regulator_enable(phy->vdd); |
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if (rval < 0) |
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goto done; |
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rval = omap3isp_csi2_reset(phy->csi2); |
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if (rval < 0) |
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goto done; |
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phy->entity = entity; |
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rval = omap3isp_csiphy_config(phy); |
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if (rval < 0) |
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goto done; |
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if (phy->isp->revision == ISP_REVISION_15_0) { |
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rval = csiphy_set_power(phy, ISPCSI2_PHY_CFG_PWR_CMD_ON); |
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if (rval) { |
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regulator_disable(phy->vdd); |
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goto done; |
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} |
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csiphy_power_autoswitch_enable(phy, true); |
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} |
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done: |
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if (rval < 0) |
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phy->entity = NULL; |
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mutex_unlock(&phy->mutex); |
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return rval; |
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} |
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void omap3isp_csiphy_release(struct isp_csiphy *phy) |
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{ |
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mutex_lock(&phy->mutex); |
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if (phy->entity) { |
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struct isp_pipeline *pipe = to_isp_pipeline(phy->entity); |
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struct isp_bus_cfg *buscfg = |
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v4l2_subdev_to_bus_cfg(pipe->external); |
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csiphy_routing_cfg(phy, buscfg->interface, false, |
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buscfg->bus.ccp2.phy_layer); |
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if (phy->isp->revision == ISP_REVISION_15_0) { |
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csiphy_power_autoswitch_enable(phy, false); |
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csiphy_set_power(phy, ISPCSI2_PHY_CFG_PWR_CMD_OFF); |
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} |
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regulator_disable(phy->vdd); |
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phy->entity = NULL; |
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} |
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mutex_unlock(&phy->mutex); |
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} |
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/* |
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* omap3isp_csiphy_init - Initialize the CSI PHY frontends |
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*/ |
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int omap3isp_csiphy_init(struct isp_device *isp) |
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{ |
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struct isp_csiphy *phy1 = &isp->isp_csiphy1; |
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struct isp_csiphy *phy2 = &isp->isp_csiphy2; |
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phy2->isp = isp; |
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phy2->csi2 = &isp->isp_csi2a; |
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phy2->num_data_lanes = ISP_CSIPHY2_NUM_DATA_LANES; |
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phy2->cfg_regs = OMAP3_ISP_IOMEM_CSI2A_REGS1; |
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phy2->phy_regs = OMAP3_ISP_IOMEM_CSIPHY2; |
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mutex_init(&phy2->mutex); |
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phy1->isp = isp; |
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mutex_init(&phy1->mutex); |
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if (isp->revision == ISP_REVISION_15_0) { |
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phy1->csi2 = &isp->isp_csi2c; |
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phy1->num_data_lanes = ISP_CSIPHY1_NUM_DATA_LANES; |
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phy1->cfg_regs = OMAP3_ISP_IOMEM_CSI2C_REGS1; |
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phy1->phy_regs = OMAP3_ISP_IOMEM_CSIPHY1; |
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} |
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return 0; |
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} |
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void omap3isp_csiphy_cleanup(struct isp_device *isp) |
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{ |
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mutex_destroy(&isp->isp_csiphy1.mutex); |
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mutex_destroy(&isp->isp_csiphy2.mutex); |
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}
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