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155 lines
5.7 KiB
155 lines
5.7 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (C) 2012 Samsung Electronics Co., Ltd. |
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*/ |
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#ifndef FIMC_LITE_REG_H_ |
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#define FIMC_LITE_REG_H_ |
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#include <linux/bitops.h> |
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#include "fimc-lite.h" |
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/* Camera Source size */ |
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#define FLITE_REG_CISRCSIZE 0x00 |
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#define FLITE_REG_CISRCSIZE_ORDER422_IN_YCBYCR (0 << 14) |
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#define FLITE_REG_CISRCSIZE_ORDER422_IN_YCRYCB (1 << 14) |
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#define FLITE_REG_CISRCSIZE_ORDER422_IN_CBYCRY (2 << 14) |
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#define FLITE_REG_CISRCSIZE_ORDER422_IN_CRYCBY (3 << 14) |
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#define FLITE_REG_CISRCSIZE_ORDER422_MASK (0x3 << 14) |
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#define FLITE_REG_CISRCSIZE_SIZE_CAM_MASK (0x3fff << 16 | 0x3fff) |
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/* Global control */ |
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#define FLITE_REG_CIGCTRL 0x04 |
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#define FLITE_REG_CIGCTRL_YUV422_1P (0x1e << 24) |
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#define FLITE_REG_CIGCTRL_RAW8 (0x2a << 24) |
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#define FLITE_REG_CIGCTRL_RAW10 (0x2b << 24) |
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#define FLITE_REG_CIGCTRL_RAW12 (0x2c << 24) |
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#define FLITE_REG_CIGCTRL_RAW14 (0x2d << 24) |
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/* User defined formats. x = 0...15 */ |
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#define FLITE_REG_CIGCTRL_USER(x) ((0x30 + x - 1) << 24) |
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#define FLITE_REG_CIGCTRL_FMT_MASK (0x3f << 24) |
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#define FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE BIT(21) |
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#define FLITE_REG_CIGCTRL_ODMA_DISABLE BIT(20) |
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#define FLITE_REG_CIGCTRL_SWRST_REQ BIT(19) |
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#define FLITE_REG_CIGCTRL_SWRST_RDY BIT(18) |
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#define FLITE_REG_CIGCTRL_SWRST BIT(17) |
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#define FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR BIT(15) |
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#define FLITE_REG_CIGCTRL_INVPOLPCLK BIT(14) |
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#define FLITE_REG_CIGCTRL_INVPOLVSYNC BIT(13) |
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#define FLITE_REG_CIGCTRL_INVPOLHREF BIT(12) |
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/* Interrupts mask bits (1 disables an interrupt) */ |
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#define FLITE_REG_CIGCTRL_IRQ_LASTEN BIT(8) |
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#define FLITE_REG_CIGCTRL_IRQ_ENDEN BIT(7) |
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#define FLITE_REG_CIGCTRL_IRQ_STARTEN BIT(6) |
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#define FLITE_REG_CIGCTRL_IRQ_OVFEN BIT(5) |
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#define FLITE_REG_CIGCTRL_IRQ_DISABLE_MASK (0xf << 5) |
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#define FLITE_REG_CIGCTRL_SELCAM_MIPI BIT(3) |
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/* Image Capture Enable */ |
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#define FLITE_REG_CIIMGCPT 0x08 |
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#define FLITE_REG_CIIMGCPT_IMGCPTEN BIT(31) |
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#define FLITE_REG_CIIMGCPT_CPT_FREN BIT(25) |
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#define FLITE_REG_CIIMGCPT_CPT_MOD_FRCNT (1 << 18) |
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#define FLITE_REG_CIIMGCPT_CPT_MOD_FREN (0 << 18) |
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/* Capture Sequence */ |
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#define FLITE_REG_CICPTSEQ 0x0c |
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/* Camera Window Offset */ |
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#define FLITE_REG_CIWDOFST 0x10 |
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#define FLITE_REG_CIWDOFST_WINOFSEN BIT(31) |
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#define FLITE_REG_CIWDOFST_CLROVIY BIT(31) |
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#define FLITE_REG_CIWDOFST_CLROVFICB BIT(15) |
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#define FLITE_REG_CIWDOFST_CLROVFICR BIT(14) |
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#define FLITE_REG_CIWDOFST_OFST_MASK ((0x1fff << 16) | 0x1fff) |
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/* Camera Window Offset2 */ |
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#define FLITE_REG_CIWDOFST2 0x14 |
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/* Camera Output DMA Format */ |
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#define FLITE_REG_CIODMAFMT 0x18 |
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#define FLITE_REG_CIODMAFMT_RAW_CON BIT(15) |
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#define FLITE_REG_CIODMAFMT_PACK12 BIT(14) |
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#define FLITE_REG_CIODMAFMT_YCBYCR (0 << 4) |
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#define FLITE_REG_CIODMAFMT_YCRYCB (1 << 4) |
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#define FLITE_REG_CIODMAFMT_CBYCRY (2 << 4) |
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#define FLITE_REG_CIODMAFMT_CRYCBY (3 << 4) |
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#define FLITE_REG_CIODMAFMT_YCBCR_ORDER_MASK (0x3 << 4) |
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/* Camera Output Canvas */ |
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#define FLITE_REG_CIOCAN 0x20 |
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#define FLITE_REG_CIOCAN_MASK ((0x3fff << 16) | 0x3fff) |
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/* Camera Output DMA Offset */ |
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#define FLITE_REG_CIOOFF 0x24 |
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#define FLITE_REG_CIOOFF_MASK ((0x3fff << 16) | 0x3fff) |
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/* Camera Output DMA Start Address */ |
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#define FLITE_REG_CIOSA 0x30 |
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/* Camera Status */ |
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#define FLITE_REG_CISTATUS 0x40 |
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#define FLITE_REG_CISTATUS_MIPI_VVALID BIT(22) |
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#define FLITE_REG_CISTATUS_MIPI_HVALID BIT(21) |
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#define FLITE_REG_CISTATUS_MIPI_DVALID BIT(20) |
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#define FLITE_REG_CISTATUS_ITU_VSYNC BIT(14) |
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#define FLITE_REG_CISTATUS_ITU_HREFF BIT(13) |
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#define FLITE_REG_CISTATUS_OVFIY BIT(10) |
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#define FLITE_REG_CISTATUS_OVFICB BIT(9) |
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#define FLITE_REG_CISTATUS_OVFICR BIT(8) |
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#define FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW BIT(7) |
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#define FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND BIT(6) |
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#define FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART BIT(5) |
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#define FLITE_REG_CISTATUS_IRQ_SRC_FRMEND BIT(4) |
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#define FLITE_REG_CISTATUS_IRQ_CAM BIT(0) |
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#define FLITE_REG_CISTATUS_IRQ_MASK (0xf << 4) |
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/* Camera Status2 */ |
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#define FLITE_REG_CISTATUS2 0x44 |
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#define FLITE_REG_CISTATUS2_LASTCAPEND BIT(1) |
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#define FLITE_REG_CISTATUS2_FRMEND BIT(0) |
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/* Qos Threshold */ |
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#define FLITE_REG_CITHOLD 0xf0 |
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#define FLITE_REG_CITHOLD_W_QOS_EN BIT(30) |
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/* Camera General Purpose */ |
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#define FLITE_REG_CIGENERAL 0xfc |
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/* b0: 1 - camera B, 0 - camera A */ |
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#define FLITE_REG_CIGENERAL_CAM_B BIT(0) |
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#define FLITE_REG_CIFCNTSEQ 0x100 |
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#define FLITE_REG_CIOSAN(x) (0x200 + (4 * (x))) |
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/* ---------------------------------------------------------------------------- |
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* Function declarations |
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*/ |
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void flite_hw_reset(struct fimc_lite *dev); |
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void flite_hw_clear_pending_irq(struct fimc_lite *dev); |
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u32 flite_hw_get_interrupt_source(struct fimc_lite *dev); |
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void flite_hw_clear_last_capture_end(struct fimc_lite *dev); |
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void flite_hw_set_interrupt_mask(struct fimc_lite *dev); |
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void flite_hw_capture_start(struct fimc_lite *dev); |
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void flite_hw_capture_stop(struct fimc_lite *dev); |
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void flite_hw_set_camera_bus(struct fimc_lite *dev, |
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struct fimc_source_info *s_info); |
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void flite_hw_set_camera_polarity(struct fimc_lite *dev, |
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struct fimc_source_info *cam); |
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void flite_hw_set_window_offset(struct fimc_lite *dev, struct flite_frame *f); |
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void flite_hw_set_source_format(struct fimc_lite *dev, struct flite_frame *f); |
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void flite_hw_set_output_dma(struct fimc_lite *dev, struct flite_frame *f, |
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bool enable); |
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void flite_hw_set_dma_window(struct fimc_lite *dev, struct flite_frame *f); |
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void flite_hw_set_test_pattern(struct fimc_lite *dev, bool on); |
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void flite_hw_dump_regs(struct fimc_lite *dev, const char *label); |
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void flite_hw_set_dma_buffer(struct fimc_lite *dev, struct flite_buffer *buf); |
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void flite_hw_mask_dma_buffer(struct fimc_lite *dev, u32 index); |
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static inline void flite_hw_set_dma_buf_mask(struct fimc_lite *dev, u32 mask) |
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{ |
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writel(mask, dev->regs + FLITE_REG_CIFCNTSEQ); |
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} |
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#endif /* FIMC_LITE_REG_H */
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