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413 lines
11 KiB
413 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* APM X-Gene SoC RNG Driver |
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* |
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* Copyright (c) 2014, Applied Micro Circuits Corporation |
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* Author: Rameshwar Prasad Sahu <[email protected]> |
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* Shamal Winchurkar <[email protected]> |
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* Feng Kan <[email protected]> |
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*/ |
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#include <linux/acpi.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/hw_random.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/module.h> |
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#include <linux/of_platform.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_address.h> |
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#include <linux/timer.h> |
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#define RNG_MAX_DATUM 4 |
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#define MAX_TRY 100 |
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#define XGENE_RNG_RETRY_COUNT 20 |
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#define XGENE_RNG_RETRY_INTERVAL 10 |
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/* RNG Registers */ |
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#define RNG_INOUT_0 0x00 |
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#define RNG_INTR_STS_ACK 0x10 |
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#define RNG_CONTROL 0x14 |
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#define RNG_CONFIG 0x18 |
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#define RNG_ALARMCNT 0x1c |
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#define RNG_FROENABLE 0x20 |
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#define RNG_FRODETUNE 0x24 |
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#define RNG_ALARMMASK 0x28 |
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#define RNG_ALARMSTOP 0x2c |
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#define RNG_OPTIONS 0x78 |
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#define RNG_EIP_REV 0x7c |
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#define MONOBIT_FAIL_MASK BIT(7) |
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#define POKER_FAIL_MASK BIT(6) |
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#define LONG_RUN_FAIL_MASK BIT(5) |
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#define RUN_FAIL_MASK BIT(4) |
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#define NOISE_FAIL_MASK BIT(3) |
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#define STUCK_OUT_MASK BIT(2) |
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#define SHUTDOWN_OFLO_MASK BIT(1) |
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#define READY_MASK BIT(0) |
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#define MAJOR_HW_REV_RD(src) (((src) & 0x0f000000) >> 24) |
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#define MINOR_HW_REV_RD(src) (((src) & 0x00f00000) >> 20) |
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#define HW_PATCH_LEVEL_RD(src) (((src) & 0x000f0000) >> 16) |
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#define MAX_REFILL_CYCLES_SET(dst, src) \ |
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((dst & ~0xffff0000) | (((u32)src << 16) & 0xffff0000)) |
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#define MIN_REFILL_CYCLES_SET(dst, src) \ |
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((dst & ~0x000000ff) | (((u32)src) & 0x000000ff)) |
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#define ALARM_THRESHOLD_SET(dst, src) \ |
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((dst & ~0x000000ff) | (((u32)src) & 0x000000ff)) |
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#define ENABLE_RNG_SET(dst, src) \ |
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((dst & ~BIT(10)) | (((u32)src << 10) & BIT(10))) |
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#define REGSPEC_TEST_MODE_SET(dst, src) \ |
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((dst & ~BIT(8)) | (((u32)src << 8) & BIT(8))) |
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#define MONOBIT_FAIL_MASK_SET(dst, src) \ |
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((dst & ~BIT(7)) | (((u32)src << 7) & BIT(7))) |
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#define POKER_FAIL_MASK_SET(dst, src) \ |
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((dst & ~BIT(6)) | (((u32)src << 6) & BIT(6))) |
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#define LONG_RUN_FAIL_MASK_SET(dst, src) \ |
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((dst & ~BIT(5)) | (((u32)src << 5) & BIT(5))) |
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#define RUN_FAIL_MASK_SET(dst, src) \ |
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((dst & ~BIT(4)) | (((u32)src << 4) & BIT(4))) |
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#define NOISE_FAIL_MASK_SET(dst, src) \ |
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((dst & ~BIT(3)) | (((u32)src << 3) & BIT(3))) |
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#define STUCK_OUT_MASK_SET(dst, src) \ |
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((dst & ~BIT(2)) | (((u32)src << 2) & BIT(2))) |
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#define SHUTDOWN_OFLO_MASK_SET(dst, src) \ |
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((dst & ~BIT(1)) | (((u32)src << 1) & BIT(1))) |
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struct xgene_rng_dev { |
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u32 irq; |
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void __iomem *csr_base; |
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u32 revision; |
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u32 datum_size; |
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u32 failure_cnt; /* Failure count last minute */ |
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unsigned long failure_ts;/* First failure timestamp */ |
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struct timer_list failure_timer; |
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struct device *dev; |
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struct clk *clk; |
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}; |
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static void xgene_rng_expired_timer(struct timer_list *t) |
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{ |
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struct xgene_rng_dev *ctx = from_timer(ctx, t, failure_timer); |
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/* Clear failure counter as timer expired */ |
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disable_irq(ctx->irq); |
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ctx->failure_cnt = 0; |
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del_timer(&ctx->failure_timer); |
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enable_irq(ctx->irq); |
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} |
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static void xgene_rng_start_timer(struct xgene_rng_dev *ctx) |
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{ |
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ctx->failure_timer.expires = jiffies + 120 * HZ; |
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add_timer(&ctx->failure_timer); |
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} |
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/* |
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* Initialize or reinit free running oscillators (FROs) |
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*/ |
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static void xgene_rng_init_fro(struct xgene_rng_dev *ctx, u32 fro_val) |
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{ |
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writel(fro_val, ctx->csr_base + RNG_FRODETUNE); |
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writel(0x00000000, ctx->csr_base + RNG_ALARMMASK); |
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writel(0x00000000, ctx->csr_base + RNG_ALARMSTOP); |
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writel(0xFFFFFFFF, ctx->csr_base + RNG_FROENABLE); |
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} |
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static void xgene_rng_chk_overflow(struct xgene_rng_dev *ctx) |
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{ |
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u32 val; |
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val = readl(ctx->csr_base + RNG_INTR_STS_ACK); |
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if (val & MONOBIT_FAIL_MASK) |
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/* |
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* LFSR detected an out-of-bounds number of 1s after |
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* checking 20,000 bits (test T1 as specified in the |
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* AIS-31 standard) |
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*/ |
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dev_err(ctx->dev, "test monobit failure error 0x%08X\n", val); |
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if (val & POKER_FAIL_MASK) |
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/* |
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* LFSR detected an out-of-bounds value in at least one |
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* of the 16 poker_count_X counters or an out of bounds sum |
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* of squares value after checking 20,000 bits (test T2 as |
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* specified in the AIS-31 standard) |
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*/ |
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dev_err(ctx->dev, "test poker failure error 0x%08X\n", val); |
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if (val & LONG_RUN_FAIL_MASK) |
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/* |
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* LFSR detected a sequence of 34 identical bits |
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* (test T4 as specified in the AIS-31 standard) |
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*/ |
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dev_err(ctx->dev, "test long run failure error 0x%08X\n", val); |
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if (val & RUN_FAIL_MASK) |
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/* |
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* LFSR detected an outof-bounds value for at least one |
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* of the running counters after checking 20,000 bits |
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* (test T3 as specified in the AIS-31 standard) |
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*/ |
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dev_err(ctx->dev, "test run failure error 0x%08X\n", val); |
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if (val & NOISE_FAIL_MASK) |
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/* LFSR detected a sequence of 48 identical bits */ |
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dev_err(ctx->dev, "noise failure error 0x%08X\n", val); |
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if (val & STUCK_OUT_MASK) |
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/* |
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* Detected output data registers generated same value twice |
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* in a row |
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*/ |
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dev_err(ctx->dev, "stuck out failure error 0x%08X\n", val); |
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if (val & SHUTDOWN_OFLO_MASK) { |
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u32 frostopped; |
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/* FROs shut down after a second error event. Try recover. */ |
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if (++ctx->failure_cnt == 1) { |
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/* 1st time, just recover */ |
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ctx->failure_ts = jiffies; |
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frostopped = readl(ctx->csr_base + RNG_ALARMSTOP); |
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xgene_rng_init_fro(ctx, frostopped); |
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/* |
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* We must start a timer to clear out this error |
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* in case the system timer wrap around |
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*/ |
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xgene_rng_start_timer(ctx); |
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} else { |
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/* 2nd time failure in lesser than 1 minute? */ |
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if (time_after(ctx->failure_ts + 60 * HZ, jiffies)) { |
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dev_err(ctx->dev, |
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"FRO shutdown failure error 0x%08X\n", |
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val); |
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} else { |
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/* 2nd time failure after 1 minutes, recover */ |
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ctx->failure_ts = jiffies; |
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ctx->failure_cnt = 1; |
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/* |
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* We must start a timer to clear out this |
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* error in case the system timer wrap |
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* around |
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*/ |
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xgene_rng_start_timer(ctx); |
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} |
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frostopped = readl(ctx->csr_base + RNG_ALARMSTOP); |
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xgene_rng_init_fro(ctx, frostopped); |
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} |
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} |
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/* Clear them all */ |
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writel(val, ctx->csr_base + RNG_INTR_STS_ACK); |
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} |
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static irqreturn_t xgene_rng_irq_handler(int irq, void *id) |
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{ |
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struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) id; |
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/* RNG Alarm Counter overflow */ |
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xgene_rng_chk_overflow(ctx); |
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return IRQ_HANDLED; |
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} |
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static int xgene_rng_data_present(struct hwrng *rng, int wait) |
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{ |
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struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv; |
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u32 i, val = 0; |
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for (i = 0; i < XGENE_RNG_RETRY_COUNT; i++) { |
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val = readl(ctx->csr_base + RNG_INTR_STS_ACK); |
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if ((val & READY_MASK) || !wait) |
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break; |
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udelay(XGENE_RNG_RETRY_INTERVAL); |
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} |
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return (val & READY_MASK); |
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} |
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static int xgene_rng_data_read(struct hwrng *rng, u32 *data) |
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{ |
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struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv; |
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int i; |
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for (i = 0; i < ctx->datum_size; i++) |
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data[i] = readl(ctx->csr_base + RNG_INOUT_0 + i * 4); |
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/* Clear ready bit to start next transaction */ |
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writel(READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK); |
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return ctx->datum_size << 2; |
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} |
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static void xgene_rng_init_internal(struct xgene_rng_dev *ctx) |
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{ |
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u32 val; |
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writel(0x00000000, ctx->csr_base + RNG_CONTROL); |
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val = MAX_REFILL_CYCLES_SET(0, 10); |
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val = MIN_REFILL_CYCLES_SET(val, 10); |
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writel(val, ctx->csr_base + RNG_CONFIG); |
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val = ALARM_THRESHOLD_SET(0, 0xFF); |
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writel(val, ctx->csr_base + RNG_ALARMCNT); |
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xgene_rng_init_fro(ctx, 0); |
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writel(MONOBIT_FAIL_MASK | |
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POKER_FAIL_MASK | |
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LONG_RUN_FAIL_MASK | |
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RUN_FAIL_MASK | |
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NOISE_FAIL_MASK | |
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STUCK_OUT_MASK | |
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SHUTDOWN_OFLO_MASK | |
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READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK); |
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val = ENABLE_RNG_SET(0, 1); |
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val = MONOBIT_FAIL_MASK_SET(val, 1); |
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val = POKER_FAIL_MASK_SET(val, 1); |
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val = LONG_RUN_FAIL_MASK_SET(val, 1); |
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val = RUN_FAIL_MASK_SET(val, 1); |
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val = NOISE_FAIL_MASK_SET(val, 1); |
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val = STUCK_OUT_MASK_SET(val, 1); |
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val = SHUTDOWN_OFLO_MASK_SET(val, 1); |
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writel(val, ctx->csr_base + RNG_CONTROL); |
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} |
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static int xgene_rng_init(struct hwrng *rng) |
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{ |
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struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv; |
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ctx->failure_cnt = 0; |
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timer_setup(&ctx->failure_timer, xgene_rng_expired_timer, 0); |
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ctx->revision = readl(ctx->csr_base + RNG_EIP_REV); |
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dev_dbg(ctx->dev, "Rev %d.%d.%d\n", |
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MAJOR_HW_REV_RD(ctx->revision), |
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MINOR_HW_REV_RD(ctx->revision), |
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HW_PATCH_LEVEL_RD(ctx->revision)); |
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dev_dbg(ctx->dev, "Options 0x%08X", |
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readl(ctx->csr_base + RNG_OPTIONS)); |
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xgene_rng_init_internal(ctx); |
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ctx->datum_size = RNG_MAX_DATUM; |
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return 0; |
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} |
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#ifdef CONFIG_ACPI |
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static const struct acpi_device_id xgene_rng_acpi_match[] = { |
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{ "APMC0D18", }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(acpi, xgene_rng_acpi_match); |
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#endif |
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static struct hwrng xgene_rng_func = { |
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.name = "xgene-rng", |
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.init = xgene_rng_init, |
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.data_present = xgene_rng_data_present, |
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.data_read = xgene_rng_data_read, |
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}; |
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static int xgene_rng_probe(struct platform_device *pdev) |
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{ |
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struct xgene_rng_dev *ctx; |
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int rc = 0; |
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ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); |
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if (!ctx) |
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return -ENOMEM; |
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ctx->dev = &pdev->dev; |
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platform_set_drvdata(pdev, ctx); |
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ctx->csr_base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(ctx->csr_base)) |
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return PTR_ERR(ctx->csr_base); |
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rc = platform_get_irq(pdev, 0); |
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if (rc < 0) |
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return rc; |
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ctx->irq = rc; |
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dev_dbg(&pdev->dev, "APM X-Gene RNG BASE %p ALARM IRQ %d", |
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ctx->csr_base, ctx->irq); |
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rc = devm_request_irq(&pdev->dev, ctx->irq, xgene_rng_irq_handler, 0, |
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dev_name(&pdev->dev), ctx); |
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if (rc) { |
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dev_err(&pdev->dev, "Could not request RNG alarm IRQ\n"); |
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return rc; |
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} |
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/* Enable IP clock */ |
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ctx->clk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(ctx->clk)) { |
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dev_warn(&pdev->dev, "Couldn't get the clock for RNG\n"); |
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} else { |
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rc = clk_prepare_enable(ctx->clk); |
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if (rc) { |
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dev_warn(&pdev->dev, |
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"clock prepare enable failed for RNG"); |
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return rc; |
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} |
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} |
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xgene_rng_func.priv = (unsigned long) ctx; |
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rc = devm_hwrng_register(&pdev->dev, &xgene_rng_func); |
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if (rc) { |
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dev_err(&pdev->dev, "RNG registering failed error %d\n", rc); |
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if (!IS_ERR(ctx->clk)) |
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clk_disable_unprepare(ctx->clk); |
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return rc; |
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} |
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rc = device_init_wakeup(&pdev->dev, 1); |
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if (rc) { |
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dev_err(&pdev->dev, "RNG device_init_wakeup failed error %d\n", |
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rc); |
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if (!IS_ERR(ctx->clk)) |
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clk_disable_unprepare(ctx->clk); |
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return rc; |
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} |
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return 0; |
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} |
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static int xgene_rng_remove(struct platform_device *pdev) |
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{ |
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struct xgene_rng_dev *ctx = platform_get_drvdata(pdev); |
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int rc; |
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rc = device_init_wakeup(&pdev->dev, 0); |
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if (rc) |
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dev_err(&pdev->dev, "RNG init wakeup failed error %d\n", rc); |
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if (!IS_ERR(ctx->clk)) |
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clk_disable_unprepare(ctx->clk); |
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return rc; |
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} |
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static const struct of_device_id xgene_rng_of_match[] = { |
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{ .compatible = "apm,xgene-rng" }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, xgene_rng_of_match); |
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static struct platform_driver xgene_rng_driver = { |
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.probe = xgene_rng_probe, |
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.remove = xgene_rng_remove, |
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.driver = { |
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.name = "xgene-rng", |
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.of_match_table = xgene_rng_of_match, |
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.acpi_match_table = ACPI_PTR(xgene_rng_acpi_match), |
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}, |
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}; |
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module_platform_driver(xgene_rng_driver); |
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MODULE_DESCRIPTION("APM X-Gene RNG driver"); |
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MODULE_LICENSE("GPL");
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