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785 lines
17 KiB
785 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// Register cache access API |
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// |
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// Copyright 2011 Wolfson Microelectronics plc |
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// |
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// Author: Dimitris Papastamos <[email protected]> |
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#include <linux/bsearch.h> |
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#include <linux/device.h> |
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#include <linux/export.h> |
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#include <linux/slab.h> |
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#include <linux/sort.h> |
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#include "trace.h" |
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#include "internal.h" |
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static const struct regcache_ops *cache_types[] = { |
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®cache_rbtree_ops, |
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#if IS_ENABLED(CONFIG_REGCACHE_COMPRESSED) |
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®cache_lzo_ops, |
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#endif |
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®cache_flat_ops, |
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}; |
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static int regcache_hw_init(struct regmap *map) |
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{ |
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int i, j; |
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int ret; |
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int count; |
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unsigned int reg, val; |
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void *tmp_buf; |
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if (!map->num_reg_defaults_raw) |
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return -EINVAL; |
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/* calculate the size of reg_defaults */ |
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for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++) |
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if (regmap_readable(map, i * map->reg_stride) && |
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!regmap_volatile(map, i * map->reg_stride)) |
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count++; |
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/* all registers are unreadable or volatile, so just bypass */ |
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if (!count) { |
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map->cache_bypass = true; |
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return 0; |
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} |
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map->num_reg_defaults = count; |
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map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default), |
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GFP_KERNEL); |
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if (!map->reg_defaults) |
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return -ENOMEM; |
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if (!map->reg_defaults_raw) { |
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bool cache_bypass = map->cache_bypass; |
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dev_warn(map->dev, "No cache defaults, reading back from HW\n"); |
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/* Bypass the cache access till data read from HW */ |
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map->cache_bypass = true; |
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tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL); |
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if (!tmp_buf) { |
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ret = -ENOMEM; |
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goto err_free; |
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} |
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ret = regmap_raw_read(map, 0, tmp_buf, |
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map->cache_size_raw); |
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map->cache_bypass = cache_bypass; |
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if (ret == 0) { |
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map->reg_defaults_raw = tmp_buf; |
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map->cache_free = true; |
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} else { |
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kfree(tmp_buf); |
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} |
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} |
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/* fill the reg_defaults */ |
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for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) { |
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reg = i * map->reg_stride; |
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if (!regmap_readable(map, reg)) |
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continue; |
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if (regmap_volatile(map, reg)) |
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continue; |
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if (map->reg_defaults_raw) { |
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val = regcache_get_val(map, map->reg_defaults_raw, i); |
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} else { |
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bool cache_bypass = map->cache_bypass; |
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map->cache_bypass = true; |
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ret = regmap_read(map, reg, &val); |
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map->cache_bypass = cache_bypass; |
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if (ret != 0) { |
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dev_err(map->dev, "Failed to read %d: %d\n", |
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reg, ret); |
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goto err_free; |
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} |
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} |
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map->reg_defaults[j].reg = reg; |
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map->reg_defaults[j].def = val; |
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j++; |
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} |
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return 0; |
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err_free: |
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kfree(map->reg_defaults); |
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return ret; |
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} |
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int regcache_init(struct regmap *map, const struct regmap_config *config) |
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{ |
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int ret; |
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int i; |
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void *tmp_buf; |
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if (map->cache_type == REGCACHE_NONE) { |
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if (config->reg_defaults || config->num_reg_defaults_raw) |
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dev_warn(map->dev, |
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"No cache used with register defaults set!\n"); |
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map->cache_bypass = true; |
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return 0; |
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} |
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if (config->reg_defaults && !config->num_reg_defaults) { |
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dev_err(map->dev, |
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"Register defaults are set without the number!\n"); |
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return -EINVAL; |
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} |
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for (i = 0; i < config->num_reg_defaults; i++) |
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if (config->reg_defaults[i].reg % map->reg_stride) |
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return -EINVAL; |
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for (i = 0; i < ARRAY_SIZE(cache_types); i++) |
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if (cache_types[i]->type == map->cache_type) |
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break; |
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if (i == ARRAY_SIZE(cache_types)) { |
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dev_err(map->dev, "Could not match compress type: %d\n", |
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map->cache_type); |
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return -EINVAL; |
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} |
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map->num_reg_defaults = config->num_reg_defaults; |
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map->num_reg_defaults_raw = config->num_reg_defaults_raw; |
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map->reg_defaults_raw = config->reg_defaults_raw; |
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map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8); |
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map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw; |
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map->cache = NULL; |
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map->cache_ops = cache_types[i]; |
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if (!map->cache_ops->read || |
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!map->cache_ops->write || |
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!map->cache_ops->name) |
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return -EINVAL; |
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/* We still need to ensure that the reg_defaults |
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* won't vanish from under us. We'll need to make |
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* a copy of it. |
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*/ |
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if (config->reg_defaults) { |
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tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults * |
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sizeof(struct reg_default), GFP_KERNEL); |
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if (!tmp_buf) |
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return -ENOMEM; |
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map->reg_defaults = tmp_buf; |
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} else if (map->num_reg_defaults_raw) { |
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/* Some devices such as PMICs don't have cache defaults, |
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* we cope with this by reading back the HW registers and |
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* crafting the cache defaults by hand. |
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*/ |
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ret = regcache_hw_init(map); |
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if (ret < 0) |
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return ret; |
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if (map->cache_bypass) |
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return 0; |
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} |
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if (!map->max_register) |
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map->max_register = map->num_reg_defaults_raw; |
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if (map->cache_ops->init) { |
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dev_dbg(map->dev, "Initializing %s cache\n", |
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map->cache_ops->name); |
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ret = map->cache_ops->init(map); |
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if (ret) |
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goto err_free; |
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} |
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return 0; |
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err_free: |
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kfree(map->reg_defaults); |
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if (map->cache_free) |
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kfree(map->reg_defaults_raw); |
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return ret; |
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} |
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void regcache_exit(struct regmap *map) |
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{ |
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if (map->cache_type == REGCACHE_NONE) |
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return; |
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BUG_ON(!map->cache_ops); |
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kfree(map->reg_defaults); |
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if (map->cache_free) |
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kfree(map->reg_defaults_raw); |
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if (map->cache_ops->exit) { |
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dev_dbg(map->dev, "Destroying %s cache\n", |
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map->cache_ops->name); |
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map->cache_ops->exit(map); |
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} |
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} |
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/** |
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* regcache_read - Fetch the value of a given register from the cache. |
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* |
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* @map: map to configure. |
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* @reg: The register index. |
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* @value: The value to be returned. |
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* |
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* Return a negative value on failure, 0 on success. |
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*/ |
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int regcache_read(struct regmap *map, |
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unsigned int reg, unsigned int *value) |
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{ |
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int ret; |
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if (map->cache_type == REGCACHE_NONE) |
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return -ENOSYS; |
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BUG_ON(!map->cache_ops); |
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if (!regmap_volatile(map, reg)) { |
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ret = map->cache_ops->read(map, reg, value); |
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if (ret == 0) |
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trace_regmap_reg_read_cache(map, reg, *value); |
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return ret; |
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} |
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return -EINVAL; |
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} |
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/** |
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* regcache_write - Set the value of a given register in the cache. |
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* |
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* @map: map to configure. |
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* @reg: The register index. |
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* @value: The new register value. |
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* |
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* Return a negative value on failure, 0 on success. |
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*/ |
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int regcache_write(struct regmap *map, |
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unsigned int reg, unsigned int value) |
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{ |
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if (map->cache_type == REGCACHE_NONE) |
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return 0; |
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BUG_ON(!map->cache_ops); |
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if (!regmap_volatile(map, reg)) |
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return map->cache_ops->write(map, reg, value); |
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return 0; |
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} |
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static bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg, |
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unsigned int val) |
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{ |
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int ret; |
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/* If we don't know the chip just got reset, then sync everything. */ |
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if (!map->no_sync_defaults) |
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return true; |
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/* Is this the hardware default? If so skip. */ |
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ret = regcache_lookup_reg(map, reg); |
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if (ret >= 0 && val == map->reg_defaults[ret].def) |
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return false; |
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return true; |
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} |
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static int regcache_default_sync(struct regmap *map, unsigned int min, |
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unsigned int max) |
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{ |
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unsigned int reg; |
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for (reg = min; reg <= max; reg += map->reg_stride) { |
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unsigned int val; |
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int ret; |
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if (regmap_volatile(map, reg) || |
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!regmap_writeable(map, reg)) |
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continue; |
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ret = regcache_read(map, reg, &val); |
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if (ret) |
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return ret; |
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if (!regcache_reg_needs_sync(map, reg, val)) |
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continue; |
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map->cache_bypass = true; |
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ret = _regmap_write(map, reg, val); |
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map->cache_bypass = false; |
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if (ret) { |
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dev_err(map->dev, "Unable to sync register %#x. %d\n", |
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reg, ret); |
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return ret; |
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} |
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dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val); |
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} |
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return 0; |
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} |
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/** |
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* regcache_sync - Sync the register cache with the hardware. |
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* |
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* @map: map to configure. |
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* |
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* Any registers that should not be synced should be marked as |
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* volatile. In general drivers can choose not to use the provided |
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* syncing functionality if they so require. |
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* |
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* Return a negative value on failure, 0 on success. |
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*/ |
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int regcache_sync(struct regmap *map) |
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{ |
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int ret = 0; |
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unsigned int i; |
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const char *name; |
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bool bypass; |
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BUG_ON(!map->cache_ops); |
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map->lock(map->lock_arg); |
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/* Remember the initial bypass state */ |
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bypass = map->cache_bypass; |
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dev_dbg(map->dev, "Syncing %s cache\n", |
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map->cache_ops->name); |
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name = map->cache_ops->name; |
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trace_regcache_sync(map, name, "start"); |
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if (!map->cache_dirty) |
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goto out; |
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map->async = true; |
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/* Apply any patch first */ |
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map->cache_bypass = true; |
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for (i = 0; i < map->patch_regs; i++) { |
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ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def); |
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if (ret != 0) { |
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dev_err(map->dev, "Failed to write %x = %x: %d\n", |
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map->patch[i].reg, map->patch[i].def, ret); |
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goto out; |
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} |
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} |
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map->cache_bypass = false; |
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if (map->cache_ops->sync) |
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ret = map->cache_ops->sync(map, 0, map->max_register); |
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else |
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ret = regcache_default_sync(map, 0, map->max_register); |
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if (ret == 0) |
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map->cache_dirty = false; |
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out: |
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/* Restore the bypass state */ |
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map->async = false; |
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map->cache_bypass = bypass; |
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map->no_sync_defaults = false; |
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map->unlock(map->lock_arg); |
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regmap_async_complete(map); |
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trace_regcache_sync(map, name, "stop"); |
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return ret; |
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} |
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EXPORT_SYMBOL_GPL(regcache_sync); |
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/** |
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* regcache_sync_region - Sync part of the register cache with the hardware. |
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* |
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* @map: map to sync. |
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* @min: first register to sync |
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* @max: last register to sync |
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* |
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* Write all non-default register values in the specified region to |
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* the hardware. |
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* |
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* Return a negative value on failure, 0 on success. |
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*/ |
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int regcache_sync_region(struct regmap *map, unsigned int min, |
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unsigned int max) |
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{ |
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int ret = 0; |
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const char *name; |
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bool bypass; |
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BUG_ON(!map->cache_ops); |
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map->lock(map->lock_arg); |
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/* Remember the initial bypass state */ |
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bypass = map->cache_bypass; |
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name = map->cache_ops->name; |
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dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max); |
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trace_regcache_sync(map, name, "start region"); |
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if (!map->cache_dirty) |
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goto out; |
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map->async = true; |
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if (map->cache_ops->sync) |
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ret = map->cache_ops->sync(map, min, max); |
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else |
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ret = regcache_default_sync(map, min, max); |
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out: |
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/* Restore the bypass state */ |
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map->cache_bypass = bypass; |
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map->async = false; |
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map->no_sync_defaults = false; |
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map->unlock(map->lock_arg); |
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regmap_async_complete(map); |
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trace_regcache_sync(map, name, "stop region"); |
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return ret; |
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} |
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EXPORT_SYMBOL_GPL(regcache_sync_region); |
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/** |
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* regcache_drop_region - Discard part of the register cache |
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* |
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* @map: map to operate on |
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* @min: first register to discard |
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* @max: last register to discard |
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* |
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* Discard part of the register cache. |
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* |
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* Return a negative value on failure, 0 on success. |
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*/ |
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int regcache_drop_region(struct regmap *map, unsigned int min, |
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unsigned int max) |
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{ |
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int ret = 0; |
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if (!map->cache_ops || !map->cache_ops->drop) |
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return -EINVAL; |
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map->lock(map->lock_arg); |
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trace_regcache_drop_region(map, min, max); |
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ret = map->cache_ops->drop(map, min, max); |
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map->unlock(map->lock_arg); |
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return ret; |
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} |
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EXPORT_SYMBOL_GPL(regcache_drop_region); |
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/** |
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* regcache_cache_only - Put a register map into cache only mode |
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* |
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* @map: map to configure |
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* @enable: flag if changes should be written to the hardware |
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* |
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* When a register map is marked as cache only writes to the register |
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* map API will only update the register cache, they will not cause |
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* any hardware changes. This is useful for allowing portions of |
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* drivers to act as though the device were functioning as normal when |
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* it is disabled for power saving reasons. |
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*/ |
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void regcache_cache_only(struct regmap *map, bool enable) |
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{ |
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map->lock(map->lock_arg); |
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WARN_ON(map->cache_bypass && enable); |
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map->cache_only = enable; |
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trace_regmap_cache_only(map, enable); |
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map->unlock(map->lock_arg); |
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} |
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EXPORT_SYMBOL_GPL(regcache_cache_only); |
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|
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/** |
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* regcache_mark_dirty - Indicate that HW registers were reset to default values |
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* |
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* @map: map to mark |
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* |
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* Inform regcache that the device has been powered down or reset, so that |
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* on resume, regcache_sync() knows to write out all non-default values |
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* stored in the cache. |
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* |
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* If this function is not called, regcache_sync() will assume that |
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* the hardware state still matches the cache state, modulo any writes that |
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* happened when cache_only was true. |
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*/ |
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void regcache_mark_dirty(struct regmap *map) |
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{ |
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map->lock(map->lock_arg); |
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map->cache_dirty = true; |
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map->no_sync_defaults = true; |
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map->unlock(map->lock_arg); |
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} |
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EXPORT_SYMBOL_GPL(regcache_mark_dirty); |
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|
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/** |
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* regcache_cache_bypass - Put a register map into cache bypass mode |
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* |
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* @map: map to configure |
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* @enable: flag if changes should not be written to the cache |
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* |
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* When a register map is marked with the cache bypass option, writes |
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* to the register map API will only update the hardware and not the |
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* the cache directly. This is useful when syncing the cache back to |
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* the hardware. |
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*/ |
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void regcache_cache_bypass(struct regmap *map, bool enable) |
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{ |
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map->lock(map->lock_arg); |
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WARN_ON(map->cache_only && enable); |
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map->cache_bypass = enable; |
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trace_regmap_cache_bypass(map, enable); |
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map->unlock(map->lock_arg); |
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} |
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EXPORT_SYMBOL_GPL(regcache_cache_bypass); |
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bool regcache_set_val(struct regmap *map, void *base, unsigned int idx, |
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unsigned int val) |
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{ |
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if (regcache_get_val(map, base, idx) == val) |
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return true; |
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|
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/* Use device native format if possible */ |
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if (map->format.format_val) { |
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map->format.format_val(base + (map->cache_word_size * idx), |
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val, 0); |
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return false; |
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} |
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|
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switch (map->cache_word_size) { |
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case 1: { |
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u8 *cache = base; |
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|
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cache[idx] = val; |
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break; |
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} |
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case 2: { |
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u16 *cache = base; |
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|
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cache[idx] = val; |
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break; |
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} |
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case 4: { |
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u32 *cache = base; |
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|
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cache[idx] = val; |
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break; |
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} |
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#ifdef CONFIG_64BIT |
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case 8: { |
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u64 *cache = base; |
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cache[idx] = val; |
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break; |
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} |
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#endif |
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default: |
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BUG(); |
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} |
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return false; |
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} |
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|
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unsigned int regcache_get_val(struct regmap *map, const void *base, |
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unsigned int idx) |
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{ |
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if (!base) |
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return -EINVAL; |
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|
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/* Use device native format if possible */ |
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if (map->format.parse_val) |
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return map->format.parse_val(regcache_get_val_addr(map, base, |
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idx)); |
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|
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switch (map->cache_word_size) { |
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case 1: { |
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const u8 *cache = base; |
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|
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return cache[idx]; |
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} |
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case 2: { |
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const u16 *cache = base; |
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|
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return cache[idx]; |
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} |
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case 4: { |
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const u32 *cache = base; |
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|
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return cache[idx]; |
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} |
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#ifdef CONFIG_64BIT |
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case 8: { |
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const u64 *cache = base; |
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|
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return cache[idx]; |
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} |
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#endif |
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default: |
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BUG(); |
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} |
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/* unreachable */ |
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return -1; |
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} |
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|
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static int regcache_default_cmp(const void *a, const void *b) |
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{ |
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const struct reg_default *_a = a; |
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const struct reg_default *_b = b; |
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|
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return _a->reg - _b->reg; |
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} |
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|
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int regcache_lookup_reg(struct regmap *map, unsigned int reg) |
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{ |
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struct reg_default key; |
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struct reg_default *r; |
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|
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key.reg = reg; |
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key.def = 0; |
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|
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r = bsearch(&key, map->reg_defaults, map->num_reg_defaults, |
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sizeof(struct reg_default), regcache_default_cmp); |
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|
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if (r) |
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return r - map->reg_defaults; |
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else |
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return -ENOENT; |
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} |
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|
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static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx) |
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{ |
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if (!cache_present) |
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return true; |
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|
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return test_bit(idx, cache_present); |
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} |
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|
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static int regcache_sync_block_single(struct regmap *map, void *block, |
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unsigned long *cache_present, |
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unsigned int block_base, |
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unsigned int start, unsigned int end) |
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{ |
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unsigned int i, regtmp, val; |
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int ret; |
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for (i = start; i < end; i++) { |
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regtmp = block_base + (i * map->reg_stride); |
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if (!regcache_reg_present(cache_present, i) || |
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!regmap_writeable(map, regtmp)) |
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continue; |
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val = regcache_get_val(map, block, i); |
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if (!regcache_reg_needs_sync(map, regtmp, val)) |
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continue; |
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|
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map->cache_bypass = true; |
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|
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ret = _regmap_write(map, regtmp, val); |
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|
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map->cache_bypass = false; |
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if (ret != 0) { |
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dev_err(map->dev, "Unable to sync register %#x. %d\n", |
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regtmp, ret); |
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return ret; |
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} |
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dev_dbg(map->dev, "Synced register %#x, value %#x\n", |
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regtmp, val); |
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} |
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|
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return 0; |
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} |
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|
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static int regcache_sync_block_raw_flush(struct regmap *map, const void **data, |
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unsigned int base, unsigned int cur) |
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{ |
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size_t val_bytes = map->format.val_bytes; |
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int ret, count; |
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|
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if (*data == NULL) |
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return 0; |
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|
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count = (cur - base) / map->reg_stride; |
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|
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dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n", |
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count * val_bytes, count, base, cur - map->reg_stride); |
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|
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map->cache_bypass = true; |
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|
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ret = _regmap_raw_write(map, base, *data, count * val_bytes, false); |
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if (ret) |
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dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n", |
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base, cur - map->reg_stride, ret); |
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|
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map->cache_bypass = false; |
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|
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*data = NULL; |
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|
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return ret; |
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} |
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|
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static int regcache_sync_block_raw(struct regmap *map, void *block, |
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unsigned long *cache_present, |
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unsigned int block_base, unsigned int start, |
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unsigned int end) |
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{ |
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unsigned int i, val; |
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unsigned int regtmp = 0; |
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unsigned int base = 0; |
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const void *data = NULL; |
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int ret; |
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|
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for (i = start; i < end; i++) { |
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regtmp = block_base + (i * map->reg_stride); |
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|
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if (!regcache_reg_present(cache_present, i) || |
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!regmap_writeable(map, regtmp)) { |
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ret = regcache_sync_block_raw_flush(map, &data, |
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base, regtmp); |
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if (ret != 0) |
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return ret; |
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continue; |
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} |
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|
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val = regcache_get_val(map, block, i); |
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if (!regcache_reg_needs_sync(map, regtmp, val)) { |
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ret = regcache_sync_block_raw_flush(map, &data, |
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base, regtmp); |
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if (ret != 0) |
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return ret; |
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continue; |
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} |
|
|
|
if (!data) { |
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data = regcache_get_val_addr(map, block, i); |
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base = regtmp; |
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} |
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} |
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|
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return regcache_sync_block_raw_flush(map, &data, base, regtmp + |
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map->reg_stride); |
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} |
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|
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int regcache_sync_block(struct regmap *map, void *block, |
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unsigned long *cache_present, |
|
unsigned int block_base, unsigned int start, |
|
unsigned int end) |
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{ |
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if (regmap_can_raw_write(map) && !map->use_single_write) |
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return regcache_sync_block_raw(map, block, cache_present, |
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block_base, start, end); |
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else |
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return regcache_sync_block_single(map, block, cache_present, |
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block_base, start, end); |
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}
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