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385 lines
10 KiB
385 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* pata_rdc - Driver for later RDC PATA controllers |
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* |
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* This is actually a driver for hardware meeting |
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* INCITS 370-2004 (1510D): ATA Host Adapter Standards |
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* |
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* Based on ata_piix. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/blkdev.h> |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/gfp.h> |
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#include <scsi/scsi_host.h> |
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#include <linux/libata.h> |
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#include <linux/dmi.h> |
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#define DRV_NAME "pata_rdc" |
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#define DRV_VERSION "0.01" |
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struct rdc_host_priv { |
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u32 saved_iocfg; |
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}; |
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/** |
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* rdc_pata_cable_detect - Probe host controller cable detect info |
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* @ap: Port for which cable detect info is desired |
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* |
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* Read 80c cable indicator from ATA PCI device's PCI config |
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* register. This register is normally set by firmware (BIOS). |
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* |
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* LOCKING: |
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* None (inherited from caller). |
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*/ |
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static int rdc_pata_cable_detect(struct ata_port *ap) |
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{ |
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struct rdc_host_priv *hpriv = ap->host->private_data; |
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u8 mask; |
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/* check BIOS cable detect results */ |
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mask = 0x30 << (2 * ap->port_no); |
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if ((hpriv->saved_iocfg & mask) == 0) |
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return ATA_CBL_PATA40; |
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return ATA_CBL_PATA80; |
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} |
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/** |
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* rdc_pata_prereset - prereset for PATA host controller |
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* @link: Target link |
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* @deadline: deadline jiffies for the operation |
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* |
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* LOCKING: |
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* None (inherited from caller). |
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*/ |
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static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline) |
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{ |
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struct ata_port *ap = link->ap; |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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static const struct pci_bits rdc_enable_bits[] = { |
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{ 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ |
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{ 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ |
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}; |
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if (!pci_test_config_bits(pdev, &rdc_enable_bits[ap->port_no])) |
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return -ENOENT; |
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return ata_sff_prereset(link, deadline); |
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} |
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static DEFINE_SPINLOCK(rdc_lock); |
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/** |
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* rdc_set_piomode - Initialize host controller PATA PIO timings |
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* @ap: Port whose timings we are configuring |
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* @adev: um |
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* |
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* Set PIO mode for device, in host controller PCI config space. |
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* |
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* LOCKING: |
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* None (inherited from caller). |
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*/ |
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static void rdc_set_piomode(struct ata_port *ap, struct ata_device *adev) |
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{ |
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unsigned int pio = adev->pio_mode - XFER_PIO_0; |
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struct pci_dev *dev = to_pci_dev(ap->host->dev); |
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unsigned long flags; |
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unsigned int is_slave = (adev->devno != 0); |
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unsigned int master_port= ap->port_no ? 0x42 : 0x40; |
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unsigned int slave_port = 0x44; |
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u16 master_data; |
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u8 slave_data; |
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u8 udma_enable; |
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int control = 0; |
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static const /* ISP RTC */ |
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u8 timings[][2] = { { 0, 0 }, |
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{ 0, 0 }, |
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{ 1, 0 }, |
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{ 2, 1 }, |
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{ 2, 3 }, }; |
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if (pio >= 2) |
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control |= 1; /* TIME1 enable */ |
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if (ata_pio_need_iordy(adev)) |
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control |= 2; /* IE enable */ |
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if (adev->class == ATA_DEV_ATA) |
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control |= 4; /* PPE enable */ |
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spin_lock_irqsave(&rdc_lock, flags); |
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/* PIO configuration clears DTE unconditionally. It will be |
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* programmed in set_dmamode which is guaranteed to be called |
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* after set_piomode if any DMA mode is available. |
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*/ |
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pci_read_config_word(dev, master_port, &master_data); |
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if (is_slave) { |
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/* clear TIME1|IE1|PPE1|DTE1 */ |
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master_data &= 0xff0f; |
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/* Enable SITRE (separate slave timing register) */ |
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master_data |= 0x4000; |
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/* enable PPE1, IE1 and TIME1 as needed */ |
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master_data |= (control << 4); |
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pci_read_config_byte(dev, slave_port, &slave_data); |
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slave_data &= (ap->port_no ? 0x0f : 0xf0); |
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/* Load the timing nibble for this slave */ |
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slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) |
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<< (ap->port_no ? 4 : 0); |
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} else { |
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/* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ |
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master_data &= 0xccf0; |
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/* Enable PPE, IE and TIME as appropriate */ |
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master_data |= control; |
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/* load ISP and RCT */ |
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master_data |= |
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(timings[pio][0] << 12) | |
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(timings[pio][1] << 8); |
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} |
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pci_write_config_word(dev, master_port, master_data); |
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if (is_slave) |
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pci_write_config_byte(dev, slave_port, slave_data); |
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/* Ensure the UDMA bit is off - it will be turned back on if |
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UDMA is selected */ |
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pci_read_config_byte(dev, 0x48, &udma_enable); |
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udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); |
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pci_write_config_byte(dev, 0x48, udma_enable); |
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spin_unlock_irqrestore(&rdc_lock, flags); |
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} |
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/** |
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* rdc_set_dmamode - Initialize host controller PATA PIO timings |
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* @ap: Port whose timings we are configuring |
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* @adev: Drive in question |
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* |
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* Set UDMA mode for device, in host controller PCI config space. |
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* |
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* LOCKING: |
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* None (inherited from caller). |
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*/ |
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static void rdc_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
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{ |
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struct pci_dev *dev = to_pci_dev(ap->host->dev); |
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unsigned long flags; |
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u8 master_port = ap->port_no ? 0x42 : 0x40; |
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u16 master_data; |
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u8 speed = adev->dma_mode; |
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int devid = adev->devno + 2 * ap->port_no; |
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u8 udma_enable = 0; |
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static const /* ISP RTC */ |
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u8 timings[][2] = { { 0, 0 }, |
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{ 0, 0 }, |
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{ 1, 0 }, |
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{ 2, 1 }, |
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{ 2, 3 }, }; |
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spin_lock_irqsave(&rdc_lock, flags); |
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pci_read_config_word(dev, master_port, &master_data); |
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pci_read_config_byte(dev, 0x48, &udma_enable); |
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if (speed >= XFER_UDMA_0) { |
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unsigned int udma = adev->dma_mode - XFER_UDMA_0; |
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u16 udma_timing; |
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u16 ideconf; |
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int u_clock, u_speed; |
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/* |
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* UDMA is handled by a combination of clock switching and |
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* selection of dividers |
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* |
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* Handy rule: Odd modes are UDMATIMx 01, even are 02 |
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* except UDMA0 which is 00 |
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*/ |
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u_speed = min(2 - (udma & 1), udma); |
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if (udma == 5) |
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u_clock = 0x1000; /* 100Mhz */ |
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else if (udma > 2) |
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u_clock = 1; /* 66Mhz */ |
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else |
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u_clock = 0; /* 33Mhz */ |
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udma_enable |= (1 << devid); |
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/* Load the CT/RP selection */ |
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pci_read_config_word(dev, 0x4A, &udma_timing); |
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udma_timing &= ~(3 << (4 * devid)); |
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udma_timing |= u_speed << (4 * devid); |
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pci_write_config_word(dev, 0x4A, udma_timing); |
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/* Select a 33/66/100Mhz clock */ |
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pci_read_config_word(dev, 0x54, &ideconf); |
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ideconf &= ~(0x1001 << devid); |
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ideconf |= u_clock << devid; |
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pci_write_config_word(dev, 0x54, ideconf); |
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} else { |
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/* |
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* MWDMA is driven by the PIO timings. We must also enable |
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* IORDY unconditionally along with TIME1. PPE has already |
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* been set when the PIO timing was set. |
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*/ |
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unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; |
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unsigned int control; |
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u8 slave_data; |
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const unsigned int needed_pio[3] = { |
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XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 |
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}; |
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int pio = needed_pio[mwdma] - XFER_PIO_0; |
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control = 3; /* IORDY|TIME1 */ |
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/* If the drive MWDMA is faster than it can do PIO then |
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we must force PIO into PIO0 */ |
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if (adev->pio_mode < needed_pio[mwdma]) |
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/* Enable DMA timing only */ |
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control |= 8; /* PIO cycles in PIO0 */ |
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if (adev->devno) { /* Slave */ |
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master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ |
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master_data |= control << 4; |
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pci_read_config_byte(dev, 0x44, &slave_data); |
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slave_data &= (ap->port_no ? 0x0f : 0xf0); |
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/* Load the matching timing */ |
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slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); |
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pci_write_config_byte(dev, 0x44, slave_data); |
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} else { /* Master */ |
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master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY |
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and master timing bits */ |
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master_data |= control; |
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master_data |= |
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(timings[pio][0] << 12) | |
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(timings[pio][1] << 8); |
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} |
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udma_enable &= ~(1 << devid); |
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pci_write_config_word(dev, master_port, master_data); |
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} |
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pci_write_config_byte(dev, 0x48, udma_enable); |
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spin_unlock_irqrestore(&rdc_lock, flags); |
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} |
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static struct ata_port_operations rdc_pata_ops = { |
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.inherits = &ata_bmdma32_port_ops, |
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.cable_detect = rdc_pata_cable_detect, |
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.set_piomode = rdc_set_piomode, |
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.set_dmamode = rdc_set_dmamode, |
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.prereset = rdc_pata_prereset, |
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}; |
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static const struct ata_port_info rdc_port_info = { |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA12_ONLY, |
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.udma_mask = ATA_UDMA5, |
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.port_ops = &rdc_pata_ops, |
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}; |
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static struct scsi_host_template rdc_sht = { |
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ATA_BMDMA_SHT(DRV_NAME), |
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}; |
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/** |
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* rdc_init_one - Register PIIX ATA PCI device with kernel services |
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* @pdev: PCI device to register |
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* @ent: Entry in rdc_pci_tbl matching with @pdev |
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* |
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* Called from kernel PCI layer. We probe for combined mode (sigh), |
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* and then hand over control to libata, for it to do the rest. |
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* |
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* LOCKING: |
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* Inherited from PCI layer (may sleep). |
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* |
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* RETURNS: |
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* Zero on success, or -ERRNO value. |
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*/ |
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static int rdc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
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{ |
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struct device *dev = &pdev->dev; |
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struct ata_port_info port_info[2]; |
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const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; |
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struct ata_host *host; |
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struct rdc_host_priv *hpriv; |
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int rc; |
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ata_print_version_once(&pdev->dev, DRV_VERSION); |
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port_info[0] = rdc_port_info; |
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port_info[1] = rdc_port_info; |
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/* enable device and prepare host */ |
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rc = pcim_enable_device(pdev); |
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if (rc) |
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return rc; |
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hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
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if (!hpriv) |
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return -ENOMEM; |
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/* Save IOCFG, this will be used for cable detection, quirk |
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* detection and restoration on detach. |
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*/ |
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pci_read_config_dword(pdev, 0x54, &hpriv->saved_iocfg); |
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rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); |
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if (rc) |
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return rc; |
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host->private_data = hpriv; |
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pci_intx(pdev, 1); |
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host->flags |= ATA_HOST_PARALLEL_SCAN; |
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pci_set_master(pdev); |
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return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, &rdc_sht); |
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} |
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static void rdc_remove_one(struct pci_dev *pdev) |
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{ |
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struct ata_host *host = pci_get_drvdata(pdev); |
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struct rdc_host_priv *hpriv = host->private_data; |
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pci_write_config_dword(pdev, 0x54, hpriv->saved_iocfg); |
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ata_pci_remove_one(pdev); |
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} |
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static const struct pci_device_id rdc_pci_tbl[] = { |
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{ PCI_DEVICE(0x17F3, 0x1011), }, |
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{ PCI_DEVICE(0x17F3, 0x1012), }, |
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{ } /* terminate list */ |
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}; |
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static struct pci_driver rdc_pci_driver = { |
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.name = DRV_NAME, |
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.id_table = rdc_pci_tbl, |
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.probe = rdc_init_one, |
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.remove = rdc_remove_one, |
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#ifdef CONFIG_PM_SLEEP |
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.suspend = ata_pci_device_suspend, |
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.resume = ata_pci_device_resume, |
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#endif |
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}; |
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module_pci_driver(rdc_pci_driver); |
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MODULE_AUTHOR("Alan Cox (based on ata_piix)"); |
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MODULE_DESCRIPTION("SCSI low-level driver for RDC PATA controllers"); |
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MODULE_LICENSE("GPL"); |
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MODULE_DEVICE_TABLE(pci, rdc_pci_tbl); |
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MODULE_VERSION(DRV_VERSION);
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