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234 lines
5.5 KiB
234 lines
5.5 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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// |
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// Copyright 2019 Madhavan Srinivasan, IBM Corporation. |
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#define pr_fmt(fmt) "generic-compat-pmu: " fmt |
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#include "isa207-common.h" |
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/* |
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* Raw event encoding: |
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* |
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* 60 56 52 48 44 40 36 32 |
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | |
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* |
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* 28 24 20 16 12 8 4 0 |
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | |
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* [ pmc ] [unit ] [ ] m [ pmcxsel ] |
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* | | |
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* | *- mark |
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* | |
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* | |
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* *- combine |
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* |
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* Below uses IBM bit numbering. |
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* |
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* MMCR1[x:y] = unit (PMCxUNIT) |
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* MMCR1[24] = pmc1combine[0] |
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* MMCR1[25] = pmc1combine[1] |
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* MMCR1[26] = pmc2combine[0] |
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* MMCR1[27] = pmc2combine[1] |
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* MMCR1[28] = pmc3combine[0] |
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* MMCR1[29] = pmc3combine[1] |
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* MMCR1[30] = pmc4combine[0] |
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* MMCR1[31] = pmc4combine[1] |
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* |
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*/ |
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/* |
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* Some power9 event codes. |
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*/ |
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#define EVENT(_name, _code) _name = _code, |
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enum { |
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EVENT(PM_CYC, 0x0001e) |
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EVENT(PM_INST_CMPL, 0x00002) |
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}; |
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#undef EVENT |
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GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC); |
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GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL); |
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static struct attribute *generic_compat_events_attr[] = { |
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GENERIC_EVENT_PTR(PM_CYC), |
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GENERIC_EVENT_PTR(PM_INST_CMPL), |
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NULL |
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}; |
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static struct attribute_group generic_compat_pmu_events_group = { |
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.name = "events", |
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.attrs = generic_compat_events_attr, |
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}; |
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PMU_FORMAT_ATTR(event, "config:0-19"); |
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PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); |
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PMU_FORMAT_ATTR(mark, "config:8"); |
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PMU_FORMAT_ATTR(combine, "config:10-11"); |
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PMU_FORMAT_ATTR(unit, "config:12-15"); |
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PMU_FORMAT_ATTR(pmc, "config:16-19"); |
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static struct attribute *generic_compat_pmu_format_attr[] = { |
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&format_attr_event.attr, |
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&format_attr_pmcxsel.attr, |
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&format_attr_mark.attr, |
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&format_attr_combine.attr, |
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&format_attr_unit.attr, |
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&format_attr_pmc.attr, |
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NULL, |
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}; |
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static struct attribute_group generic_compat_pmu_format_group = { |
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.name = "format", |
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.attrs = generic_compat_pmu_format_attr, |
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}; |
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static const struct attribute_group *generic_compat_pmu_attr_groups[] = { |
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&generic_compat_pmu_format_group, |
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&generic_compat_pmu_events_group, |
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NULL, |
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}; |
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static int compat_generic_events[] = { |
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[PERF_COUNT_HW_CPU_CYCLES] = PM_CYC, |
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[PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL, |
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}; |
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#define C(x) PERF_COUNT_HW_CACHE_##x |
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/* |
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* Table of generalized cache-related events. |
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* 0 means not supported, -1 means nonsensical, other values |
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* are event codes. |
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*/ |
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static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { |
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[ C(L1D) ] = { |
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[ C(OP_READ) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0, |
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}, |
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[ C(OP_WRITE) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0, |
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}, |
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[ C(OP_PREFETCH) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0, |
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}, |
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}, |
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[ C(L1I) ] = { |
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[ C(OP_READ) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0, |
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}, |
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[ C(OP_WRITE) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = -1, |
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}, |
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[ C(OP_PREFETCH) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0, |
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}, |
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}, |
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[ C(LL) ] = { |
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[ C(OP_READ) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0, |
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}, |
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[ C(OP_WRITE) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0, |
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}, |
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[ C(OP_PREFETCH) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0, |
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}, |
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}, |
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[ C(DTLB) ] = { |
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[ C(OP_READ) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0, |
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}, |
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[ C(OP_WRITE) ] = { |
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[ C(RESULT_ACCESS) ] = -1, |
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[ C(RESULT_MISS) ] = -1, |
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}, |
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[ C(OP_PREFETCH) ] = { |
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[ C(RESULT_ACCESS) ] = -1, |
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[ C(RESULT_MISS) ] = -1, |
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}, |
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}, |
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[ C(ITLB) ] = { |
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[ C(OP_READ) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0, |
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}, |
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[ C(OP_WRITE) ] = { |
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[ C(RESULT_ACCESS) ] = -1, |
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[ C(RESULT_MISS) ] = -1, |
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}, |
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[ C(OP_PREFETCH) ] = { |
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[ C(RESULT_ACCESS) ] = -1, |
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[ C(RESULT_MISS) ] = -1, |
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}, |
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}, |
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[ C(BPU) ] = { |
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[ C(OP_READ) ] = { |
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[ C(RESULT_ACCESS) ] = 0, |
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[ C(RESULT_MISS) ] = 0, |
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}, |
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[ C(OP_WRITE) ] = { |
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[ C(RESULT_ACCESS) ] = -1, |
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[ C(RESULT_MISS) ] = -1, |
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}, |
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[ C(OP_PREFETCH) ] = { |
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[ C(RESULT_ACCESS) ] = -1, |
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[ C(RESULT_MISS) ] = -1, |
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}, |
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}, |
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[ C(NODE) ] = { |
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[ C(OP_READ) ] = { |
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[ C(RESULT_ACCESS) ] = -1, |
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[ C(RESULT_MISS) ] = -1, |
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}, |
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[ C(OP_WRITE) ] = { |
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[ C(RESULT_ACCESS) ] = -1, |
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[ C(RESULT_MISS) ] = -1, |
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}, |
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[ C(OP_PREFETCH) ] = { |
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[ C(RESULT_ACCESS) ] = -1, |
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[ C(RESULT_MISS) ] = -1, |
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}, |
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}, |
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}; |
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#undef C |
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static struct power_pmu generic_compat_pmu = { |
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.name = "GENERIC_COMPAT", |
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.n_counter = MAX_PMU_COUNTERS, |
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.add_fields = ISA207_ADD_FIELDS, |
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.test_adder = ISA207_TEST_ADDER, |
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.compute_mmcr = isa207_compute_mmcr, |
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.get_constraint = isa207_get_constraint, |
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.disable_pmc = isa207_disable_pmc, |
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.flags = PPMU_HAS_SIER | PPMU_ARCH_207S, |
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.n_generic = ARRAY_SIZE(compat_generic_events), |
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.generic_events = compat_generic_events, |
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.cache_events = &generic_compat_cache_events, |
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.attr_groups = generic_compat_pmu_attr_groups, |
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}; |
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int init_generic_compat_pmu(void) |
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{ |
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int rc = 0; |
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rc = register_power_pmu(&generic_compat_pmu); |
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if (rc) |
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return rc; |
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/* Tell userspace that EBB is supported */ |
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cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB; |
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return 0; |
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}
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