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596 lines
17 KiB
596 lines
17 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* PowerPC version |
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
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* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP |
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> |
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* Adapted for Power Macintosh by Paul Mackerras. |
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* Low-level exception handlers and MMU support |
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* rewritten by Paul Mackerras. |
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* Copyright (C) 1996 Paul Mackerras. |
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* |
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* This file contains low-level assembler routines for managing |
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* the PowerPC MMU hash table. (PPC 8xx processors don't use a |
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* hash table, so this file is not used on them.) |
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*/ |
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|
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#include <linux/pgtable.h> |
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#include <linux/init.h> |
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#include <asm/reg.h> |
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#include <asm/page.h> |
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#include <asm/cputable.h> |
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#include <asm/ppc_asm.h> |
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#include <asm/thread_info.h> |
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#include <asm/asm-offsets.h> |
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#include <asm/export.h> |
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#include <asm/feature-fixups.h> |
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#include <asm/code-patching-asm.h> |
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#ifdef CONFIG_PTE_64BIT |
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#define PTE_FLAGS_OFFSET 4 /* offset of PTE flags, in bytes */ |
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#else |
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#define PTE_FLAGS_OFFSET 0 |
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#endif |
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|
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/* |
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* Load a PTE into the hash table, if possible. |
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* The address is in r4, and r3 contains an access flag: |
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* _PAGE_RW (0x400) if a write. |
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* r9 contains the SRR1 value, from which we use the MSR_PR bit. |
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* SPRG_THREAD contains the physical address of the current task's thread. |
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* |
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* Returns to the caller if the access is illegal or there is no |
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* mapping for the address. Otherwise it places an appropriate PTE |
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* in the hash table and returns from the exception. |
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* Uses r0, r3 - r6, r8, r10, ctr, lr. |
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*/ |
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.text |
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_GLOBAL(hash_page) |
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#ifdef CONFIG_SMP |
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lis r8, (mmu_hash_lock - PAGE_OFFSET)@h |
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ori r8, r8, (mmu_hash_lock - PAGE_OFFSET)@l |
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lis r0,0x0fff |
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b 10f |
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11: lwz r6,0(r8) |
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cmpwi 0,r6,0 |
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bne 11b |
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10: lwarx r6,0,r8 |
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cmpwi 0,r6,0 |
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bne- 11b |
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stwcx. r0,0,r8 |
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bne- 10b |
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isync |
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#endif |
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/* Get PTE (linux-style) and check access */ |
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lis r0, TASK_SIZE@h /* check if kernel address */ |
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cmplw 0,r4,r0 |
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mfspr r8,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ |
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ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */ |
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lwz r5,PGDIR(r8) /* virt page-table root */ |
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blt+ 112f /* assume user more likely */ |
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lis r5,swapper_pg_dir@ha /* if kernel address, use */ |
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addi r5,r5,swapper_pg_dir@l /* kernel page table */ |
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rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */ |
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112: tophys(r5, r5) |
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#ifndef CONFIG_PTE_64BIT |
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rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */ |
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lwz r8,0(r5) /* get pmd entry */ |
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rlwinm. r8,r8,0,0,19 /* extract address of pte page */ |
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#else |
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rlwinm r8,r4,13,19,29 /* Compute pgdir/pmd offset */ |
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lwzx r8,r8,r5 /* Get L1 entry */ |
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rlwinm. r8,r8,0,0,20 /* extract pt base address */ |
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#endif |
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#ifdef CONFIG_SMP |
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beq- .Lhash_page_out /* return if no mapping */ |
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#else |
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/* XXX it seems like the 601 will give a machine fault on the |
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rfi if its alignment is wrong (bottom 4 bits of address are |
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8 or 0xc) and we have had a not-taken conditional branch |
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to the address following the rfi. */ |
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beqlr- |
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#endif |
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#ifndef CONFIG_PTE_64BIT |
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rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */ |
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#else |
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rlwimi r8,r4,23,20,28 /* compute pte address */ |
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/* |
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* If PTE_64BIT is set, the low word is the flags word; use that |
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* word for locking since it contains all the interesting bits. |
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*/ |
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addi r8,r8,PTE_FLAGS_OFFSET |
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#endif |
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/* |
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* Update the linux PTE atomically. We do the lwarx up-front |
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* because almost always, there won't be a permission violation |
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* and there won't already be an HPTE, and thus we will have |
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* to update the PTE to set _PAGE_HASHPTE. -- paulus. |
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*/ |
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.Lretry: |
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lwarx r6,0,r8 /* get linux-style pte, flag word */ |
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#ifdef CONFIG_PPC_KUAP |
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mfsrin r5,r4 |
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rlwinm r0,r9,28,_PAGE_RW /* MSR[PR] => _PAGE_RW */ |
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rlwinm r5,r5,12,_PAGE_RW /* Ks => _PAGE_RW */ |
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andc r5,r5,r0 /* Ks & ~MSR[PR] */ |
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andc r5,r6,r5 /* Clear _PAGE_RW when Ks = 1 && MSR[PR] = 0 */ |
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andc. r5,r3,r5 /* check access & ~permission */ |
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#else |
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andc. r5,r3,r6 /* check access & ~permission */ |
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#endif |
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rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */ |
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ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE |
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#ifdef CONFIG_SMP |
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bne- .Lhash_page_out /* return if access not permitted */ |
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#else |
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bnelr- |
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#endif |
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or r5,r0,r6 /* set accessed/dirty bits */ |
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#ifdef CONFIG_PTE_64BIT |
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#ifdef CONFIG_SMP |
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subf r10,r6,r8 /* create false data dependency */ |
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subi r10,r10,PTE_FLAGS_OFFSET |
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lwzx r10,r6,r10 /* Get upper PTE word */ |
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#else |
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lwz r10,-PTE_FLAGS_OFFSET(r8) |
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#endif /* CONFIG_SMP */ |
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#endif /* CONFIG_PTE_64BIT */ |
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stwcx. r5,0,r8 /* attempt to update PTE */ |
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bne- .Lretry /* retry if someone got there first */ |
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|
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mfsrin r3,r4 /* get segment reg for segment */ |
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bl create_hpte /* add the hash table entry */ |
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#ifdef CONFIG_SMP |
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eieio |
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lis r8, (mmu_hash_lock - PAGE_OFFSET)@ha |
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li r0,0 |
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stw r0, (mmu_hash_lock - PAGE_OFFSET)@l(r8) |
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#endif |
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b fast_hash_page_return |
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#ifdef CONFIG_SMP |
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.Lhash_page_out: |
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eieio |
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lis r8, (mmu_hash_lock - PAGE_OFFSET)@ha |
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li r0,0 |
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stw r0, (mmu_hash_lock - PAGE_OFFSET)@l(r8) |
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blr |
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#endif /* CONFIG_SMP */ |
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_ASM_NOKPROBE_SYMBOL(hash_page) |
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/* |
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* Add an entry for a particular page to the hash table. |
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* |
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* add_hash_page(unsigned context, unsigned long va, unsigned long pmdval) |
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* |
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* We assume any necessary modifications to the pte (e.g. setting |
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* the accessed bit) have already been done and that there is actually |
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* a hash table in use (i.e. we're not on a 603). |
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*/ |
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_GLOBAL(add_hash_page) |
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mflr r0 |
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stw r0,4(r1) |
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#ifdef CONFIG_SMP |
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lwz r8,TASK_CPU(r2) /* to go in mmu_hash_lock */ |
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oris r8,r8,12 |
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#endif /* CONFIG_SMP */ |
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/* |
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* We disable interrupts here, even on UP, because we don't |
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* want to race with hash_page, and because we want the |
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* _PAGE_HASHPTE bit to be a reliable indication of whether |
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* the HPTE exists (or at least whether one did once). |
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* We also turn off the MMU for data accesses so that we |
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* we can't take a hash table miss (assuming the code is |
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* covered by a BAT). -- paulus |
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*/ |
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mfmsr r9 |
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rlwinm r0,r9,0,17,15 /* clear bit 16 (MSR_EE) */ |
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rlwinm r0,r0,0,28,26 /* clear MSR_DR */ |
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mtmsr r0 |
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isync |
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#ifdef CONFIG_SMP |
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lis r6, (mmu_hash_lock - PAGE_OFFSET)@ha |
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addi r6, r6, (mmu_hash_lock - PAGE_OFFSET)@l |
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10: lwarx r0,0,r6 /* take the mmu_hash_lock */ |
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cmpi 0,r0,0 |
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bne- 11f |
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stwcx. r8,0,r6 |
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beq+ 12f |
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11: lwz r0,0(r6) |
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cmpi 0,r0,0 |
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beq 10b |
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b 11b |
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12: isync |
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#endif |
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/* |
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* Fetch the linux pte and test and set _PAGE_HASHPTE atomically. |
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* If _PAGE_HASHPTE was already set, we don't replace the existing |
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* HPTE, so we just unlock and return. |
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*/ |
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mr r8,r5 |
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#ifndef CONFIG_PTE_64BIT |
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rlwimi r8,r4,22,20,29 |
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#else |
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rlwimi r8,r4,23,20,28 |
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addi r8,r8,PTE_FLAGS_OFFSET |
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#endif |
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1: lwarx r6,0,r8 |
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andi. r0,r6,_PAGE_HASHPTE |
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bne 9f /* if HASHPTE already set, done */ |
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#ifdef CONFIG_PTE_64BIT |
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#ifdef CONFIG_SMP |
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subf r10,r6,r8 /* create false data dependency */ |
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subi r10,r10,PTE_FLAGS_OFFSET |
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lwzx r10,r6,r10 /* Get upper PTE word */ |
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#else |
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lwz r10,-PTE_FLAGS_OFFSET(r8) |
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#endif /* CONFIG_SMP */ |
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#endif /* CONFIG_PTE_64BIT */ |
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ori r5,r6,_PAGE_HASHPTE |
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stwcx. r5,0,r8 |
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bne- 1b |
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/* Convert context and va to VSID */ |
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mulli r3,r3,897*16 /* multiply context by context skew */ |
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rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ |
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mulli r0,r0,0x111 /* multiply by ESID skew */ |
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add r3,r3,r0 /* note create_hpte trims to 24 bits */ |
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bl create_hpte |
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9: |
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#ifdef CONFIG_SMP |
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lis r6, (mmu_hash_lock - PAGE_OFFSET)@ha |
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addi r6, r6, (mmu_hash_lock - PAGE_OFFSET)@l |
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eieio |
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li r0,0 |
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stw r0,0(r6) /* clear mmu_hash_lock */ |
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#endif |
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/* reenable interrupts and DR */ |
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mtmsr r9 |
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isync |
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lwz r0,4(r1) |
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mtlr r0 |
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blr |
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_ASM_NOKPROBE_SYMBOL(add_hash_page) |
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/* |
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* This routine adds a hardware PTE to the hash table. |
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* It is designed to be called with the MMU either on or off. |
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* r3 contains the VSID, r4 contains the virtual address, |
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* r5 contains the linux PTE, r6 contains the old value of the |
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* linux PTE (before setting _PAGE_HASHPTE). r10 contains the |
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* upper half of the PTE if CONFIG_PTE_64BIT. |
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* On SMP, the caller should have the mmu_hash_lock held. |
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* We assume that the caller has (or will) set the _PAGE_HASHPTE |
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* bit in the linux PTE in memory. The value passed in r6 should |
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* be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set |
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* this routine will skip the search for an existing HPTE. |
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* This procedure modifies r0, r3 - r6, r8, cr0. |
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* -- paulus. |
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* |
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* For speed, 4 of the instructions get patched once the size and |
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* physical address of the hash table are known. These definitions |
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* of Hash_base and Hash_bits below are for the early hash table. |
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*/ |
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Hash_base = early_hash |
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Hash_bits = 12 /* e.g. 256kB hash table */ |
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Hash_msk = (((1 << Hash_bits) - 1) * 64) |
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|
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/* defines for the PTE format for 32-bit PPCs */ |
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#define HPTE_SIZE 8 |
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#define PTEG_SIZE 64 |
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#define LG_PTEG_SIZE 6 |
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#define LDPTEu lwzu |
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#define LDPTE lwz |
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#define STPTE stw |
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#define CMPPTE cmpw |
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#define PTE_H 0x40 |
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#define PTE_V 0x80000000 |
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#define TST_V(r) rlwinm. r,r,0,0,0 |
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#define SET_V(r) oris r,r,PTE_V@h |
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#define CLR_V(r,t) rlwinm r,r,0,1,31 |
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#define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1) |
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#define HASH_RIGHT 31-LG_PTEG_SIZE |
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__REF |
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_GLOBAL(create_hpte) |
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/* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */ |
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rlwinm r8,r5,32-9,30,30 /* _PAGE_RW -> PP msb */ |
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rlwinm r0,r5,32-6,30,30 /* _PAGE_DIRTY -> PP msb */ |
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and r8,r8,r0 /* writable if _RW & _DIRTY */ |
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rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */ |
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rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */ |
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ori r8,r8,0xe04 /* clear out reserved bits */ |
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andc r8,r5,r8 /* PP = user? (rw&dirty? 1: 3): 0 */ |
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BEGIN_FTR_SECTION |
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rlwinm r8,r8,0,~_PAGE_COHERENT /* clear M (coherence not required) */ |
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END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) |
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#ifdef CONFIG_PTE_64BIT |
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/* Put the XPN bits into the PTE */ |
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rlwimi r8,r10,8,20,22 |
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rlwimi r8,r10,2,29,29 |
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#endif |
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|
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/* Construct the high word of the PPC-style PTE (r5) */ |
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rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ |
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rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */ |
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SET_V(r5) /* set V (valid) bit */ |
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|
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patch_site 0f, patch__hash_page_A0 |
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patch_site 1f, patch__hash_page_A1 |
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patch_site 2f, patch__hash_page_A2 |
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/* Get the address of the primary PTE group in the hash table (r3) */ |
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0: lis r0, (Hash_base - PAGE_OFFSET)@h /* base address of hash table */ |
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1: rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ |
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2: rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ |
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xor r3,r3,r0 /* make primary hash */ |
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li r0,8 /* PTEs/group */ |
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/* |
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* Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search |
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* if it is clear, meaning that the HPTE isn't there already... |
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*/ |
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andi. r6,r6,_PAGE_HASHPTE |
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beq+ 10f /* no PTE: go look for an empty slot */ |
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tlbie r4 |
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/* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ |
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mtctr r0 |
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addi r4,r3,-HPTE_SIZE |
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1: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */ |
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CMPPTE 0,r6,r5 |
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bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ |
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beq+ .Lfound_slot |
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|
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patch_site 0f, patch__hash_page_B |
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/* Search the secondary PTEG for a matching PTE */ |
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ori r5,r5,PTE_H /* set H (secondary hash) bit */ |
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0: xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ |
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xori r4,r4,(-PTEG_SIZE & 0xffff) |
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addi r4,r4,-HPTE_SIZE |
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mtctr r0 |
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2: LDPTEu r6,HPTE_SIZE(r4) |
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CMPPTE 0,r6,r5 |
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bdnzf 2,2b |
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beq+ .Lfound_slot |
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xori r5,r5,PTE_H /* clear H bit again */ |
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|
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/* Search the primary PTEG for an empty slot */ |
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10: mtctr r0 |
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addi r4,r3,-HPTE_SIZE /* search primary PTEG */ |
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1: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */ |
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TST_V(r6) /* test valid bit */ |
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bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ |
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beq+ .Lfound_empty |
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|
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patch_site 0f, patch__hash_page_C |
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/* Search the secondary PTEG for an empty slot */ |
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ori r5,r5,PTE_H /* set H (secondary hash) bit */ |
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0: xoris r4,r3,Hash_msk>>16 /* compute secondary hash */ |
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xori r4,r4,(-PTEG_SIZE & 0xffff) |
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addi r4,r4,-HPTE_SIZE |
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mtctr r0 |
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2: LDPTEu r6,HPTE_SIZE(r4) |
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TST_V(r6) |
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bdnzf 2,2b |
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beq+ .Lfound_empty |
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xori r5,r5,PTE_H /* clear H bit again */ |
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|
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/* |
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* Choose an arbitrary slot in the primary PTEG to overwrite. |
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* Since both the primary and secondary PTEGs are full, and we |
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* have no information that the PTEs in the primary PTEG are |
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* more important or useful than those in the secondary PTEG, |
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* and we know there is a definite (although small) speed |
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* advantage to putting the PTE in the primary PTEG, we always |
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* put the PTE in the primary PTEG. |
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*/ |
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|
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lis r4, (next_slot - PAGE_OFFSET)@ha /* get next evict slot */ |
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lwz r6, (next_slot - PAGE_OFFSET)@l(r4) |
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addi r6,r6,HPTE_SIZE /* search for candidate */ |
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andi. r6,r6,7*HPTE_SIZE |
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stw r6,next_slot@l(r4) |
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add r4,r3,r6 |
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#ifndef CONFIG_SMP |
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/* Store PTE in PTEG */ |
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.Lfound_empty: |
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STPTE r5,0(r4) |
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.Lfound_slot: |
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STPTE r8,HPTE_SIZE/2(r4) |
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|
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#else /* CONFIG_SMP */ |
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/* |
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* Between the tlbie above and updating the hash table entry below, |
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* another CPU could read the hash table entry and put it in its TLB. |
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* There are 3 cases: |
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* 1. using an empty slot |
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* 2. updating an earlier entry to change permissions (i.e. enable write) |
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* 3. taking over the PTE for an unrelated address |
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* |
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* In each case it doesn't really matter if the other CPUs have the old |
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* PTE in their TLB. So we don't need to bother with another tlbie here, |
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* which is convenient as we've overwritten the register that had the |
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* address. :-) The tlbie above is mainly to make sure that this CPU comes |
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* and gets the new PTE from the hash table. |
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* |
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* We do however have to make sure that the PTE is never in an invalid |
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* state with the V bit set. |
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*/ |
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.Lfound_empty: |
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.Lfound_slot: |
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CLR_V(r5,r0) /* clear V (valid) bit in PTE */ |
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STPTE r5,0(r4) |
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sync |
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TLBSYNC |
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STPTE r8,HPTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */ |
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sync |
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SET_V(r5) |
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STPTE r5,0(r4) /* finally set V bit in PTE */ |
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#endif /* CONFIG_SMP */ |
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sync /* make sure pte updates get to memory */ |
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blr |
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.previous |
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_ASM_NOKPROBE_SYMBOL(create_hpte) |
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|
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.section .bss |
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.align 2 |
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next_slot: |
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.space 4 |
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.previous |
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/* |
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* Flush the entry for a particular page from the hash table. |
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* |
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* flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval, |
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* int count) |
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* |
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* We assume that there is a hash table in use (Hash != 0). |
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*/ |
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__REF |
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_GLOBAL(flush_hash_pages) |
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/* |
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* We disable interrupts here, even on UP, because we want |
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* the _PAGE_HASHPTE bit to be a reliable indication of |
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* whether the HPTE exists (or at least whether one did once). |
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* We also turn off the MMU for data accesses so that we |
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* we can't take a hash table miss (assuming the code is |
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* covered by a BAT). -- paulus |
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*/ |
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mfmsr r10 |
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ |
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rlwinm r0,r0,0,28,26 /* clear MSR_DR */ |
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mtmsr r0 |
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isync |
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/* First find a PTE in the range that has _PAGE_HASHPTE set */ |
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#ifndef CONFIG_PTE_64BIT |
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rlwimi r5,r4,22,20,29 |
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#else |
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rlwimi r5,r4,23,20,28 |
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addi r5,r5,PTE_FLAGS_OFFSET |
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#endif |
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1: lwz r0,0(r5) |
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cmpwi cr1,r6,1 |
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andi. r0,r0,_PAGE_HASHPTE |
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bne 2f |
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ble cr1,19f |
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addi r4,r4,0x1000 |
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addi r5,r5,PTE_SIZE |
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addi r6,r6,-1 |
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b 1b |
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/* Convert context and va to VSID */ |
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2: mulli r3,r3,897*16 /* multiply context by context skew */ |
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rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */ |
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mulli r0,r0,0x111 /* multiply by ESID skew */ |
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add r3,r3,r0 /* note code below trims to 24 bits */ |
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/* Construct the high word of the PPC-style PTE (r11) */ |
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rlwinm r11,r3,7,1,24 /* put VSID in 0x7fffff80 bits */ |
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rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */ |
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SET_V(r11) /* set V (valid) bit */ |
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#ifdef CONFIG_SMP |
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lis r9, (mmu_hash_lock - PAGE_OFFSET)@ha |
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addi r9, r9, (mmu_hash_lock - PAGE_OFFSET)@l |
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tophys (r8, r2) |
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lwz r8, TASK_CPU(r8) |
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oris r8,r8,9 |
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10: lwarx r0,0,r9 |
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cmpi 0,r0,0 |
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bne- 11f |
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stwcx. r8,0,r9 |
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beq+ 12f |
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11: lwz r0,0(r9) |
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cmpi 0,r0,0 |
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beq 10b |
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b 11b |
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12: isync |
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#endif |
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/* |
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* Check the _PAGE_HASHPTE bit in the linux PTE. If it is |
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* already clear, we're done (for this pte). If not, |
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* clear it (atomically) and proceed. -- paulus. |
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*/ |
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33: lwarx r8,0,r5 /* fetch the pte flags word */ |
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andi. r0,r8,_PAGE_HASHPTE |
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beq 8f /* done if HASHPTE is already clear */ |
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rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */ |
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stwcx. r8,0,r5 /* update the pte */ |
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bne- 33b |
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patch_site 0f, patch__flush_hash_A0 |
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patch_site 1f, patch__flush_hash_A1 |
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patch_site 2f, patch__flush_hash_A2 |
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/* Get the address of the primary PTE group in the hash table (r3) */ |
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0: lis r8, (Hash_base - PAGE_OFFSET)@h /* base address of hash table */ |
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1: rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */ |
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2: rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */ |
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xor r8,r0,r8 /* make primary hash */ |
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/* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */ |
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li r0,8 /* PTEs/group */ |
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mtctr r0 |
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addi r12,r8,-HPTE_SIZE |
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1: LDPTEu r0,HPTE_SIZE(r12) /* get next PTE */ |
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CMPPTE 0,r0,r11 |
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bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */ |
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beq+ 3f |
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patch_site 0f, patch__flush_hash_B |
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/* Search the secondary PTEG for a matching PTE */ |
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ori r11,r11,PTE_H /* set H (secondary hash) bit */ |
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li r0,8 /* PTEs/group */ |
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0: xoris r12,r8,Hash_msk>>16 /* compute secondary hash */ |
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xori r12,r12,(-PTEG_SIZE & 0xffff) |
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addi r12,r12,-HPTE_SIZE |
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mtctr r0 |
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2: LDPTEu r0,HPTE_SIZE(r12) |
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CMPPTE 0,r0,r11 |
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bdnzf 2,2b |
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xori r11,r11,PTE_H /* clear H again */ |
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bne- 4f /* should rarely fail to find it */ |
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3: li r0,0 |
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STPTE r0,0(r12) /* invalidate entry */ |
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4: sync |
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tlbie r4 /* in hw tlb too */ |
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sync |
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8: ble cr1,9f /* if all ptes checked */ |
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81: addi r6,r6,-1 |
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addi r5,r5,PTE_SIZE |
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addi r4,r4,0x1000 |
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lwz r0,0(r5) /* check next pte */ |
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cmpwi cr1,r6,1 |
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andi. r0,r0,_PAGE_HASHPTE |
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bne 33b |
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bgt cr1,81b |
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9: |
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#ifdef CONFIG_SMP |
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TLBSYNC |
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li r0,0 |
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stw r0,0(r9) /* clear mmu_hash_lock */ |
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#endif |
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19: mtmsr r10 |
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isync |
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blr |
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.previous |
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EXPORT_SYMBOL(flush_hash_pages) |
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_ASM_NOKPROBE_SYMBOL(flush_hash_pages)
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