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165 lines
4.0 KiB
165 lines
4.0 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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#ifndef _ASM_POWERPC_EXCEPTION_H |
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#define _ASM_POWERPC_EXCEPTION_H |
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/* |
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* Extracted from head_64.S |
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* |
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* PowerPC version |
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* Copyright (C) 1995-1996 Gary Thomas ([email protected]) |
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* |
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* Rewritten by Cort Dougan ([email protected]) for PReP |
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* Copyright (C) 1996 Cort Dougan <[email protected]> |
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* Adapted for Power Macintosh by Paul Mackerras. |
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* Low-level exception handlers and MMU support |
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* rewritten by Paul Mackerras. |
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* Copyright (C) 1996 Paul Mackerras. |
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* |
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* Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and |
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* Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com |
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* |
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* This file contains the low-level support and setup for the |
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* PowerPC-64 platform, including trap and interrupt dispatch. |
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*/ |
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/* |
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* The following macros define the code that appears as |
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* the prologue to each of the exception handlers. They |
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* are split into two parts to allow a single kernel binary |
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* to be used for pSeries and iSeries. |
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* |
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* We make as much of the exception code common between native |
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* exception handlers (including pSeries LPAR) and iSeries LPAR |
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* implementations as possible. |
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*/ |
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#include <asm/feature-fixups.h> |
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/* PACA save area size in u64 units (exgen, exmc, etc) */ |
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#define EX_SIZE 10 |
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/* |
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* maximum recursive depth of MCE exceptions |
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*/ |
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#define MAX_MCE_DEPTH 4 |
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#ifdef __ASSEMBLY__ |
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#define STF_ENTRY_BARRIER_SLOT \ |
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STF_ENTRY_BARRIER_FIXUP_SECTION; \ |
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nop; \ |
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nop; \ |
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nop |
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#define STF_EXIT_BARRIER_SLOT \ |
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STF_EXIT_BARRIER_FIXUP_SECTION; \ |
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nop; \ |
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nop; \ |
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nop; \ |
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nop; \ |
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nop; \ |
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nop |
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#define ENTRY_FLUSH_SLOT \ |
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ENTRY_FLUSH_FIXUP_SECTION; \ |
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nop; \ |
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nop; \ |
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nop; |
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#define SCV_ENTRY_FLUSH_SLOT \ |
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SCV_ENTRY_FLUSH_FIXUP_SECTION; \ |
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nop; \ |
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nop; \ |
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nop; |
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/* |
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* r10 must be free to use, r13 must be paca |
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*/ |
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#define INTERRUPT_TO_KERNEL \ |
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STF_ENTRY_BARRIER_SLOT; \ |
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ENTRY_FLUSH_SLOT |
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/* |
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* r10, ctr must be free to use, r13 must be paca |
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*/ |
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#define SCV_INTERRUPT_TO_KERNEL \ |
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STF_ENTRY_BARRIER_SLOT; \ |
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SCV_ENTRY_FLUSH_SLOT |
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/* |
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* Macros for annotating the expected destination of (h)rfid |
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* |
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* The nop instructions allow us to insert one or more instructions to flush the |
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* L1-D cache when returning to userspace or a guest. |
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* |
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* powerpc relies on return from interrupt/syscall being context synchronising |
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* (which hrfid, rfid, and rfscv are) to support ARCH_HAS_MEMBARRIER_SYNC_CORE |
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* without additional synchronisation instructions. |
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* |
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* soft-masked interrupt replay does not include a context-synchronising rfid, |
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* but those always return to kernel, the sync is only required when returning |
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* to user. |
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*/ |
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#define RFI_FLUSH_SLOT \ |
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RFI_FLUSH_FIXUP_SECTION; \ |
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nop; \ |
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nop; \ |
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nop |
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#define RFI_TO_KERNEL \ |
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rfid |
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#define RFI_TO_USER \ |
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STF_EXIT_BARRIER_SLOT; \ |
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RFI_FLUSH_SLOT; \ |
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rfid; \ |
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b rfi_flush_fallback |
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#define RFI_TO_USER_OR_KERNEL \ |
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STF_EXIT_BARRIER_SLOT; \ |
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RFI_FLUSH_SLOT; \ |
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rfid; \ |
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b rfi_flush_fallback |
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#define RFI_TO_GUEST \ |
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STF_EXIT_BARRIER_SLOT; \ |
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RFI_FLUSH_SLOT; \ |
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rfid; \ |
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b rfi_flush_fallback |
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#define HRFI_TO_KERNEL \ |
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hrfid |
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#define HRFI_TO_USER \ |
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STF_EXIT_BARRIER_SLOT; \ |
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RFI_FLUSH_SLOT; \ |
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hrfid; \ |
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b hrfi_flush_fallback |
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#define HRFI_TO_USER_OR_KERNEL \ |
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STF_EXIT_BARRIER_SLOT; \ |
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RFI_FLUSH_SLOT; \ |
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hrfid; \ |
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b hrfi_flush_fallback |
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#define HRFI_TO_GUEST \ |
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STF_EXIT_BARRIER_SLOT; \ |
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RFI_FLUSH_SLOT; \ |
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hrfid; \ |
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b hrfi_flush_fallback |
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#define HRFI_TO_UNKNOWN \ |
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STF_EXIT_BARRIER_SLOT; \ |
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RFI_FLUSH_SLOT; \ |
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hrfid; \ |
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b hrfi_flush_fallback |
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#define RFSCV_TO_USER \ |
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STF_EXIT_BARRIER_SLOT; \ |
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RFI_FLUSH_SLOT; \ |
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RFSCV; \ |
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b rfscv_flush_fallback |
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#else /* __ASSEMBLY__ */ |
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/* Prototype for function defined in exceptions-64s.S */ |
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void do_uaccess_flush(void); |
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#endif /* __ASSEMBLY__ */ |
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#endif /* _ASM_POWERPC_EXCEPTION_H */
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