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643 lines
14 KiB
643 lines
14 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* A small micro-assembler. It is intentionally kept simple, does only |
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* support a subset of instructions, and does not try to hide pipeline |
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* effects like branch delay slots. |
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* |
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* Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer |
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* Copyright (C) 2005, 2007 Maciej W. Rozycki |
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* Copyright (C) 2006 Ralf Baechle ([email protected]) |
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* Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. |
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*/ |
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|
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enum fields { |
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RS = 0x001, |
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RT = 0x002, |
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RD = 0x004, |
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RE = 0x008, |
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SIMM = 0x010, |
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UIMM = 0x020, |
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BIMM = 0x040, |
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JIMM = 0x080, |
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FUNC = 0x100, |
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SET = 0x200, |
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SCIMM = 0x400, |
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SIMM9 = 0x800, |
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}; |
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#define OP_MASK 0x3f |
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#define OP_SH 26 |
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#define RD_MASK 0x1f |
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#define RD_SH 11 |
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#define RE_MASK 0x1f |
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#define RE_SH 6 |
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#define IMM_MASK 0xffff |
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#define IMM_SH 0 |
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#define JIMM_MASK 0x3ffffff |
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#define JIMM_SH 0 |
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#define FUNC_MASK 0x3f |
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#define FUNC_SH 0 |
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#define SET_MASK 0x7 |
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#define SET_SH 0 |
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#define SIMM9_SH 7 |
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#define SIMM9_MASK 0x1ff |
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enum opcode { |
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insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1, |
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insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bgtz, insn_blez, |
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insn_bltz, insn_bltzl, insn_bne, insn_break, insn_cache, insn_cfc1, |
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insn_cfcmsa, insn_ctc1, insn_ctcmsa, insn_daddiu, insn_daddu, insn_ddivu, |
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insn_ddivu_r6, insn_di, insn_dins, insn_dinsm, insn_dinsu, insn_divu, |
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insn_divu_r6, insn_dmfc0, insn_dmodu, insn_dmtc0, insn_dmultu, |
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insn_dmulu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd, insn_dsll, |
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insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav, insn_dsrl, |
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insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext, insn_ins, |
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insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu, insn_ld, |
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insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, insn_ll, insn_lld, |
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insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi, |
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insn_mflo, insn_modu, insn_movn, insn_movz, insn_mtc0, insn_mthc0, |
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insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_nor, |
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insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, insn_sc, |
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insn_scd, insn_seleqz, insn_selnez, insn_sd, insn_sh, insn_sll, |
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insn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, |
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insn_srav, insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, |
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insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, |
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insn_wsbh, insn_xor, insn_xori, insn_yield, |
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insn_invalid /* insn_invalid must be last */ |
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}; |
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struct insn { |
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u32 match; |
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enum fields fields; |
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}; |
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static inline u32 build_rs(u32 arg) |
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{ |
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WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
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|
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return (arg & RS_MASK) << RS_SH; |
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} |
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static inline u32 build_rt(u32 arg) |
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{ |
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WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
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return (arg & RT_MASK) << RT_SH; |
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} |
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static inline u32 build_rd(u32 arg) |
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{ |
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WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
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return (arg & RD_MASK) << RD_SH; |
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} |
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static inline u32 build_re(u32 arg) |
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{ |
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WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
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return (arg & RE_MASK) << RE_SH; |
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} |
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static inline u32 build_simm(s32 arg) |
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{ |
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WARN(arg > 0x7fff || arg < -0x8000, |
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KERN_WARNING "Micro-assembler field overflow\n"); |
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return arg & 0xffff; |
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} |
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static inline u32 build_uimm(u32 arg) |
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{ |
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WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
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return arg & IMM_MASK; |
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} |
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static inline u32 build_scimm(u32 arg) |
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{ |
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WARN(arg & ~SCIMM_MASK, |
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KERN_WARNING "Micro-assembler field overflow\n"); |
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return (arg & SCIMM_MASK) << SCIMM_SH; |
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} |
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static inline u32 build_scimm9(s32 arg) |
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{ |
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WARN((arg > 0xff || arg < -0x100), |
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KERN_WARNING "Micro-assembler field overflow\n"); |
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return (arg & SIMM9_MASK) << SIMM9_SH; |
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} |
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static inline u32 build_func(u32 arg) |
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{ |
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WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
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return arg & FUNC_MASK; |
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} |
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static inline u32 build_set(u32 arg) |
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{ |
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WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n"); |
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return arg & SET_MASK; |
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} |
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static void build_insn(u32 **buf, enum opcode opc, ...); |
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|
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#define I_u1u2u3(op) \ |
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Ip_u1u2u3(op) \ |
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{ \ |
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build_insn(buf, insn##op, a, b, c); \ |
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} \ |
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UASM_EXPORT_SYMBOL(uasm_i##op); |
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#define I_s3s1s2(op) \ |
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Ip_s3s1s2(op) \ |
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{ \ |
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build_insn(buf, insn##op, b, c, a); \ |
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} \ |
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UASM_EXPORT_SYMBOL(uasm_i##op); |
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#define I_u2u1u3(op) \ |
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Ip_u2u1u3(op) \ |
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{ \ |
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build_insn(buf, insn##op, b, a, c); \ |
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} \ |
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UASM_EXPORT_SYMBOL(uasm_i##op); |
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#define I_u3u2u1(op) \ |
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Ip_u3u2u1(op) \ |
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{ \ |
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build_insn(buf, insn##op, c, b, a); \ |
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} \ |
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UASM_EXPORT_SYMBOL(uasm_i##op); |
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#define I_u3u1u2(op) \ |
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Ip_u3u1u2(op) \ |
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{ \ |
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build_insn(buf, insn##op, b, c, a); \ |
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} \ |
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UASM_EXPORT_SYMBOL(uasm_i##op); |
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#define I_u1u2s3(op) \ |
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Ip_u1u2s3(op) \ |
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{ \ |
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build_insn(buf, insn##op, a, b, c); \ |
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} \ |
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UASM_EXPORT_SYMBOL(uasm_i##op); |
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#define I_u2s3u1(op) \ |
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Ip_u2s3u1(op) \ |
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{ \ |
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build_insn(buf, insn##op, c, a, b); \ |
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} \ |
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UASM_EXPORT_SYMBOL(uasm_i##op); |
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#define I_u2u1s3(op) \ |
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Ip_u2u1s3(op) \ |
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{ \ |
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build_insn(buf, insn##op, b, a, c); \ |
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} \ |
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UASM_EXPORT_SYMBOL(uasm_i##op); |
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#define I_u2u1msbu3(op) \ |
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Ip_u2u1msbu3(op) \ |
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{ \ |
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build_insn(buf, insn##op, b, a, c+d-1, c); \ |
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} \ |
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UASM_EXPORT_SYMBOL(uasm_i##op); |
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#define I_u2u1msb32u3(op) \ |
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Ip_u2u1msbu3(op) \ |
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{ \ |
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build_insn(buf, insn##op, b, a, c+d-33, c); \ |
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} \ |
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UASM_EXPORT_SYMBOL(uasm_i##op); |
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#define I_u2u1msb32msb3(op) \ |
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Ip_u2u1msbu3(op) \ |
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{ \ |
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build_insn(buf, insn##op, b, a, c+d-33, c-32); \ |
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} \ |
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UASM_EXPORT_SYMBOL(uasm_i##op); |
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#define I_u2u1msbdu3(op) \ |
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Ip_u2u1msbu3(op) \ |
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{ \ |
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build_insn(buf, insn##op, b, a, d-1, c); \ |
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} \ |
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UASM_EXPORT_SYMBOL(uasm_i##op); |
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#define I_u1u2(op) \ |
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Ip_u1u2(op) \ |
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{ \ |
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build_insn(buf, insn##op, a, b); \ |
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} \ |
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UASM_EXPORT_SYMBOL(uasm_i##op); |
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#define I_u2u1(op) \ |
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Ip_u1u2(op) \ |
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{ \ |
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build_insn(buf, insn##op, b, a); \ |
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} \ |
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UASM_EXPORT_SYMBOL(uasm_i##op); |
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#define I_u1s2(op) \ |
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Ip_u1s2(op) \ |
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{ \ |
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build_insn(buf, insn##op, a, b); \ |
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} \ |
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UASM_EXPORT_SYMBOL(uasm_i##op); |
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#define I_u1(op) \ |
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Ip_u1(op) \ |
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{ \ |
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build_insn(buf, insn##op, a); \ |
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} \ |
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UASM_EXPORT_SYMBOL(uasm_i##op); |
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#define I_0(op) \ |
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Ip_0(op) \ |
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{ \ |
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build_insn(buf, insn##op); \ |
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} \ |
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UASM_EXPORT_SYMBOL(uasm_i##op); |
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I_u2u1s3(_addiu) |
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I_u3u1u2(_addu) |
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I_u2u1u3(_andi) |
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I_u3u1u2(_and) |
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I_u1u2s3(_beq) |
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I_u1u2s3(_beql) |
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I_u1s2(_bgez) |
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I_u1s2(_bgezl) |
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I_u1s2(_bgtz) |
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I_u1s2(_blez) |
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I_u1s2(_bltz) |
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I_u1s2(_bltzl) |
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I_u1u2s3(_bne) |
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I_u1(_break) |
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I_u2s3u1(_cache) |
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I_u1u2(_cfc1) |
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I_u2u1(_cfcmsa) |
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I_u1u2(_ctc1) |
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I_u2u1(_ctcmsa) |
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I_u1u2(_ddivu) |
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I_u3u1u2(_ddivu_r6) |
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I_u1u2u3(_dmfc0) |
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I_u3u1u2(_dmodu) |
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I_u1u2u3(_dmtc0) |
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I_u1u2(_dmultu) |
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I_u3u1u2(_dmulu) |
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I_u2u1s3(_daddiu) |
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I_u3u1u2(_daddu) |
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I_u1(_di); |
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I_u1u2(_divu) |
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I_u3u1u2(_divu_r6) |
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I_u2u1(_dsbh); |
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I_u2u1(_dshd); |
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I_u2u1u3(_dsll) |
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I_u2u1u3(_dsll32) |
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I_u3u2u1(_dsllv) |
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I_u2u1u3(_dsra) |
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I_u2u1u3(_dsra32) |
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I_u3u2u1(_dsrav) |
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I_u2u1u3(_dsrl) |
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I_u2u1u3(_dsrl32) |
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I_u3u2u1(_dsrlv) |
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I_u2u1u3(_drotr) |
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I_u2u1u3(_drotr32) |
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I_u3u1u2(_dsubu) |
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I_0(_eret) |
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I_u2u1msbdu3(_ext) |
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I_u2u1msbu3(_ins) |
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I_u1(_j) |
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I_u1(_jal) |
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I_u2u1(_jalr) |
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I_u1(_jr) |
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I_u2s3u1(_lb) |
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I_u2s3u1(_lbu) |
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I_u2s3u1(_ld) |
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I_u2s3u1(_lh) |
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I_u2s3u1(_lhu) |
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I_u2s3u1(_ll) |
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I_u2s3u1(_lld) |
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I_u1s2(_lui) |
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I_u2s3u1(_lw) |
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I_u2s3u1(_lwu) |
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I_u1u2u3(_mfc0) |
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I_u1u2u3(_mfhc0) |
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I_u3u1u2(_modu) |
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I_u3u1u2(_movn) |
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I_u3u1u2(_movz) |
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I_u1(_mfhi) |
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I_u1(_mflo) |
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I_u1u2u3(_mtc0) |
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I_u1u2u3(_mthc0) |
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I_u1(_mthi) |
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I_u1(_mtlo) |
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I_u3u1u2(_mul) |
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I_u1u2(_multu) |
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I_u3u1u2(_mulu) |
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I_u3u1u2(_nor) |
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I_u3u1u2(_or) |
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I_u2u1u3(_ori) |
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I_0(_rfe) |
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I_u2s3u1(_sb) |
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I_u2s3u1(_sc) |
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I_u2s3u1(_scd) |
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I_u2s3u1(_sd) |
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I_u3u1u2(_seleqz) |
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I_u3u1u2(_selnez) |
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I_u2s3u1(_sh) |
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I_u2u1u3(_sll) |
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I_u3u2u1(_sllv) |
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I_s3s1s2(_slt) |
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I_u2u1s3(_slti) |
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I_u2u1s3(_sltiu) |
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I_u3u1u2(_sltu) |
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I_u2u1u3(_sra) |
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I_u3u2u1(_srav) |
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I_u2u1u3(_srl) |
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I_u3u2u1(_srlv) |
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I_u2u1u3(_rotr) |
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I_u3u1u2(_subu) |
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I_u2s3u1(_sw) |
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I_u1(_sync) |
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I_0(_tlbp) |
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I_0(_tlbr) |
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I_0(_tlbwi) |
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I_0(_tlbwr) |
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I_u1(_wait); |
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I_u2u1(_wsbh) |
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I_u3u1u2(_xor) |
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I_u2u1u3(_xori) |
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I_u2u1(_yield) |
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I_u2u1msbu3(_dins); |
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I_u2u1msb32u3(_dinsm); |
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I_u2u1msb32msb3(_dinsu); |
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I_u1(_syscall); |
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I_u1u2s3(_bbit0); |
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I_u1u2s3(_bbit1); |
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I_u3u1u2(_lwx) |
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I_u3u1u2(_ldx) |
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I_u1u2(_ldpte) |
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I_u2u1u3(_lddir) |
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|
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#ifdef CONFIG_CPU_CAVIUM_OCTEON |
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#include <asm/octeon/octeon.h> |
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void uasm_i_pref(u32 **buf, unsigned int a, signed int b, |
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unsigned int c) |
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{ |
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if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && a <= 24 && a != 5) |
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/* |
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* As per erratum Core-14449, replace prefetches 0-4, |
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* 6-24 with 'pref 28'. |
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*/ |
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build_insn(buf, insn_pref, c, 28, b); |
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else |
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build_insn(buf, insn_pref, c, a, b); |
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} |
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UASM_EXPORT_SYMBOL(uasm_i_pref); |
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#else |
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I_u2s3u1(_pref) |
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#endif |
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|
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/* Handle labels. */ |
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void uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) |
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{ |
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(*lab)->addr = addr; |
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(*lab)->lab = lid; |
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(*lab)++; |
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} |
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UASM_EXPORT_SYMBOL(uasm_build_label); |
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|
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int uasm_in_compat_space_p(long addr) |
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{ |
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/* Is this address in 32bit compat space? */ |
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return addr == (int)addr; |
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} |
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UASM_EXPORT_SYMBOL(uasm_in_compat_space_p); |
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|
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static int uasm_rel_highest(long val) |
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{ |
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#ifdef CONFIG_64BIT |
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return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; |
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#else |
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return 0; |
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#endif |
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} |
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static int uasm_rel_higher(long val) |
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{ |
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#ifdef CONFIG_64BIT |
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return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; |
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#else |
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return 0; |
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#endif |
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} |
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int uasm_rel_hi(long val) |
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{ |
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return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; |
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} |
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UASM_EXPORT_SYMBOL(uasm_rel_hi); |
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|
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int uasm_rel_lo(long val) |
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{ |
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return ((val & 0xffff) ^ 0x8000) - 0x8000; |
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} |
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UASM_EXPORT_SYMBOL(uasm_rel_lo); |
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|
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void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr) |
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{ |
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if (!uasm_in_compat_space_p(addr)) { |
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uasm_i_lui(buf, rs, uasm_rel_highest(addr)); |
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if (uasm_rel_higher(addr)) |
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uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr)); |
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if (uasm_rel_hi(addr)) { |
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uasm_i_dsll(buf, rs, rs, 16); |
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uasm_i_daddiu(buf, rs, rs, |
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uasm_rel_hi(addr)); |
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uasm_i_dsll(buf, rs, rs, 16); |
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} else |
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uasm_i_dsll32(buf, rs, rs, 0); |
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} else |
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uasm_i_lui(buf, rs, uasm_rel_hi(addr)); |
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} |
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UASM_EXPORT_SYMBOL(UASM_i_LA_mostly); |
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|
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void UASM_i_LA(u32 **buf, unsigned int rs, long addr) |
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{ |
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UASM_i_LA_mostly(buf, rs, addr); |
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if (uasm_rel_lo(addr)) { |
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if (!uasm_in_compat_space_p(addr)) |
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uasm_i_daddiu(buf, rs, rs, |
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uasm_rel_lo(addr)); |
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else |
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uasm_i_addiu(buf, rs, rs, |
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uasm_rel_lo(addr)); |
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} |
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} |
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UASM_EXPORT_SYMBOL(UASM_i_LA); |
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|
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/* Handle relocations. */ |
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void uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid) |
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{ |
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(*rel)->addr = addr; |
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(*rel)->type = R_MIPS_PC16; |
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(*rel)->lab = lid; |
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(*rel)++; |
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} |
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UASM_EXPORT_SYMBOL(uasm_r_mips_pc16); |
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|
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static inline void __resolve_relocs(struct uasm_reloc *rel, |
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struct uasm_label *lab); |
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|
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void uasm_resolve_relocs(struct uasm_reloc *rel, |
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struct uasm_label *lab) |
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{ |
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struct uasm_label *l; |
|
|
|
for (; rel->lab != UASM_LABEL_INVALID; rel++) |
|
for (l = lab; l->lab != UASM_LABEL_INVALID; l++) |
|
if (rel->lab == l->lab) |
|
__resolve_relocs(rel, l); |
|
} |
|
UASM_EXPORT_SYMBOL(uasm_resolve_relocs); |
|
|
|
void uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end, |
|
long off) |
|
{ |
|
for (; rel->lab != UASM_LABEL_INVALID; rel++) |
|
if (rel->addr >= first && rel->addr < end) |
|
rel->addr += off; |
|
} |
|
UASM_EXPORT_SYMBOL(uasm_move_relocs); |
|
|
|
void uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end, |
|
long off) |
|
{ |
|
for (; lab->lab != UASM_LABEL_INVALID; lab++) |
|
if (lab->addr >= first && lab->addr < end) |
|
lab->addr += off; |
|
} |
|
UASM_EXPORT_SYMBOL(uasm_move_labels); |
|
|
|
void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab, |
|
u32 *first, u32 *end, u32 *target) |
|
{ |
|
long off = (long)(target - first); |
|
|
|
memcpy(target, first, (end - first) * sizeof(u32)); |
|
|
|
uasm_move_relocs(rel, first, end, off); |
|
uasm_move_labels(lab, first, end, off); |
|
} |
|
UASM_EXPORT_SYMBOL(uasm_copy_handler); |
|
|
|
int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr) |
|
{ |
|
for (; rel->lab != UASM_LABEL_INVALID; rel++) { |
|
if (rel->addr == addr |
|
&& (rel->type == R_MIPS_PC16 |
|
|| rel->type == R_MIPS_26)) |
|
return 1; |
|
} |
|
|
|
return 0; |
|
} |
|
UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay); |
|
|
|
/* Convenience functions for labeled branches. */ |
|
void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, |
|
int lid) |
|
{ |
|
uasm_r_mips_pc16(r, *p, lid); |
|
uasm_i_bltz(p, reg, 0); |
|
} |
|
UASM_EXPORT_SYMBOL(uasm_il_bltz); |
|
|
|
void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid) |
|
{ |
|
uasm_r_mips_pc16(r, *p, lid); |
|
uasm_i_b(p, 0); |
|
} |
|
UASM_EXPORT_SYMBOL(uasm_il_b); |
|
|
|
void uasm_il_beq(u32 **p, struct uasm_reloc **r, unsigned int r1, |
|
unsigned int r2, int lid) |
|
{ |
|
uasm_r_mips_pc16(r, *p, lid); |
|
uasm_i_beq(p, r1, r2, 0); |
|
} |
|
UASM_EXPORT_SYMBOL(uasm_il_beq); |
|
|
|
void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, |
|
int lid) |
|
{ |
|
uasm_r_mips_pc16(r, *p, lid); |
|
uasm_i_beqz(p, reg, 0); |
|
} |
|
UASM_EXPORT_SYMBOL(uasm_il_beqz); |
|
|
|
void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, |
|
int lid) |
|
{ |
|
uasm_r_mips_pc16(r, *p, lid); |
|
uasm_i_beqzl(p, reg, 0); |
|
} |
|
UASM_EXPORT_SYMBOL(uasm_il_beqzl); |
|
|
|
void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1, |
|
unsigned int reg2, int lid) |
|
{ |
|
uasm_r_mips_pc16(r, *p, lid); |
|
uasm_i_bne(p, reg1, reg2, 0); |
|
} |
|
UASM_EXPORT_SYMBOL(uasm_il_bne); |
|
|
|
void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, |
|
int lid) |
|
{ |
|
uasm_r_mips_pc16(r, *p, lid); |
|
uasm_i_bnez(p, reg, 0); |
|
} |
|
UASM_EXPORT_SYMBOL(uasm_il_bnez); |
|
|
|
void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, |
|
int lid) |
|
{ |
|
uasm_r_mips_pc16(r, *p, lid); |
|
uasm_i_bgezl(p, reg, 0); |
|
} |
|
UASM_EXPORT_SYMBOL(uasm_il_bgezl); |
|
|
|
void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, |
|
int lid) |
|
{ |
|
uasm_r_mips_pc16(r, *p, lid); |
|
uasm_i_bgez(p, reg, 0); |
|
} |
|
UASM_EXPORT_SYMBOL(uasm_il_bgez); |
|
|
|
void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg, |
|
unsigned int bit, int lid) |
|
{ |
|
uasm_r_mips_pc16(r, *p, lid); |
|
uasm_i_bbit0(p, reg, bit, 0); |
|
} |
|
UASM_EXPORT_SYMBOL(uasm_il_bbit0); |
|
|
|
void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg, |
|
unsigned int bit, int lid) |
|
{ |
|
uasm_r_mips_pc16(r, *p, lid); |
|
uasm_i_bbit1(p, reg, bit, 0); |
|
} |
|
UASM_EXPORT_SYMBOL(uasm_il_bbit1);
|
|
|