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532 lines
13 KiB
532 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Goramo MultiLink router platform code |
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* Copyright (C) 2006-2009 Krzysztof Halasa <[email protected]> |
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*/ |
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#include <linux/delay.h> |
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#include <linux/gpio.h> |
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#include <linux/hdlc.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/kernel.h> |
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#include <linux/pci.h> |
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#include <linux/platform_data/wan_ixp4xx_hss.h> |
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#include <linux/serial_8250.h> |
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#include <asm/mach-types.h> |
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#include <asm/mach/arch.h> |
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#include <asm/mach/flash.h> |
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#include <asm/mach/pci.h> |
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#include <asm/system_info.h> |
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#include "irqs.h" |
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#define SLOT_ETHA 0x0B /* IDSEL = AD21 */ |
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#define SLOT_ETHB 0x0C /* IDSEL = AD20 */ |
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#define SLOT_MPCI 0x0D /* IDSEL = AD19 */ |
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#define SLOT_NEC 0x0E /* IDSEL = AD18 */ |
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/* GPIO lines */ |
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#define GPIO_SCL 0 |
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#define GPIO_SDA 1 |
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#define GPIO_STR 2 |
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#define GPIO_IRQ_NEC 3 |
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#define GPIO_IRQ_ETHA 4 |
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#define GPIO_IRQ_ETHB 5 |
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#define GPIO_HSS0_DCD_N 6 |
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#define GPIO_HSS1_DCD_N 7 |
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#define GPIO_UART0_DCD 8 |
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#define GPIO_UART1_DCD 9 |
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#define GPIO_HSS0_CTS_N 10 |
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#define GPIO_HSS1_CTS_N 11 |
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#define GPIO_IRQ_MPCI 12 |
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#define GPIO_HSS1_RTS_N 13 |
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#define GPIO_HSS0_RTS_N 14 |
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/* GPIO15 is not connected */ |
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/* Control outputs from 74HC4094 */ |
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#define CONTROL_HSS0_CLK_INT 0 |
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#define CONTROL_HSS1_CLK_INT 1 |
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#define CONTROL_HSS0_DTR_N 2 |
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#define CONTROL_HSS1_DTR_N 3 |
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#define CONTROL_EXT 4 |
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#define CONTROL_AUTO_RESET 5 |
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#define CONTROL_PCI_RESET_N 6 |
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#define CONTROL_EEPROM_WC_N 7 |
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/* offsets from start of flash ROM = 0x50000000 */ |
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#define CFG_ETH0_ADDRESS 0x40 /* 6 bytes */ |
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#define CFG_ETH1_ADDRESS 0x46 /* 6 bytes */ |
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#define CFG_REV 0x4C /* u32 */ |
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#define CFG_SDRAM_SIZE 0x50 /* u32 */ |
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#define CFG_SDRAM_CONF 0x54 /* u32 */ |
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#define CFG_SDRAM_MODE 0x58 /* u32 */ |
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#define CFG_SDRAM_REFRESH 0x5C /* u32 */ |
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#define CFG_HW_BITS 0x60 /* u32 */ |
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#define CFG_HW_USB_PORTS 0x00000007 /* 0 = no NEC chip, 1-5 = ports # */ |
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#define CFG_HW_HAS_PCI_SLOT 0x00000008 |
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#define CFG_HW_HAS_ETH0 0x00000010 |
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#define CFG_HW_HAS_ETH1 0x00000020 |
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#define CFG_HW_HAS_HSS0 0x00000040 |
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#define CFG_HW_HAS_HSS1 0x00000080 |
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#define CFG_HW_HAS_UART0 0x00000100 |
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#define CFG_HW_HAS_UART1 0x00000200 |
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#define CFG_HW_HAS_EEPROM 0x00000400 |
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#define FLASH_CMD_READ_ARRAY 0xFF |
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#define FLASH_CMD_READ_ID 0x90 |
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#define FLASH_SER_OFF 0x102 /* 0x81 in 16-bit mode */ |
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static u32 hw_bits = 0xFFFFFFFD; /* assume all hardware present */; |
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static u8 control_value; |
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/* |
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* FIXME: this is reimplementing I2C bit-bangining. Move this |
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* over to using driver/i2c/busses/i2c-gpio.c like all other boards |
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* and register proper I2C device(s) on the bus for this. (See |
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* other IXP4xx boards for examples.) |
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*/ |
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static void set_scl(u8 value) |
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{ |
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gpio_set_value(GPIO_SCL, !!value); |
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udelay(3); |
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} |
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static void set_sda(u8 value) |
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{ |
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gpio_set_value(GPIO_SDA, !!value); |
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udelay(3); |
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} |
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static void set_str(u8 value) |
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{ |
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gpio_set_value(GPIO_STR, !!value); |
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udelay(3); |
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} |
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static inline void set_control(int line, int value) |
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{ |
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if (value) |
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control_value |= (1 << line); |
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else |
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control_value &= ~(1 << line); |
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} |
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static void output_control(void) |
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{ |
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int i; |
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gpio_direction_output(GPIO_SCL, 1); |
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gpio_direction_output(GPIO_SDA, 1); |
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for (i = 0; i < 8; i++) { |
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set_scl(0); |
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set_sda(control_value & (0x80 >> i)); /* MSB first */ |
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set_scl(1); /* active edge */ |
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} |
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set_str(1); |
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set_str(0); |
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set_scl(0); |
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set_sda(1); /* Be ready for START */ |
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set_scl(1); |
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} |
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static void (*set_carrier_cb_tab[2])(void *pdev, int carrier); |
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static int hss_set_clock(int port, unsigned int clock_type) |
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{ |
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int ctrl_int = port ? CONTROL_HSS1_CLK_INT : CONTROL_HSS0_CLK_INT; |
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switch (clock_type) { |
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case CLOCK_DEFAULT: |
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case CLOCK_EXT: |
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set_control(ctrl_int, 0); |
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output_control(); |
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return CLOCK_EXT; |
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case CLOCK_INT: |
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set_control(ctrl_int, 1); |
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output_control(); |
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return CLOCK_INT; |
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default: |
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return -EINVAL; |
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} |
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} |
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static irqreturn_t hss_dcd_irq(int irq, void *pdev) |
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{ |
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int port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N)); |
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int i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N); |
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set_carrier_cb_tab[port](pdev, !i); |
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return IRQ_HANDLED; |
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} |
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static int hss_open(int port, void *pdev, |
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void (*set_carrier_cb)(void *pdev, int carrier)) |
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{ |
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int i, irq; |
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if (!port) |
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irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N); |
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else |
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irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N); |
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i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N); |
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set_carrier_cb(pdev, !i); |
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set_carrier_cb_tab[!!port] = set_carrier_cb; |
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if ((i = request_irq(irq, hss_dcd_irq, 0, "IXP4xx HSS", pdev)) != 0) { |
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printk(KERN_ERR "ixp4xx_hss: failed to request IRQ%i (%i)\n", |
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irq, i); |
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return i; |
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} |
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set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 0); |
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output_control(); |
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gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 0); |
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return 0; |
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} |
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static void hss_close(int port, void *pdev) |
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{ |
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free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) : |
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IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev); |
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set_carrier_cb_tab[!!port] = NULL; /* catch bugs */ |
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set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1); |
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output_control(); |
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gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 1); |
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} |
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/* Flash memory */ |
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static struct flash_platform_data flash_data = { |
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.map_name = "cfi_probe", |
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.width = 2, |
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}; |
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static struct resource flash_resource = { |
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.flags = IORESOURCE_MEM, |
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}; |
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static struct platform_device device_flash = { |
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.name = "IXP4XX-Flash", |
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.id = 0, |
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.dev = { .platform_data = &flash_data }, |
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.num_resources = 1, |
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.resource = &flash_resource, |
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}; |
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/* IXP425 2 UART ports */ |
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static struct resource uart_resources[] = { |
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{ |
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.start = IXP4XX_UART1_BASE_PHYS, |
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.end = IXP4XX_UART1_BASE_PHYS + 0x0fff, |
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.flags = IORESOURCE_MEM, |
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}, |
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{ |
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.start = IXP4XX_UART2_BASE_PHYS, |
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.end = IXP4XX_UART2_BASE_PHYS + 0x0fff, |
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.flags = IORESOURCE_MEM, |
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} |
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}; |
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static struct plat_serial8250_port uart_data[] = { |
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{ |
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.mapbase = IXP4XX_UART1_BASE_PHYS, |
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.membase = (char __iomem *)IXP4XX_UART1_BASE_VIRT + |
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REG_OFFSET, |
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.irq = IRQ_IXP4XX_UART1, |
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, |
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.iotype = UPIO_MEM, |
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.regshift = 2, |
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.uartclk = IXP4XX_UART_XTAL, |
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}, |
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{ |
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.mapbase = IXP4XX_UART2_BASE_PHYS, |
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.membase = (char __iomem *)IXP4XX_UART2_BASE_VIRT + |
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REG_OFFSET, |
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.irq = IRQ_IXP4XX_UART2, |
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, |
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.iotype = UPIO_MEM, |
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.regshift = 2, |
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.uartclk = IXP4XX_UART_XTAL, |
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}, |
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{ }, |
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}; |
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static struct platform_device device_uarts = { |
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.name = "serial8250", |
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.id = PLAT8250_DEV_PLATFORM, |
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.dev.platform_data = uart_data, |
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.num_resources = 2, |
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.resource = uart_resources, |
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}; |
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/* Built-in 10/100 Ethernet MAC interfaces */ |
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static struct resource eth_npeb_resources[] = { |
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{ |
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.start = IXP4XX_EthB_BASE_PHYS, |
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.end = IXP4XX_EthB_BASE_PHYS + 0x0fff, |
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.flags = IORESOURCE_MEM, |
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}, |
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}; |
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static struct resource eth_npec_resources[] = { |
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{ |
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.start = IXP4XX_EthC_BASE_PHYS, |
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.end = IXP4XX_EthC_BASE_PHYS + 0x0fff, |
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.flags = IORESOURCE_MEM, |
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}, |
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}; |
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static struct eth_plat_info eth_plat[] = { |
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{ |
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.phy = 0, |
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.rxq = 3, |
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.txreadyq = 32, |
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}, { |
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.phy = 1, |
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.rxq = 4, |
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.txreadyq = 33, |
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} |
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}; |
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static struct platform_device device_eth_tab[] = { |
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{ |
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.name = "ixp4xx_eth", |
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.id = IXP4XX_ETH_NPEB, |
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.dev.platform_data = eth_plat, |
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.num_resources = ARRAY_SIZE(eth_npeb_resources), |
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.resource = eth_npeb_resources, |
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}, { |
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.name = "ixp4xx_eth", |
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.id = IXP4XX_ETH_NPEC, |
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.dev.platform_data = eth_plat + 1, |
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.num_resources = ARRAY_SIZE(eth_npec_resources), |
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.resource = eth_npec_resources, |
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} |
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}; |
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/* IXP425 2 synchronous serial ports */ |
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static struct hss_plat_info hss_plat[] = { |
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{ |
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.set_clock = hss_set_clock, |
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.open = hss_open, |
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.close = hss_close, |
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.txreadyq = 34, |
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}, { |
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.set_clock = hss_set_clock, |
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.open = hss_open, |
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.close = hss_close, |
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.txreadyq = 35, |
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} |
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}; |
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static struct platform_device device_hss_tab[] = { |
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{ |
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.name = "ixp4xx_hss", |
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.id = 0, |
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.dev.platform_data = hss_plat, |
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}, { |
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.name = "ixp4xx_hss", |
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.id = 1, |
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.dev.platform_data = hss_plat + 1, |
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} |
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}; |
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static struct platform_device *device_tab[7] __initdata = { |
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&device_flash, /* index 0 */ |
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}; |
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static inline u8 __init flash_readb(u8 __iomem *flash, u32 addr) |
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{ |
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#ifdef __ARMEB__ |
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return __raw_readb(flash + addr); |
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#else |
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return __raw_readb(flash + (addr ^ 3)); |
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#endif |
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} |
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static inline u16 __init flash_readw(u8 __iomem *flash, u32 addr) |
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{ |
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#ifdef __ARMEB__ |
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return __raw_readw(flash + addr); |
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#else |
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return __raw_readw(flash + (addr ^ 2)); |
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#endif |
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} |
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static void __init gmlr_init(void) |
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{ |
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u8 __iomem *flash; |
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int i, devices = 1; /* flash */ |
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ixp4xx_sys_init(); |
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if ((flash = ioremap(IXP4XX_EXP_BUS_BASE_PHYS, 0x80)) == NULL) |
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printk(KERN_ERR "goramo-mlr: unable to access system" |
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" configuration data\n"); |
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else { |
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system_rev = __raw_readl(flash + CFG_REV); |
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hw_bits = __raw_readl(flash + CFG_HW_BITS); |
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for (i = 0; i < ETH_ALEN; i++) { |
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eth_plat[0].hwaddr[i] = |
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flash_readb(flash, CFG_ETH0_ADDRESS + i); |
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eth_plat[1].hwaddr[i] = |
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flash_readb(flash, CFG_ETH1_ADDRESS + i); |
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} |
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__raw_writew(FLASH_CMD_READ_ID, flash); |
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system_serial_high = flash_readw(flash, FLASH_SER_OFF); |
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system_serial_high <<= 16; |
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system_serial_high |= flash_readw(flash, FLASH_SER_OFF + 2); |
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system_serial_low = flash_readw(flash, FLASH_SER_OFF + 4); |
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system_serial_low <<= 16; |
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system_serial_low |= flash_readw(flash, FLASH_SER_OFF + 6); |
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__raw_writew(FLASH_CMD_READ_ARRAY, flash); |
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iounmap(flash); |
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} |
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switch (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) { |
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case CFG_HW_HAS_UART0: |
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memset(&uart_data[1], 0, sizeof(uart_data[1])); |
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device_uarts.num_resources = 1; |
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break; |
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case CFG_HW_HAS_UART1: |
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device_uarts.dev.platform_data = &uart_data[1]; |
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device_uarts.resource = &uart_resources[1]; |
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device_uarts.num_resources = 1; |
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break; |
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} |
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if (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) |
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device_tab[devices++] = &device_uarts; /* max index 1 */ |
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if (hw_bits & CFG_HW_HAS_ETH0) |
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device_tab[devices++] = &device_eth_tab[0]; /* max index 2 */ |
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if (hw_bits & CFG_HW_HAS_ETH1) |
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device_tab[devices++] = &device_eth_tab[1]; /* max index 3 */ |
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if (hw_bits & CFG_HW_HAS_HSS0) |
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device_tab[devices++] = &device_hss_tab[0]; /* max index 4 */ |
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if (hw_bits & CFG_HW_HAS_HSS1) |
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device_tab[devices++] = &device_hss_tab[1]; /* max index 5 */ |
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hss_plat[0].timer_freq = ixp4xx_timer_freq; |
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hss_plat[1].timer_freq = ixp4xx_timer_freq; |
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gpio_request(GPIO_SCL, "SCL/clock"); |
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gpio_request(GPIO_SDA, "SDA/data"); |
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gpio_request(GPIO_STR, "strobe"); |
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gpio_request(GPIO_HSS0_RTS_N, "HSS0 RTS"); |
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gpio_request(GPIO_HSS1_RTS_N, "HSS1 RTS"); |
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gpio_request(GPIO_HSS0_DCD_N, "HSS0 DCD"); |
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gpio_request(GPIO_HSS1_DCD_N, "HSS1 DCD"); |
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gpio_direction_output(GPIO_SCL, 1); |
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gpio_direction_output(GPIO_SDA, 1); |
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gpio_direction_output(GPIO_STR, 0); |
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gpio_direction_output(GPIO_HSS0_RTS_N, 1); |
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gpio_direction_output(GPIO_HSS1_RTS_N, 1); |
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gpio_direction_input(GPIO_HSS0_DCD_N); |
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gpio_direction_input(GPIO_HSS1_DCD_N); |
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irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); |
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irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); |
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set_control(CONTROL_HSS0_DTR_N, 1); |
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set_control(CONTROL_HSS1_DTR_N, 1); |
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set_control(CONTROL_EEPROM_WC_N, 1); |
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set_control(CONTROL_PCI_RESET_N, 1); |
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output_control(); |
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msleep(1); /* Wait for PCI devices to initialize */ |
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flash_resource.start = IXP4XX_EXP_BUS_BASE(0); |
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flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; |
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platform_add_devices(device_tab, devices); |
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} |
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#ifdef CONFIG_PCI |
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static void __init gmlr_pci_preinit(void) |
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{ |
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irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); |
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irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); |
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irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); |
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irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); |
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ixp4xx_pci_preinit(); |
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} |
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static void __init gmlr_pci_postinit(void) |
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{ |
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if ((hw_bits & CFG_HW_USB_PORTS) >= 2 && |
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(hw_bits & CFG_HW_USB_PORTS) < 5) { |
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/* need to adjust number of USB ports on NEC chip */ |
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u32 value, addr = BIT(32 - SLOT_NEC) | 0xE0; |
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if (!ixp4xx_pci_read(addr, NP_CMD_CONFIGREAD, &value)) { |
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value &= ~7; |
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value |= (hw_bits & CFG_HW_USB_PORTS); |
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ixp4xx_pci_write(addr, NP_CMD_CONFIGWRITE, value); |
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} |
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} |
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} |
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static int __init gmlr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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switch(slot) { |
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case SLOT_ETHA: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA); |
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case SLOT_ETHB: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB); |
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case SLOT_NEC: return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC); |
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default: return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI); |
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} |
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} |
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static struct hw_pci gmlr_hw_pci __initdata = { |
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.nr_controllers = 1, |
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.ops = &ixp4xx_ops, |
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.preinit = gmlr_pci_preinit, |
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.postinit = gmlr_pci_postinit, |
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.setup = ixp4xx_setup, |
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.map_irq = gmlr_map_irq, |
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}; |
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static int __init gmlr_pci_init(void) |
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{ |
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if (machine_is_goramo_mlr() && |
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(hw_bits & (CFG_HW_USB_PORTS | CFG_HW_HAS_PCI_SLOT))) |
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pci_common_init(&gmlr_hw_pci); |
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return 0; |
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} |
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subsys_initcall(gmlr_pci_init); |
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#endif /* CONFIG_PCI */ |
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MACHINE_START(GORAMO_MLR, "MultiLink") |
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/* Maintainer: Krzysztof Halasa */ |
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.map_io = ixp4xx_map_io, |
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.init_early = ixp4xx_init_early, |
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.init_irq = ixp4xx_init_irq, |
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.init_time = ixp4xx_timer_init, |
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.atag_offset = 0x100, |
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.init_machine = gmlr_init, |
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#if defined(CONFIG_PCI) |
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.dma_zone_size = SZ_64M, |
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#endif |
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.restart = ixp4xx_restart, |
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MACHINE_END
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