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67 lines
1.6 KiB
67 lines
1.6 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Microchip Sparx5 Mobile Storage Host Controller Binding |
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allOf: |
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- $ref: "mmc-controller.yaml" |
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maintainers: |
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- Lars Povlsen <[email protected]> |
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# Everything else is described in the common file |
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properties: |
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compatible: |
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const: microchip,dw-sparx5-sdhci |
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reg: |
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maxItems: 1 |
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interrupts: |
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maxItems: 1 |
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clocks: |
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maxItems: 1 |
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description: |
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Handle to "core" clock for the sdhci controller. |
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clock-names: |
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items: |
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- const: core |
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microchip,clock-delay: |
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description: Delay clock to card to meet setup time requirements. |
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Each step increase by 1.25ns. |
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$ref: "/schemas/types.yaml#/definitions/uint32" |
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minimum: 1 |
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maximum: 15 |
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required: |
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- compatible |
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- reg |
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- interrupts |
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- clocks |
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- clock-names |
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unevaluatedProperties: false |
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examples: |
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- | |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/clock/microchip,sparx5.h> |
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sdhci0: mmc@600800000 { |
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compatible = "microchip,dw-sparx5-sdhci"; |
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reg = <0x00800000 0x1000>; |
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pinctrl-0 = <&emmc_pins>; |
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pinctrl-names = "default"; |
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clocks = <&clks CLK_ID_AUX1>; |
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clock-names = "core"; |
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assigned-clocks = <&clks CLK_ID_AUX1>; |
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assigned-clock-rates = <800000000>; |
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
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bus-width = <8>; |
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microchip,clock-delay = <10>; |
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};
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