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32 lines
1.1 KiB
32 lines
1.1 KiB
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ |
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/* |
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* Copyright (c) 2022 MediaTek Inc. |
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* Author: Chun-Jie Chen <[email protected]> |
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*/ |
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#ifndef _DT_BINDINGS_POWER_MT8186_POWER_H |
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#define _DT_BINDINGS_POWER_MT8186_POWER_H |
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#define MT8186_POWER_DOMAIN_MFG0 0 |
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#define MT8186_POWER_DOMAIN_MFG1 1 |
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#define MT8186_POWER_DOMAIN_MFG2 2 |
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#define MT8186_POWER_DOMAIN_MFG3 3 |
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#define MT8186_POWER_DOMAIN_SSUSB 4 |
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#define MT8186_POWER_DOMAIN_SSUSB_P1 5 |
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#define MT8186_POWER_DOMAIN_DIS 6 |
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#define MT8186_POWER_DOMAIN_IMG 7 |
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#define MT8186_POWER_DOMAIN_IMG2 8 |
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#define MT8186_POWER_DOMAIN_IPE 9 |
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#define MT8186_POWER_DOMAIN_CAM 10 |
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#define MT8186_POWER_DOMAIN_CAM_RAWA 11 |
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#define MT8186_POWER_DOMAIN_CAM_RAWB 12 |
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#define MT8186_POWER_DOMAIN_VENC 13 |
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#define MT8186_POWER_DOMAIN_VDEC 14 |
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#define MT8186_POWER_DOMAIN_WPE 15 |
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#define MT8186_POWER_DOMAIN_CONN_ON 16 |
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#define MT8186_POWER_DOMAIN_CSIRX_TOP 17 |
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#define MT8186_POWER_DOMAIN_ADSP_AO 18 |
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#define MT8186_POWER_DOMAIN_ADSP_INFRA 19 |
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#define MT8186_POWER_DOMAIN_ADSP_TOP 20 |
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#endif /* _DT_BINDINGS_POWER_MT8186_POWER_H */
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