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127 lines
4.7 KiB
127 lines
4.7 KiB
/* SPDX-License-Identifier: GPL-2.0+ */ |
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/* |
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* (C) 2015 Siarhei Siamashka <[email protected]> |
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*/ |
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/* |
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* Support for the SSD2828 bridge chip, which can take pixel data coming |
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* from a parallel LCD interface and translate it on the flight into MIPI DSI |
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* interface for driving a MIPI compatible TFT display. |
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* |
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* Implemented as a utility function. To be used from display drivers, which are |
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* responsible for driving parallel LCD hardware in front of the video pipeline. |
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*/ |
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#ifndef _SSD2828_H |
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#define _SSD2828_H |
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struct ctfb_res_modes; |
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struct ssd2828_config { |
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/*********************************************************************/ |
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/* SSD2828 configuration */ |
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/*********************************************************************/ |
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/* |
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* The pins, which are used for SPI communication. This is only used |
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* for configuring SSD2828, so the performance is irrelevant (only |
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* around a hundred of bytes is moved). Also these can be any arbitrary |
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* GPIO pins (not necessarily the pins having hardware SPI function). |
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* Moreover, the 'sdo' pin may be even not wired up in some devices. |
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* |
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* These configuration variables need to be set as pin numbers for |
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* the standard u-boot GPIO interface (gpio_get_value/gpio_set_value |
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* functions). Note that -1 value can be used for the pins, which are |
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* not really wired up. |
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*/ |
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int csx_pin; |
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int sck_pin; |
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int sdi_pin; |
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int sdo_pin; |
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/* SSD2828 reset pin (shared with LCD panel reset) */ |
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int reset_pin; |
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/* |
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* The SSD2828 has its own dedicated clock source 'tx_clk' (connected |
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* to TX_CLK_XIO/TX_CLK_XIN pins), which is necessary at least for |
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* clocking SPI after reset. The exact clock speed is not strictly, |
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* defined, but the datasheet says that it must be somewhere in the |
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* 8MHz - 30MHz range (see "TX_CLK Timing" section). It can be also |
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* used as a reference clock for PLL. If the exact clock frequency |
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* is known, then it can be specified here. If it is unknown, or the |
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* information is not trustworthy, then it can be set to 0. |
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* |
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* If unsure, set to 0. |
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*/ |
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int ssd2828_tx_clk_khz; |
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/* |
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* This is not a property of the used LCD panel, but more like a |
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* property of the SSD2828 wiring. See the "SSD2828QN4 RGB data |
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* arrangement" table in the datasheet. The SSD2828 pins are arranged |
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* in such a way that 18bpp and 24bpp configurations are completely |
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* incompatible with each other. |
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* |
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* Depending on the color depth, this must be set to 16, 18 or 24. |
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*/ |
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int ssd2828_color_depth; |
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/*********************************************************************/ |
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/* LCD panel configuration */ |
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/*********************************************************************/ |
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/* |
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* The number of lanes in the MIPI DSI interface. May vary from 1 to 4. |
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* |
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* This information can be found in the LCD panel datasheet. |
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*/ |
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int mipi_dsi_number_of_data_lanes; |
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/* |
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* Data transfer bit rate per lane. Please note that it is expected |
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* to be higher than the pixel clock rate of the used video mode when |
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* multiplied by the number of lanes. This is perfectly normal because |
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* MIPI DSI handles data transfers in periodic bursts, and uses the |
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* idle time between bursts for sending configuration information and |
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* commands. Or just for saving power. |
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* |
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* The necessary Mbps/lane information can be found in the LCD panel |
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* datasheet. Note that the transfer rate can't be always set precisely |
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* and it may be rounded *up* (introducing no more than 10Mbps error). |
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*/ |
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int mipi_dsi_bitrate_per_data_lane_mbps; |
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/* |
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* Setting this to 1 enforces packing of 18bpp pixel data in 24bpp |
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* envelope when sending it over the MIPI DSI link. |
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* |
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* If unsure, set to 0. |
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*/ |
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int mipi_dsi_loosely_packed_pixel_format; |
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/* |
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* According to the "Example for system sleep in and out" section in |
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* the SSD2828 datasheet, some LCD panel specific delays are necessary |
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* after MIPI DCS commands EXIT_SLEEP_MODE and SET_DISPLAY_ON. |
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* |
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* For example, Allwinner uses 100 milliseconds delay after |
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* EXIT_SLEEP_MODE and 200 milliseconds delay after SET_DISPLAY_ON. |
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*/ |
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int mipi_dsi_delay_after_exit_sleep_mode_ms; |
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int mipi_dsi_delay_after_set_display_on_ms; |
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}; |
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/* |
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* Initialize the SSD2828 chip. It needs the 'ssd2828_config' structure |
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* and also the video mode timings. |
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* |
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* The right place to insert this function call is after the parallel LCD |
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* interface is initialized and before turning on the backlight. This is |
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* advised in the "Example for system sleep in and out" section of the |
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* SSD2828 datasheet. And also SS2828 may use 'pclk' as the clock source |
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* for PLL, which means that the input signal must be already there. |
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*/ |
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int ssd2828_init(const struct ssd2828_config *cfg, |
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const struct ctfb_res_modes *mode); |
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#endif
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