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282 lines
6.7 KiB
282 lines
6.7 KiB
#ifndef __ATI_RADEON_FB_H |
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#define __ATI_RADEON_FB_H |
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/*************************************************************** |
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* Most of the definitions here are adapted right from XFree86 * |
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***************************************************************/ |
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/* |
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* Chip families. Must fit in the low 16 bits of a long word |
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*/ |
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enum radeon_family { |
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CHIP_FAMILY_UNKNOW, |
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CHIP_FAMILY_LEGACY, |
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CHIP_FAMILY_RADEON, |
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CHIP_FAMILY_RV100, |
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CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ |
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CHIP_FAMILY_RV200, |
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CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), |
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RS250 (IGP 7000) */ |
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CHIP_FAMILY_R200, |
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CHIP_FAMILY_RV250, |
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CHIP_FAMILY_RS300, /* Radeon 9000 IGP */ |
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CHIP_FAMILY_RV280, |
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CHIP_FAMILY_R300, |
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CHIP_FAMILY_R350, |
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CHIP_FAMILY_RV350, |
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CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ |
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CHIP_FAMILY_R420, /* R420/R423/M18 */ |
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CHIP_FAMILY_LAST, |
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}; |
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#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \ |
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((rinfo)->family == CHIP_FAMILY_RV200) || \ |
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((rinfo)->family == CHIP_FAMILY_RS100) || \ |
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((rinfo)->family == CHIP_FAMILY_RS200) || \ |
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((rinfo)->family == CHIP_FAMILY_RV250) || \ |
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((rinfo)->family == CHIP_FAMILY_RV280) || \ |
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((rinfo)->family == CHIP_FAMILY_RS300)) |
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#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \ |
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((rinfo)->family == CHIP_FAMILY_RV350) || \ |
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((rinfo)->family == CHIP_FAMILY_R350) || \ |
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((rinfo)->family == CHIP_FAMILY_RV380) || \ |
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((rinfo)->family == CHIP_FAMILY_R420)) |
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struct radeonfb_info { |
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char name[20]; |
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struct pci_device_id pdev; |
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u16 family; |
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u32 fb_base_bus; |
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u32 mmio_base_bus; |
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void *mmio_base; |
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void *fb_base; |
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u32 video_ram; |
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u32 mapped_vram; |
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int vram_width; |
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int vram_ddr; |
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u32 fb_local_base; |
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}; |
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#define INREG8(addr) readb((rinfo->mmio_base)+addr) |
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#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) |
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#define INREG16(addr) readw((rinfo->mmio_base)+addr) |
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#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) |
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#define INREG(addr) readl((rinfo->mmio_base)+addr) |
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#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) |
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static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, |
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u32 val, u32 mask) |
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{ |
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unsigned int tmp; |
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tmp = INREG(addr); |
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tmp &= (mask); |
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tmp |= (val); |
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OUTREG(addr, tmp); |
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} |
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#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask) |
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/* |
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* 2D Engine helper routines |
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*/ |
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static inline void radeon_engine_flush (struct radeonfb_info *rinfo) |
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{ |
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int i; |
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/* initiate flush */ |
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OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, |
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~RB2D_DC_FLUSH_ALL); |
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for (i=0; i < 2000000; i++) { |
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if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) |
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return; |
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udelay(1); |
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} |
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printf("radeonfb: Flush Timeout !\n"); |
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} |
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static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) |
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{ |
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int i; |
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for (i=0; i<2000000; i++) { |
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if ((INREG(RBBM_STATUS) & 0x7f) >= entries) |
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return; |
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udelay(1); |
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} |
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printf("radeonfb: FIFO Timeout !\n"); |
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} |
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static inline void _radeon_engine_idle(struct radeonfb_info *rinfo) |
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{ |
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int i; |
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/* ensure FIFO is empty before waiting for idle */ |
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_radeon_fifo_wait (rinfo, 64); |
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for (i=0; i<2000000; i++) { |
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if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { |
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radeon_engine_flush (rinfo); |
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return; |
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} |
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udelay(1); |
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} |
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printf("radeonfb: Idle Timeout !\n"); |
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} |
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#define radeon_engine_idle() _radeon_engine_idle(rinfo) |
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#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries) |
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#define radeon_msleep(ms) _radeon_msleep(rinfo,ms) |
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/* |
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* This structure contains the various registers manipulated by this |
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* driver for setting or restoring a mode. It's mostly copied from |
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* XFree's RADEONSaveRec structure. A few chip settings might still be |
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* tweaked without beeing reflected or saved in these registers though |
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*/ |
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struct radeon_regs { |
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/* Common registers */ |
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u32 ovr_clr; |
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u32 ovr_wid_left_right; |
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u32 ovr_wid_top_bottom; |
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u32 ov0_scale_cntl; |
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u32 mpp_tb_config; |
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u32 mpp_gp_config; |
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u32 subpic_cntl; |
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u32 viph_control; |
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u32 i2c_cntl_1; |
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u32 gen_int_cntl; |
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u32 cap0_trig_cntl; |
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u32 cap1_trig_cntl; |
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u32 bus_cntl; |
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u32 surface_cntl; |
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u32 bios_5_scratch; |
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/* Other registers to save for VT switches or driver load/unload */ |
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u32 dp_datatype; |
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u32 rbbm_soft_reset; |
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u32 clock_cntl_index; |
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u32 amcgpio_en_reg; |
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u32 amcgpio_mask; |
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/* Surface/tiling registers */ |
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u32 surf_lower_bound[8]; |
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u32 surf_upper_bound[8]; |
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u32 surf_info[8]; |
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/* CRTC registers */ |
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u32 crtc_gen_cntl; |
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u32 crtc_ext_cntl; |
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u32 dac_cntl; |
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u32 crtc_h_total_disp; |
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u32 crtc_h_sync_strt_wid; |
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u32 crtc_v_total_disp; |
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u32 crtc_v_sync_strt_wid; |
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u32 crtc_offset; |
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u32 crtc_offset_cntl; |
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u32 crtc_pitch; |
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u32 disp_merge_cntl; |
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u32 grph_buffer_cntl; |
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u32 crtc_more_cntl; |
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/* CRTC2 registers */ |
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u32 crtc2_gen_cntl; |
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u32 dac2_cntl; |
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u32 disp_output_cntl; |
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u32 disp_hw_debug; |
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u32 disp2_merge_cntl; |
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u32 grph2_buffer_cntl; |
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u32 crtc2_h_total_disp; |
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u32 crtc2_h_sync_strt_wid; |
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u32 crtc2_v_total_disp; |
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u32 crtc2_v_sync_strt_wid; |
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u32 crtc2_offset; |
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u32 crtc2_offset_cntl; |
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u32 crtc2_pitch; |
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/* Flat panel regs */ |
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u32 fp_crtc_h_total_disp; |
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u32 fp_crtc_v_total_disp; |
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u32 fp_gen_cntl; |
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u32 fp2_gen_cntl; |
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u32 fp_h_sync_strt_wid; |
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u32 fp2_h_sync_strt_wid; |
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u32 fp_horz_stretch; |
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u32 fp_panel_cntl; |
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u32 fp_v_sync_strt_wid; |
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u32 fp2_v_sync_strt_wid; |
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u32 fp_vert_stretch; |
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u32 lvds_gen_cntl; |
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u32 lvds_pll_cntl; |
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u32 tmds_crc; |
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u32 tmds_transmitter_cntl; |
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/* Computed values for PLL */ |
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u32 dot_clock_freq; |
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int feedback_div; |
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int post_div; |
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/* PLL registers */ |
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u32 ppll_div_3; |
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u32 ppll_ref_div; |
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u32 vclk_ecp_cntl; |
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u32 clk_cntl_index; |
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/* Computed values for PLL2 */ |
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u32 dot_clock_freq_2; |
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int feedback_div_2; |
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int post_div_2; |
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/* PLL2 registers */ |
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u32 p2pll_ref_div; |
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u32 p2pll_div_0; |
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u32 htotal_cntl2; |
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/* Palette */ |
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int palette_valid; |
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}; |
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static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr) |
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{ |
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u32 data; |
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OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); |
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/* radeon_pll_errata_after_index(rinfo); */ |
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data = INREG(CLOCK_CNTL_DATA); |
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/* radeon_pll_errata_after_data(rinfo); */ |
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return data; |
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} |
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static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, |
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u32 val) |
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{ |
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OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); |
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/* radeon_pll_errata_after_index(rinfo); */ |
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OUTREG(CLOCK_CNTL_DATA, val); |
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/* radeon_pll_errata_after_data(rinfo); */ |
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} |
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static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index, |
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u32 val, u32 mask) |
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{ |
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unsigned int tmp; |
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tmp = __INPLL(rinfo, index); |
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tmp &= (mask); |
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tmp |= (val); |
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__OUTPLL(rinfo, index, tmp); |
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} |
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#define INPLL(addr) __INPLL(rinfo, addr) |
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#define OUTPLL(index, val) __OUTPLL(rinfo, index, val) |
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#define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask) |
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#endif
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