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222 lines
4.6 KiB
222 lines
4.6 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* (C) Copyright 2009-2012 ADVANSEE |
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* Benoît Thébaudeau <[email protected]> |
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* |
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* Based on the Linux rtc-imxdi.c driver, which is: |
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* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. |
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* Copyright 2010 Orex Computed Radiography |
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*/ |
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/* |
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* Date & Time support for Freescale i.MX DryIce RTC |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <linux/compat.h> |
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#include <rtc.h> |
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#include <asm/io.h> |
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#include <asm/arch/imx-regs.h> |
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/* DryIce Register Definitions */ |
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struct imxdi_regs { |
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u32 dtcmr; /* Time Counter MSB Reg */ |
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u32 dtclr; /* Time Counter LSB Reg */ |
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u32 dcamr; /* Clock Alarm MSB Reg */ |
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u32 dcalr; /* Clock Alarm LSB Reg */ |
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u32 dcr; /* Control Reg */ |
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u32 dsr; /* Status Reg */ |
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u32 dier; /* Interrupt Enable Reg */ |
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}; |
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#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */ |
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#define DCR_TCE (1 << 3) /* Time Counter Enable */ |
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#define DSR_WBF (1 << 10) /* Write Busy Flag */ |
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#define DSR_WNF (1 << 9) /* Write Next Flag */ |
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#define DSR_WCF (1 << 8) /* Write Complete Flag */ |
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#define DSR_WEF (1 << 7) /* Write Error Flag */ |
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#define DSR_CAF (1 << 4) /* Clock Alarm Flag */ |
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#define DSR_NVF (1 << 1) /* Non-Valid Flag */ |
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#define DSR_SVF (1 << 0) /* Security Violation Flag */ |
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#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */ |
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#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */ |
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#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */ |
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#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */ |
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/* Driver Private Data */ |
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struct imxdi_data { |
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struct imxdi_regs __iomem *regs; |
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int init_done; |
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}; |
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static struct imxdi_data data; |
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/* |
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* This function attempts to clear the dryice write-error flag. |
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* |
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* A dryice write error is similar to a bus fault and should not occur in |
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* normal operation. Clearing the flag requires another write, so the root |
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* cause of the problem may need to be fixed before the flag can be cleared. |
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*/ |
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static void clear_write_error(void) |
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{ |
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int cnt; |
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puts("### Warning: RTC - Register write error!\n"); |
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/* clear the write error flag */ |
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__raw_writel(DSR_WEF, &data.regs->dsr); |
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/* wait for it to take effect */ |
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for (cnt = 0; cnt < 1000; cnt++) { |
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if ((__raw_readl(&data.regs->dsr) & DSR_WEF) == 0) |
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return; |
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udelay(10); |
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} |
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puts("### Error: RTC - Cannot clear write-error flag!\n"); |
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} |
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/* |
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* Write a dryice register and wait until it completes. |
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* |
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* Use interrupt flags to determine when the write has completed. |
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*/ |
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#define DI_WRITE_WAIT(val, reg) \ |
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( \ |
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/* do the register write */ \ |
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__raw_writel((val), &data.regs->reg), \ |
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\ |
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di_write_wait((val), #reg) \ |
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) |
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static int di_write_wait(u32 val, const char *reg) |
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{ |
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int cnt; |
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int ret = 0; |
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int rc = 0; |
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/* wait for the write to finish */ |
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for (cnt = 0; cnt < 100; cnt++) { |
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if ((__raw_readl(&data.regs->dsr) & (DSR_WCF | DSR_WEF)) != 0) { |
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ret = 1; |
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break; |
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} |
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udelay(10); |
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} |
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if (ret == 0) |
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printf("### Warning: RTC - Write-wait timeout " |
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"val = 0x%.8x reg = %s\n", val, reg); |
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/* check for write error */ |
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if (__raw_readl(&data.regs->dsr) & DSR_WEF) { |
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clear_write_error(); |
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rc = -1; |
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} |
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return rc; |
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} |
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/* |
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* Initialize dryice hardware |
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*/ |
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static int di_init(void) |
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{ |
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int rc = 0; |
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data.regs = (struct imxdi_regs __iomem *)IMX_DRYICE_BASE; |
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/* mask all interrupts */ |
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__raw_writel(0, &data.regs->dier); |
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/* put dryice into valid state */ |
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if (__raw_readl(&data.regs->dsr) & DSR_NVF) { |
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rc = DI_WRITE_WAIT(DSR_NVF | DSR_SVF, dsr); |
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if (rc) |
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goto err; |
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} |
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/* initialize alarm */ |
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rc = DI_WRITE_WAIT(DCAMR_UNSET, dcamr); |
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if (rc) |
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goto err; |
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rc = DI_WRITE_WAIT(0, dcalr); |
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if (rc) |
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goto err; |
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/* clear alarm flag */ |
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if (__raw_readl(&data.regs->dsr) & DSR_CAF) { |
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rc = DI_WRITE_WAIT(DSR_CAF, dsr); |
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if (rc) |
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goto err; |
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} |
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/* the timer won't count if it has never been written to */ |
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if (__raw_readl(&data.regs->dtcmr) == 0) { |
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rc = DI_WRITE_WAIT(0, dtcmr); |
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if (rc) |
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goto err; |
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} |
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/* start keeping time */ |
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if (!(__raw_readl(&data.regs->dcr) & DCR_TCE)) { |
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rc = DI_WRITE_WAIT(__raw_readl(&data.regs->dcr) | DCR_TCE, dcr); |
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if (rc) |
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goto err; |
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} |
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data.init_done = 1; |
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return 0; |
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err: |
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return rc; |
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} |
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int rtc_get(struct rtc_time *tmp) |
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{ |
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unsigned long now; |
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int rc = 0; |
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if (!data.init_done) { |
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rc = di_init(); |
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if (rc) |
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goto err; |
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} |
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now = __raw_readl(&data.regs->dtcmr); |
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rtc_to_tm(now, tmp); |
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err: |
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return rc; |
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} |
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int rtc_set(struct rtc_time *tmp) |
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{ |
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unsigned long now; |
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int rc; |
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if (!data.init_done) { |
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rc = di_init(); |
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if (rc) |
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goto err; |
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} |
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now = rtc_mktime(tmp); |
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/* zero the fractional part first */ |
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rc = DI_WRITE_WAIT(0, dtclr); |
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if (rc == 0) |
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rc = DI_WRITE_WAIT(now, dtcmr); |
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err: |
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return rc; |
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} |
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void rtc_reset(void) |
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{ |
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di_init(); |
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}
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