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374 lines
10 KiB
374 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright (C) 2016 Socionext Inc. |
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* Author: Masahiro Yamada <[email protected]> |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <reset-uclass.h> |
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#include <linux/bitops.h> |
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#include <linux/io.h> |
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#include <linux/sizes.h> |
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struct uniphier_reset_data { |
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unsigned int id; |
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unsigned int reg; |
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unsigned int bit; |
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unsigned int flags; |
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#define UNIPHIER_RESET_ACTIVE_LOW BIT(0) |
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}; |
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#define UNIPHIER_RESET_ID_END (unsigned int)(-1) |
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#define UNIPHIER_RESET_END \ |
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{ .id = UNIPHIER_RESET_ID_END } |
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#define UNIPHIER_RESET(_id, _reg, _bit) \ |
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{ \ |
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.id = (_id), \ |
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.reg = (_reg), \ |
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.bit = (_bit), \ |
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} |
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#define UNIPHIER_RESETX(_id, _reg, _bit) \ |
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{ \ |
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.id = (_id), \ |
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.reg = (_reg), \ |
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.bit = (_bit), \ |
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.flags = UNIPHIER_RESET_ACTIVE_LOW, \ |
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} |
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/* System reset data */ |
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static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { |
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UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */ |
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UNIPHIER_RESETX(6, 0x2000, 12), /* ETHER */ |
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UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */ |
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UNIPHIER_RESETX(12, 0x2000, 6), /* GIO */ |
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UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */ |
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UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */ |
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UNIPHIER_RESET_END, |
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}; |
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static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { |
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UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */ |
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UNIPHIER_RESETX(6, 0x2000, 12), /* ETHER */ |
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UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */ |
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UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */ |
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UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */ |
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UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */ |
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UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */ |
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UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */ |
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UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */ |
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UNIPHIER_RESETX(21, 0x2014, 1), /* USB31-PHY1 */ |
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UNIPHIER_RESETX(28, 0x2014, 12), /* SATA */ |
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UNIPHIER_RESET(29, 0x2014, 8), /* SATA-PHY (active high) */ |
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UNIPHIER_RESET_END, |
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}; |
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static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { |
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UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */ |
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UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */ |
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UNIPHIER_RESETX(6, 0x200c, 6), /* ETHER */ |
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UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC */ |
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UNIPHIER_RESETX(14, 0x200c, 5), /* USB30 */ |
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UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */ |
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UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */ |
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UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */ |
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UNIPHIER_RESETX(19, 0x200c, 15), /* USB30-PHY3 */ |
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UNIPHIER_RESET_END, |
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}; |
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static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = { |
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UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */ |
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UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */ |
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UNIPHIER_RESETX(6, 0x200c, 9), /* ETHER0 */ |
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UNIPHIER_RESETX(7, 0x200c, 10), /* ETHER1 */ |
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UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */ |
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UNIPHIER_RESETX(12, 0x200c, 4), /* USB30 link */ |
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UNIPHIER_RESETX(13, 0x200c, 5), /* USB31 link */ |
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UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY0 */ |
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UNIPHIER_RESETX(17, 0x200c, 18), /* USB30-PHY1 */ |
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UNIPHIER_RESETX(18, 0x200c, 20), /* USB30-PHY2 */ |
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UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY0 */ |
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UNIPHIER_RESETX(21, 0x200c, 19), /* USB31-PHY1 */ |
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UNIPHIER_RESET_END, |
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}; |
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/* Media I/O reset data */ |
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#define UNIPHIER_MIO_RESET_SD(id, ch) \ |
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UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0) |
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#define UNIPHIER_MIO_RESET_SD_BRIDGE(id, ch) \ |
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UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 26) |
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#define UNIPHIER_MIO_RESET_EMMC_HW_RESET(id, ch) \ |
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UNIPHIER_RESETX((id), 0x80 + 0x200 * (ch), 0) |
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#define UNIPHIER_MIO_RESET_USB2(id, ch) \ |
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UNIPHIER_RESETX((id), 0x114 + 0x200 * (ch), 0) |
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#define UNIPHIER_MIO_RESET_USB2_BRIDGE(id, ch) \ |
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UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 24) |
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#define UNIPHIER_MIO_RESET_DMAC(id) \ |
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UNIPHIER_RESETX((id), 0x110, 17) |
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static const struct uniphier_reset_data uniphier_mio_reset_data[] = { |
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UNIPHIER_MIO_RESET_SD(0, 0), |
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UNIPHIER_MIO_RESET_SD(1, 1), |
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UNIPHIER_MIO_RESET_SD(2, 2), |
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UNIPHIER_MIO_RESET_SD_BRIDGE(3, 0), |
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UNIPHIER_MIO_RESET_SD_BRIDGE(4, 1), |
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UNIPHIER_MIO_RESET_SD_BRIDGE(5, 2), |
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UNIPHIER_MIO_RESET_EMMC_HW_RESET(6, 1), |
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UNIPHIER_MIO_RESET_DMAC(7), |
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UNIPHIER_MIO_RESET_USB2(8, 0), |
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UNIPHIER_MIO_RESET_USB2(9, 1), |
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UNIPHIER_MIO_RESET_USB2(10, 2), |
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UNIPHIER_MIO_RESET_USB2(11, 3), |
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UNIPHIER_MIO_RESET_USB2_BRIDGE(12, 0), |
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UNIPHIER_MIO_RESET_USB2_BRIDGE(13, 1), |
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UNIPHIER_MIO_RESET_USB2_BRIDGE(14, 2), |
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UNIPHIER_MIO_RESET_USB2_BRIDGE(15, 3), |
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UNIPHIER_RESET_END, |
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}; |
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/* Peripheral reset data */ |
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#define UNIPHIER_PERI_RESET_UART(id, ch) \ |
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UNIPHIER_RESETX((id), 0x114, 19 + (ch)) |
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#define UNIPHIER_PERI_RESET_I2C(id, ch) \ |
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UNIPHIER_RESETX((id), 0x114, 5 + (ch)) |
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#define UNIPHIER_PERI_RESET_FI2C(id, ch) \ |
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UNIPHIER_RESETX((id), 0x114, 24 + (ch)) |
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static const struct uniphier_reset_data uniphier_ld4_peri_reset_data[] = { |
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UNIPHIER_PERI_RESET_UART(0, 0), |
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UNIPHIER_PERI_RESET_UART(1, 1), |
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UNIPHIER_PERI_RESET_UART(2, 2), |
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UNIPHIER_PERI_RESET_UART(3, 3), |
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UNIPHIER_PERI_RESET_I2C(4, 0), |
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UNIPHIER_PERI_RESET_I2C(5, 1), |
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UNIPHIER_PERI_RESET_I2C(6, 2), |
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UNIPHIER_PERI_RESET_I2C(7, 3), |
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UNIPHIER_PERI_RESET_I2C(8, 4), |
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UNIPHIER_RESET_END, |
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}; |
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static const struct uniphier_reset_data uniphier_pro4_peri_reset_data[] = { |
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UNIPHIER_PERI_RESET_UART(0, 0), |
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UNIPHIER_PERI_RESET_UART(1, 1), |
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UNIPHIER_PERI_RESET_UART(2, 2), |
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UNIPHIER_PERI_RESET_UART(3, 3), |
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UNIPHIER_PERI_RESET_FI2C(4, 0), |
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UNIPHIER_PERI_RESET_FI2C(5, 1), |
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UNIPHIER_PERI_RESET_FI2C(6, 2), |
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UNIPHIER_PERI_RESET_FI2C(7, 3), |
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UNIPHIER_PERI_RESET_FI2C(8, 4), |
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UNIPHIER_PERI_RESET_FI2C(9, 5), |
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UNIPHIER_PERI_RESET_FI2C(10, 6), |
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UNIPHIER_RESET_END, |
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}; |
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/* core implementaton */ |
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struct uniphier_reset_priv { |
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void __iomem *base; |
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const struct uniphier_reset_data *data; |
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}; |
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static int uniphier_reset_request(struct reset_ctl *reset_ctl) |
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{ |
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return 0; |
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} |
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static int uniphier_reset_free(struct reset_ctl *reset_ctl) |
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{ |
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return 0; |
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} |
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static int uniphier_reset_update(struct reset_ctl *reset_ctl, int assert) |
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{ |
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struct uniphier_reset_priv *priv = dev_get_priv(reset_ctl->dev); |
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unsigned long id = reset_ctl->id; |
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const struct uniphier_reset_data *p; |
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for (p = priv->data; p->id != UNIPHIER_RESET_ID_END; p++) { |
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u32 mask, val; |
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if (p->id != id) |
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continue; |
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val = readl(priv->base + p->reg); |
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if (p->flags & UNIPHIER_RESET_ACTIVE_LOW) |
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assert = !assert; |
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mask = BIT(p->bit); |
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if (assert) |
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val |= mask; |
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else |
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val &= ~mask; |
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writel(val, priv->base + p->reg); |
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return 0; |
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} |
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dev_err(reset_ctl->dev, "reset_id=%lu was not handled\n", id); |
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return -EINVAL; |
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} |
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static int uniphier_reset_assert(struct reset_ctl *reset_ctl) |
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{ |
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return uniphier_reset_update(reset_ctl, 1); |
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} |
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static int uniphier_reset_deassert(struct reset_ctl *reset_ctl) |
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{ |
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return uniphier_reset_update(reset_ctl, 0); |
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} |
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static const struct reset_ops uniphier_reset_ops = { |
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.request = uniphier_reset_request, |
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.free = uniphier_reset_free, |
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.rst_assert = uniphier_reset_assert, |
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.rst_deassert = uniphier_reset_deassert, |
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}; |
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static int uniphier_reset_probe(struct udevice *dev) |
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{ |
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struct uniphier_reset_priv *priv = dev_get_priv(dev); |
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fdt_addr_t addr; |
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addr = devfdt_get_addr(dev->parent); |
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if (addr == FDT_ADDR_T_NONE) |
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return -EINVAL; |
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priv->base = devm_ioremap(dev, addr, SZ_4K); |
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if (!priv->base) |
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return -ENOMEM; |
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priv->data = (void *)dev_get_driver_data(dev); |
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return 0; |
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} |
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static const struct udevice_id uniphier_reset_match[] = { |
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/* System reset */ |
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{ |
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.compatible = "socionext,uniphier-ld4-reset", |
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.data = (ulong)uniphier_pro4_sys_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-pro4-reset", |
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.data = (ulong)uniphier_pro4_sys_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-sld8-reset", |
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.data = (ulong)uniphier_pro4_sys_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-pro5-reset", |
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.data = (ulong)uniphier_pro4_sys_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-pxs2-reset", |
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.data = (ulong)uniphier_pxs2_sys_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-ld11-reset", |
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.data = (ulong)uniphier_ld20_sys_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-ld20-reset", |
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.data = (ulong)uniphier_ld20_sys_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-pxs3-reset", |
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.data = (ulong)uniphier_pxs3_sys_reset_data, |
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}, |
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/* Media I/O reset */ |
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{ |
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.compatible = "socionext,uniphier-ld4-mio-reset", |
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.data = (ulong)uniphier_mio_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-pro4-mio-reset", |
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.data = (ulong)uniphier_mio_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-sld8-mio-reset", |
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.data = (ulong)uniphier_mio_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-pro5-mio-reset", |
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.data = (ulong)uniphier_mio_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-pxs2-mio-reset", |
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.data = (ulong)uniphier_mio_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-ld11-mio-reset", |
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.data = (ulong)uniphier_mio_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-ld11-sd-reset", |
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.data = (ulong)uniphier_mio_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-ld20-sd-reset", |
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.data = (ulong)uniphier_mio_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-pxs3-sd-reset", |
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.data = (ulong)uniphier_mio_reset_data, |
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}, |
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/* Peripheral reset */ |
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{ |
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.compatible = "socionext,uniphier-ld4-peri-reset", |
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.data = (ulong)uniphier_ld4_peri_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-pro4-peri-reset", |
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.data = (ulong)uniphier_pro4_peri_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-sld8-peri-reset", |
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.data = (ulong)uniphier_ld4_peri_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-pro5-peri-reset", |
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.data = (ulong)uniphier_pro4_peri_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-pxs2-peri-reset", |
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.data = (ulong)uniphier_pro4_peri_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-ld11-peri-reset", |
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.data = (ulong)uniphier_pro4_peri_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-ld20-peri-reset", |
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.data = (ulong)uniphier_pro4_peri_reset_data, |
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}, |
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{ |
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.compatible = "socionext,uniphier-pxs3-peri-reset", |
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.data = (ulong)uniphier_pro4_peri_reset_data, |
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}, |
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{ /* sentinel */ } |
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}; |
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U_BOOT_DRIVER(uniphier_reset) = { |
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.name = "uniphier-reset", |
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.id = UCLASS_RESET, |
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.of_match = uniphier_reset_match, |
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.probe = uniphier_reset_probe, |
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.priv_auto_alloc_size = sizeof(struct uniphier_reset_priv), |
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.ops = &uniphier_reset_ops, |
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};
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