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503 lines
14 KiB
503 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd |
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*/ |
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|
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#include <common.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <syscon.h> |
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#include <asm/io.h> |
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#include <asm/arch/grf_rk3399.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/arch/periph.h> |
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#include <asm/arch/clock.h> |
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#include <dm/pinctrl.h> |
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struct rk3399_pinctrl_priv { |
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struct rk3399_grf_regs *grf; |
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struct rk3399_pmugrf_regs *pmugrf; |
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}; |
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static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf, |
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struct rk3399_pmugrf_regs *pmugrf, int pwm_id) |
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{ |
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switch (pwm_id) { |
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case PERIPH_ID_PWM0: |
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rk_clrsetreg(&grf->gpio4c_iomux, |
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GRF_GPIO4C2_SEL_MASK, |
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GRF_PWM_0 << GRF_GPIO4C2_SEL_SHIFT); |
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break; |
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case PERIPH_ID_PWM1: |
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rk_clrsetreg(&grf->gpio4c_iomux, |
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GRF_GPIO4C6_SEL_MASK, |
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GRF_PWM_1 << GRF_GPIO4C6_SEL_SHIFT); |
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break; |
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case PERIPH_ID_PWM2: |
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rk_clrsetreg(&pmugrf->gpio1c_iomux, |
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PMUGRF_GPIO1C3_SEL_MASK, |
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PMUGRF_PWM_2 << PMUGRF_GPIO1C3_SEL_SHIFT); |
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break; |
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case PERIPH_ID_PWM3: |
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if (readl(&pmugrf->soc_con0) & (1 << 5)) |
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rk_clrsetreg(&pmugrf->gpio1b_iomux, |
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PMUGRF_GPIO1B6_SEL_MASK, |
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PMUGRF_PWM_3B << PMUGRF_GPIO1B6_SEL_SHIFT); |
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else |
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rk_clrsetreg(&pmugrf->gpio0a_iomux, |
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PMUGRF_GPIO0A6_SEL_MASK, |
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PMUGRF_PWM_3A << PMUGRF_GPIO0A6_SEL_SHIFT); |
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break; |
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default: |
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debug("pwm id = %d iomux error!\n", pwm_id); |
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break; |
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} |
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} |
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static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf, |
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struct rk3399_pmugrf_regs *pmugrf, |
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int i2c_id) |
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{ |
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switch (i2c_id) { |
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case PERIPH_ID_I2C0: |
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rk_clrsetreg(&pmugrf->gpio1b_iomux, |
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PMUGRF_GPIO1B7_SEL_MASK, |
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PMUGRF_I2C0PMU_SDA << PMUGRF_GPIO1B7_SEL_SHIFT); |
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rk_clrsetreg(&pmugrf->gpio1c_iomux, |
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PMUGRF_GPIO1C0_SEL_MASK, |
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PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT); |
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break; |
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case PERIPH_ID_I2C1: |
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rk_clrsetreg(&grf->gpio4a_iomux, |
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GRF_GPIO4A1_SEL_MASK, |
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GRF_I2C1_SDA << GRF_GPIO4A1_SEL_SHIFT); |
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rk_clrsetreg(&grf->gpio4a_iomux, |
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GRF_GPIO4A2_SEL_MASK, |
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GRF_I2C1_SCL << GRF_GPIO4A2_SEL_SHIFT); |
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break; |
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case PERIPH_ID_I2C2: |
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rk_clrsetreg(&grf->gpio2a_iomux, |
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GRF_GPIO2A0_SEL_MASK, |
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GRF_I2C2_SDA << GRF_GPIO2A0_SEL_SHIFT); |
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rk_clrsetreg(&grf->gpio2a_iomux, |
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GRF_GPIO2A1_SEL_MASK, |
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GRF_I2C2_SCL << GRF_GPIO2A1_SEL_SHIFT); |
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break; |
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case PERIPH_ID_I2C3: |
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rk_clrsetreg(&grf->gpio4c_iomux, |
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GRF_GPIO4C0_SEL_MASK, |
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GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT); |
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rk_clrsetreg(&grf->gpio4c_iomux, |
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GRF_GPIO4C1_SEL_MASK, |
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GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT); |
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break; |
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case PERIPH_ID_I2C4: |
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rk_clrsetreg(&pmugrf->gpio1b_iomux, |
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PMUGRF_GPIO1B3_SEL_MASK, |
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PMUGRF_I2C4_SDA << PMUGRF_GPIO1B3_SEL_SHIFT); |
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rk_clrsetreg(&pmugrf->gpio1b_iomux, |
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PMUGRF_GPIO1B4_SEL_MASK, |
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PMUGRF_I2C4_SCL << PMUGRF_GPIO1B4_SEL_SHIFT); |
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break; |
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case PERIPH_ID_I2C7: |
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rk_clrsetreg(&grf->gpio2a_iomux, |
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GRF_GPIO2A7_SEL_MASK, |
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GRF_I2C7_SDA << GRF_GPIO2A7_SEL_SHIFT); |
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rk_clrsetreg(&grf->gpio2b_iomux, |
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GRF_GPIO2B0_SEL_MASK, |
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GRF_I2C7_SCL << GRF_GPIO2B0_SEL_SHIFT); |
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break; |
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case PERIPH_ID_I2C6: |
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rk_clrsetreg(&grf->gpio2b_iomux, |
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GRF_GPIO2B1_SEL_MASK, |
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GRF_I2C6_SDA << GRF_GPIO2B1_SEL_SHIFT); |
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rk_clrsetreg(&grf->gpio2b_iomux, |
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GRF_GPIO2B2_SEL_MASK, |
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GRF_I2C6_SDA << GRF_GPIO2B2_SEL_SHIFT); |
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break; |
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case PERIPH_ID_I2C8: |
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rk_clrsetreg(&pmugrf->gpio1c_iomux, |
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PMUGRF_GPIO1C4_SEL_MASK, |
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PMUGRF_I2C8PMU_SDA << PMUGRF_GPIO1C4_SEL_SHIFT); |
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rk_clrsetreg(&pmugrf->gpio1c_iomux, |
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PMUGRF_GPIO1C5_SEL_MASK, |
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PMUGRF_I2C8PMU_SCL << PMUGRF_GPIO1C5_SEL_SHIFT); |
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break; |
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case PERIPH_ID_I2C5: |
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default: |
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debug("i2c id = %d iomux error!\n", i2c_id); |
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break; |
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} |
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} |
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static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs *grf, int lcd_id) |
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{ |
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switch (lcd_id) { |
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case PERIPH_ID_LCDC0: |
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break; |
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default: |
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debug("lcdc id = %d iomux error!\n", lcd_id); |
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break; |
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} |
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} |
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static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf, |
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struct rk3399_pmugrf_regs *pmugrf, |
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enum periph_id spi_id, int cs) |
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{ |
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switch (spi_id) { |
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case PERIPH_ID_SPI0: |
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switch (cs) { |
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case 0: |
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rk_clrsetreg(&grf->gpio3a_iomux, |
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GRF_GPIO3A7_SEL_MASK, |
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GRF_SPI0NORCODEC_CSN0 |
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<< GRF_GPIO3A7_SEL_SHIFT); |
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break; |
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case 1: |
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rk_clrsetreg(&grf->gpio3b_iomux, |
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GRF_GPIO3B0_SEL_MASK, |
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GRF_SPI0NORCODEC_CSN1 |
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<< GRF_GPIO3B0_SEL_SHIFT); |
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break; |
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default: |
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goto err; |
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} |
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rk_clrsetreg(&grf->gpio3a_iomux, |
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GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_SHIFT |
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| GRF_GPIO3A6_SEL_SHIFT, |
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GRF_SPI0NORCODEC_RXD << GRF_GPIO3A4_SEL_SHIFT |
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| GRF_SPI0NORCODEC_RXD << GRF_GPIO3A5_SEL_SHIFT |
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| GRF_SPI0NORCODEC_RXD << GRF_GPIO3A6_SEL_SHIFT); |
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break; |
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case PERIPH_ID_SPI1: |
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if (cs != 0) |
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goto err; |
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rk_clrsetreg(&pmugrf->gpio1a_iomux, |
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PMUGRF_GPIO1A7_SEL_MASK, |
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PMUGRF_SPI1EC_RXD << PMUGRF_GPIO1A7_SEL_SHIFT); |
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rk_clrsetreg(&pmugrf->gpio1b_iomux, |
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PMUGRF_GPIO1B0_SEL_MASK | PMUGRF_GPIO1B1_SEL_MASK |
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| PMUGRF_GPIO1B2_SEL_MASK, |
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PMUGRF_SPI1EC_TXD << PMUGRF_GPIO1B0_SEL_SHIFT |
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| PMUGRF_SPI1EC_CLK << PMUGRF_GPIO1B1_SEL_SHIFT |
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| PMUGRF_SPI1EC_CSN0 << PMUGRF_GPIO1B2_SEL_SHIFT); |
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break; |
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case PERIPH_ID_SPI2: |
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if (cs != 0) |
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goto err; |
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rk_clrsetreg(&grf->gpio2b_iomux, |
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GRF_GPIO2B1_SEL_MASK | GRF_GPIO2B2_SEL_MASK |
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| GRF_GPIO2B3_SEL_MASK | GRF_GPIO2B4_SEL_MASK, |
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GRF_SPI2TPM_RXD << GRF_GPIO2B1_SEL_SHIFT |
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| GRF_SPI2TPM_TXD << GRF_GPIO2B2_SEL_SHIFT |
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| GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT |
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| GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT); |
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break; |
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case PERIPH_ID_SPI5: |
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if (cs != 0) |
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goto err; |
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rk_clrsetreg(&grf->gpio2c_iomux, |
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GRF_GPIO2C4_SEL_MASK | GRF_GPIO2C5_SEL_MASK |
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| GRF_GPIO2C6_SEL_MASK | GRF_GPIO2C7_SEL_MASK, |
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GRF_SPI5EXPPLUS_RXD << GRF_GPIO2C4_SEL_SHIFT |
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| GRF_SPI5EXPPLUS_TXD << GRF_GPIO2C5_SEL_SHIFT |
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| GRF_SPI5EXPPLUS_CLK << GRF_GPIO2C6_SEL_SHIFT |
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| GRF_SPI5EXPPLUS_CSN0 << GRF_GPIO2C7_SEL_SHIFT); |
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break; |
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default: |
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printf("%s: spi_id %d is not supported.\n", __func__, spi_id); |
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goto err; |
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} |
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return 0; |
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err: |
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debug("rkspi: periph%d cs=%d not supported", spi_id, cs); |
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return -ENOENT; |
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} |
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static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs *grf, |
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struct rk3399_pmugrf_regs *pmugrf, |
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int uart_id) |
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{ |
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switch (uart_id) { |
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case PERIPH_ID_UART2: |
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/* Using channel-C by default */ |
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rk_clrsetreg(&grf->gpio4c_iomux, |
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GRF_GPIO4C3_SEL_MASK, |
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GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); |
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rk_clrsetreg(&grf->gpio4c_iomux, |
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GRF_GPIO4C4_SEL_MASK, |
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GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); |
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break; |
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case PERIPH_ID_UART0: |
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case PERIPH_ID_UART1: |
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case PERIPH_ID_UART3: |
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case PERIPH_ID_UART4: |
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default: |
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debug("uart id = %d iomux error!\n", uart_id); |
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break; |
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} |
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} |
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static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id) |
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{ |
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switch (mmc_id) { |
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case PERIPH_ID_EMMC: |
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break; |
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case PERIPH_ID_SDCARD: |
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rk_clrsetreg(&grf->gpio4b_iomux, |
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GRF_GPIO4B0_SEL_MASK | GRF_GPIO4B1_SEL_MASK |
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| GRF_GPIO4B2_SEL_MASK | GRF_GPIO4B3_SEL_MASK |
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| GRF_GPIO4B4_SEL_MASK | GRF_GPIO4B5_SEL_MASK, |
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GRF_SDMMC_DATA0 << GRF_GPIO4B0_SEL_SHIFT |
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| GRF_SDMMC_DATA1 << GRF_GPIO4B1_SEL_SHIFT |
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| GRF_SDMMC_DATA2 << GRF_GPIO4B2_SEL_SHIFT |
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| GRF_SDMMC_DATA3 << GRF_GPIO4B3_SEL_SHIFT |
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| GRF_SDMMC_CLKOUT << GRF_GPIO4B4_SEL_SHIFT |
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| GRF_SDMMC_CMD << GRF_GPIO4B5_SEL_SHIFT); |
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break; |
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default: |
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debug("mmc id = %d iomux error!\n", mmc_id); |
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break; |
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} |
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} |
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#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) |
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static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id) |
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{ |
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rk_clrsetreg(&grf->gpio3a_iomux, |
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GRF_GPIO3A0_SEL_MASK | GRF_GPIO3A1_SEL_MASK | |
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GRF_GPIO3A2_SEL_MASK | GRF_GPIO3A3_SEL_MASK | |
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GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_MASK | |
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GRF_GPIO3A6_SEL_MASK | GRF_GPIO3A7_SEL_MASK, |
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GRF_MAC_TXD2 << GRF_GPIO3A0_SEL_SHIFT | |
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GRF_MAC_TXD3 << GRF_GPIO3A1_SEL_SHIFT | |
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GRF_MAC_RXD2 << GRF_GPIO3A2_SEL_SHIFT | |
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GRF_MAC_RXD3 << GRF_GPIO3A3_SEL_SHIFT | |
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GRF_MAC_TXD0 << GRF_GPIO3A4_SEL_SHIFT | |
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GRF_MAC_TXD1 << GRF_GPIO3A5_SEL_SHIFT | |
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GRF_MAC_RXD0 << GRF_GPIO3A6_SEL_SHIFT | |
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GRF_MAC_RXD1 << GRF_GPIO3A7_SEL_SHIFT); |
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rk_clrsetreg(&grf->gpio3b_iomux, |
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GRF_GPIO3B0_SEL_MASK | GRF_GPIO3B1_SEL_MASK | |
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GRF_GPIO3B3_SEL_MASK | |
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GRF_GPIO3B4_SEL_MASK | GRF_GPIO3B5_SEL_MASK | |
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GRF_GPIO3B6_SEL_MASK, |
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GRF_MAC_MDC << GRF_GPIO3B0_SEL_SHIFT | |
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GRF_MAC_RXDV << GRF_GPIO3B1_SEL_SHIFT | |
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GRF_MAC_CLK << GRF_GPIO3B3_SEL_SHIFT | |
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GRF_MAC_TXEN << GRF_GPIO3B4_SEL_SHIFT | |
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GRF_MAC_MDIO << GRF_GPIO3B5_SEL_SHIFT | |
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GRF_MAC_RXCLK << GRF_GPIO3B6_SEL_SHIFT); |
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rk_clrsetreg(&grf->gpio3c_iomux, |
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GRF_GPIO3C1_SEL_MASK, |
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GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT); |
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/* Set drive strength for GMAC tx io, value 3 means 13mA */ |
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rk_clrsetreg(&grf->gpio3_e[0], |
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GRF_GPIO3A0_E_MASK | GRF_GPIO3A1_E_MASK | |
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GRF_GPIO3A4_E_MASK | GRF_GPIO3A5_E0_MASK, |
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3 << GRF_GPIO3A0_E_SHIFT | |
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3 << GRF_GPIO3A1_E_SHIFT | |
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3 << GRF_GPIO3A4_E_SHIFT | |
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1 << GRF_GPIO3A5_E0_SHIFT); |
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rk_clrsetreg(&grf->gpio3_e[1], |
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GRF_GPIO3A5_E12_MASK, |
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1 << GRF_GPIO3A5_E12_SHIFT); |
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rk_clrsetreg(&grf->gpio3_e[2], |
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GRF_GPIO3B4_E_MASK, |
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3 << GRF_GPIO3B4_E_SHIFT); |
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rk_clrsetreg(&grf->gpio3_e[4], |
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GRF_GPIO3C1_E_MASK, |
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3 << GRF_GPIO3C1_E_SHIFT); |
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} |
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#endif |
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#if !defined(CONFIG_SPL_BUILD) |
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static void pinctrl_rk3399_hdmi_config(struct rk3399_grf_regs *grf, int hdmi_id) |
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{ |
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switch (hdmi_id) { |
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case PERIPH_ID_HDMI: |
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rk_clrsetreg(&grf->gpio4c_iomux, |
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GRF_GPIO4C0_SEL_MASK | GRF_GPIO4C1_SEL_MASK, |
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(GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT) | |
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(GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT)); |
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break; |
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default: |
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debug("%s: hdmi_id = %d unsupported\n", __func__, hdmi_id); |
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break; |
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} |
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} |
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#endif |
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static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags) |
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{ |
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struct rk3399_pinctrl_priv *priv = dev_get_priv(dev); |
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debug("%s: func=%x, flags=%x\n", __func__, func, flags); |
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switch (func) { |
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case PERIPH_ID_PWM0: |
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case PERIPH_ID_PWM1: |
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case PERIPH_ID_PWM2: |
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case PERIPH_ID_PWM3: |
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case PERIPH_ID_PWM4: |
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pinctrl_rk3399_pwm_config(priv->grf, priv->pmugrf, func); |
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break; |
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case PERIPH_ID_I2C0: |
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case PERIPH_ID_I2C1: |
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case PERIPH_ID_I2C2: |
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case PERIPH_ID_I2C3: |
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case PERIPH_ID_I2C4: |
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case PERIPH_ID_I2C5: |
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case PERIPH_ID_I2C6: |
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case PERIPH_ID_I2C7: |
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case PERIPH_ID_I2C8: |
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pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func); |
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break; |
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case PERIPH_ID_SPI0: |
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case PERIPH_ID_SPI1: |
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case PERIPH_ID_SPI2: |
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case PERIPH_ID_SPI3: |
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case PERIPH_ID_SPI4: |
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case PERIPH_ID_SPI5: |
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pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags); |
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break; |
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case PERIPH_ID_UART0: |
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case PERIPH_ID_UART1: |
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case PERIPH_ID_UART2: |
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case PERIPH_ID_UART3: |
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case PERIPH_ID_UART4: |
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pinctrl_rk3399_uart_config(priv->grf, priv->pmugrf, func); |
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break; |
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case PERIPH_ID_LCDC0: |
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case PERIPH_ID_LCDC1: |
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pinctrl_rk3399_lcdc_config(priv->grf, func); |
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break; |
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case PERIPH_ID_SDMMC0: |
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case PERIPH_ID_SDMMC1: |
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pinctrl_rk3399_sdmmc_config(priv->grf, func); |
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break; |
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#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) |
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case PERIPH_ID_GMAC: |
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pinctrl_rk3399_gmac_config(priv->grf, func); |
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break; |
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#endif |
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#if !defined(CONFIG_SPL_BUILD) |
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case PERIPH_ID_HDMI: |
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pinctrl_rk3399_hdmi_config(priv->grf, func); |
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break; |
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#endif |
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default: |
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return -EINVAL; |
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} |
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|
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return 0; |
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} |
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|
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static int rk3399_pinctrl_get_periph_id(struct udevice *dev, |
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struct udevice *periph) |
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{ |
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#if !CONFIG_IS_ENABLED(OF_PLATDATA) |
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u32 cell[3]; |
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int ret; |
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|
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ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell)); |
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if (ret < 0) |
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return -EINVAL; |
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|
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switch (cell[1]) { |
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case 68: |
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return PERIPH_ID_SPI0; |
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case 53: |
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return PERIPH_ID_SPI1; |
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case 52: |
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return PERIPH_ID_SPI2; |
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case 132: |
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return PERIPH_ID_SPI5; |
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case 57: |
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return PERIPH_ID_I2C0; |
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case 59: /* Note strange order */ |
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return PERIPH_ID_I2C1; |
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case 35: |
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return PERIPH_ID_I2C2; |
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case 34: |
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return PERIPH_ID_I2C3; |
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case 56: |
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return PERIPH_ID_I2C4; |
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case 38: |
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return PERIPH_ID_I2C5; |
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case 37: |
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return PERIPH_ID_I2C6; |
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case 36: |
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return PERIPH_ID_I2C7; |
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case 58: |
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return PERIPH_ID_I2C8; |
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case 65: |
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return PERIPH_ID_SDMMC1; |
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#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) |
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case 12: |
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return PERIPH_ID_GMAC; |
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#endif |
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#if !defined(CONFIG_SPL_BUILD) |
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case 23: |
|
return PERIPH_ID_HDMI; |
|
#endif |
|
} |
|
#endif |
|
return -ENOENT; |
|
} |
|
|
|
static int rk3399_pinctrl_set_state_simple(struct udevice *dev, |
|
struct udevice *periph) |
|
{ |
|
int func; |
|
|
|
func = rk3399_pinctrl_get_periph_id(dev, periph); |
|
if (func < 0) |
|
return func; |
|
|
|
return rk3399_pinctrl_request(dev, func, 0); |
|
} |
|
|
|
static struct pinctrl_ops rk3399_pinctrl_ops = { |
|
.set_state_simple = rk3399_pinctrl_set_state_simple, |
|
.request = rk3399_pinctrl_request, |
|
.get_periph_id = rk3399_pinctrl_get_periph_id, |
|
}; |
|
|
|
static int rk3399_pinctrl_probe(struct udevice *dev) |
|
{ |
|
struct rk3399_pinctrl_priv *priv = dev_get_priv(dev); |
|
int ret = 0; |
|
|
|
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
|
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); |
|
debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf); |
|
|
|
return ret; |
|
} |
|
|
|
static const struct udevice_id rk3399_pinctrl_ids[] = { |
|
{ .compatible = "rockchip,rk3399-pinctrl" }, |
|
{ } |
|
}; |
|
|
|
U_BOOT_DRIVER(pinctrl_rk3399) = { |
|
.name = "rockchip_rk3399_pinctrl", |
|
.id = UCLASS_PINCTRL, |
|
.of_match = rk3399_pinctrl_ids, |
|
.priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv), |
|
.ops = &rk3399_pinctrl_ops, |
|
#if !CONFIG_IS_ENABLED(OF_PLATDATA) |
|
.bind = dm_scan_fdt_dev, |
|
#endif |
|
.probe = rk3399_pinctrl_probe, |
|
};
|
|
|