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426 lines
11 KiB
426 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* (C) Copyright 2002 |
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* Rich Ireland, Enterasys Networks, [email protected]. |
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* Keith Outwater, [email protected] |
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*/ |
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|
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/* |
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* Configuration support for Xilinx Virtex2 devices. Based |
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* on spartan2.c (Rich Ireland, [email protected]). |
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*/ |
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#include <common.h> |
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#include <console.h> |
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#include <virtex2.h> |
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#if 0 |
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#define FPGA_DEBUG |
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#endif |
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#ifdef FPGA_DEBUG |
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#define PRINTF(fmt,args...) printf (fmt ,##args) |
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#else |
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#define PRINTF(fmt,args...) |
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#endif |
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/* |
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* If the SelectMap interface can be overrun by the processor, define |
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* CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board configuration |
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* file and add board-specific support for checking BUSY status. By default, |
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* assume that the SelectMap interface cannot be overrun. |
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*/ |
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#ifndef CONFIG_SYS_FPGA_CHECK_BUSY |
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#undef CONFIG_SYS_FPGA_CHECK_BUSY |
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#endif |
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#ifndef CONFIG_FPGA_DELAY |
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#define CONFIG_FPGA_DELAY() |
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#endif |
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#ifndef CONFIG_SYS_FPGA_PROG_FEEDBACK |
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#define CONFIG_SYS_FPGA_PROG_FEEDBACK |
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#endif |
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/* |
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* Don't allow config cycle to be interrupted |
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*/ |
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#ifndef CONFIG_SYS_FPGA_CHECK_CTRLC |
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#undef CONFIG_SYS_FPGA_CHECK_CTRLC |
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#endif |
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/* |
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* Check for errors during configuration by default |
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*/ |
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#ifndef CONFIG_SYS_FPGA_CHECK_ERROR |
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#define CONFIG_SYS_FPGA_CHECK_ERROR |
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#endif |
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/* |
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* The default timeout in mS for INIT_B to deassert after PROG_B has |
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* been deasserted. Per the latest Virtex II Handbook (page 347), the |
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* max time from PORG_B deassertion to INIT_B deassertion is 4uS per |
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* data frame for the XC2V8000. The XC2V8000 has 2860 data frames |
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* which yields 11.44 mS. So let's make it bigger in order to handle |
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* an XC2V1000, if anyone can ever get ahold of one. |
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*/ |
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#ifndef CONFIG_SYS_FPGA_WAIT_INIT |
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#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ/2 /* 500 ms */ |
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#endif |
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/* |
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* The default timeout for waiting for BUSY to deassert during configuration. |
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* This is normally not necessary since for most reasonable configuration |
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* clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary. |
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*/ |
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#ifndef CONFIG_SYS_FPGA_WAIT_BUSY |
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#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ/200 /* 5 ms*/ |
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#endif |
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/* Default timeout for waiting for FPGA to enter operational mode after |
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* configuration data has been written. |
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*/ |
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#ifndef CONFIG_SYS_FPGA_WAIT_CONFIG |
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#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */ |
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#endif |
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static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize); |
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static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize); |
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static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); |
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static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); |
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static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize, |
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bitstream_type bstype) |
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{ |
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int ret_val = FPGA_FAIL; |
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switch (desc->iface) { |
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case slave_serial: |
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PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); |
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ret_val = virtex2_ss_load(desc, buf, bsize); |
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break; |
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case slave_selectmap: |
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PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); |
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ret_val = virtex2_ssm_load(desc, buf, bsize); |
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break; |
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default: |
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printf ("%s: Unsupported interface type, %d\n", |
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__FUNCTION__, desc->iface); |
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} |
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return ret_val; |
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} |
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static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize) |
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{ |
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int ret_val = FPGA_FAIL; |
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switch (desc->iface) { |
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case slave_serial: |
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PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); |
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ret_val = virtex2_ss_dump(desc, buf, bsize); |
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break; |
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case slave_parallel: |
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PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); |
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ret_val = virtex2_ssm_dump(desc, buf, bsize); |
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break; |
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default: |
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printf ("%s: Unsupported interface type, %d\n", |
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__FUNCTION__, desc->iface); |
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} |
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return ret_val; |
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} |
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static int virtex2_info(xilinx_desc *desc) |
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{ |
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return FPGA_SUCCESS; |
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} |
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/* |
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* Virtex-II Slave SelectMap configuration loader. Configuration via |
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* SelectMap is as follows: |
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* 1. Set the FPGA's PROG_B line low. |
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* 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high. |
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* 3. Write data to the SelectMap port. If INIT_B goes low at any time |
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* this process, a configuration error (most likely CRC failure) has |
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* ocurred. At this point a status word may be read from the |
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* SelectMap interface to determine the source of the problem (You |
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* could, for instance, put this in your 'abort' function handler). |
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* 4. After all data has been written, test the state of the FPGA |
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* INIT_B and DONE lines. If both are high, configuration has |
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* succeeded. Congratulations! |
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*/ |
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static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) |
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{ |
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int ret_val = FPGA_FAIL; |
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xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; |
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PRINTF ("%s:%d: Start with interface functions @ 0x%p\n", |
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__FUNCTION__, __LINE__, fn); |
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if (fn) { |
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size_t bytecount = 0; |
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unsigned char *data = (unsigned char *) buf; |
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int cookie = desc->cookie; |
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unsigned long ts; |
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/* Gotta split this one up (so the stack won't blow??) */ |
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PRINTF ("%s:%d: Function Table:\n" |
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" base 0x%p\n" |
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" struct 0x%p\n" |
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" pre 0x%p\n" |
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" prog 0x%p\n" |
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" init 0x%p\n" |
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" error 0x%p\n", |
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__FUNCTION__, __LINE__, |
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&fn, fn, fn->pre, fn->pgm, fn->init, fn->err); |
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PRINTF (" clock 0x%p\n" |
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" cs 0x%p\n" |
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" write 0x%p\n" |
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" rdata 0x%p\n" |
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" wdata 0x%p\n" |
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" busy 0x%p\n" |
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" abort 0x%p\n" |
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" post 0x%p\n\n", |
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fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, |
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fn->busy, fn->abort, fn->post); |
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK |
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printf ("Initializing FPGA Device %d...\n", cookie); |
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#endif |
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/* |
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* Run the pre configuration function if there is one. |
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*/ |
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if (*fn->pre) { |
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(*fn->pre) (cookie); |
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} |
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/* |
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* Assert the program line. The minimum pulse width for |
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* Virtex II devices is 300 nS (Tprogram parameter in datasheet). |
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* There is no maximum value for the pulse width. Check to make |
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* sure that INIT_B goes low after assertion of PROG_B |
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*/ |
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(*fn->pgm) (true, true, cookie); |
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udelay (10); |
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ts = get_timer (0); |
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do { |
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if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) { |
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printf ("%s:%d: ** Timeout after %d ticks waiting for INIT" |
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" to assert.\n", __FUNCTION__, __LINE__, |
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CONFIG_SYS_FPGA_WAIT_INIT); |
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(*fn->abort) (cookie); |
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return FPGA_FAIL; |
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} |
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} while (!(*fn->init) (cookie)); |
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(*fn->pgm) (false, true, cookie); |
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CONFIG_FPGA_DELAY (); |
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(*fn->clk) (true, true, cookie); |
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/* |
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* Start a timer and wait for INIT_B to go high |
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*/ |
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ts = get_timer (0); |
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do { |
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CONFIG_FPGA_DELAY (); |
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if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) { |
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printf ("%s:%d: ** Timeout after %d ticks waiting for INIT" |
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" to deassert.\n", __FUNCTION__, __LINE__, |
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CONFIG_SYS_FPGA_WAIT_INIT); |
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(*fn->abort) (cookie); |
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return FPGA_FAIL; |
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} |
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} while ((*fn->init) (cookie) && (*fn->busy) (cookie)); |
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(*fn->wr) (true, true, cookie); |
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(*fn->cs) (true, true, cookie); |
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udelay (10000); |
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/* |
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* Load the data byte by byte |
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*/ |
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while (bytecount < bsize) { |
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#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC |
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if (ctrlc ()) { |
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(*fn->abort) (cookie); |
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return FPGA_FAIL; |
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} |
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#endif |
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if ((*fn->done) (cookie) == FPGA_SUCCESS) { |
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PRINTF ("%s:%d:done went active early, bytecount = %d\n", |
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__FUNCTION__, __LINE__, bytecount); |
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break; |
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} |
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#ifdef CONFIG_SYS_FPGA_CHECK_ERROR |
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if ((*fn->init) (cookie)) { |
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printf ("\n%s:%d: ** Error: INIT asserted during" |
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" configuration\n", __FUNCTION__, __LINE__); |
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printf ("%d = buffer offset, %d = buffer size\n", |
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bytecount, bsize); |
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(*fn->abort) (cookie); |
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return FPGA_FAIL; |
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} |
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#endif |
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(*fn->wdata) (data[bytecount++], true, cookie); |
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CONFIG_FPGA_DELAY (); |
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/* |
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* Cycle the clock pin |
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*/ |
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(*fn->clk) (false, true, cookie); |
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CONFIG_FPGA_DELAY (); |
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(*fn->clk) (true, true, cookie); |
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#ifdef CONFIG_SYS_FPGA_CHECK_BUSY |
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ts = get_timer (0); |
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while ((*fn->busy) (cookie)) { |
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if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_BUSY) { |
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printf ("%s:%d: ** Timeout after %d ticks waiting for" |
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" BUSY to deassert\n", |
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__FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_BUSY); |
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(*fn->abort) (cookie); |
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return FPGA_FAIL; |
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} |
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} |
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#endif |
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK |
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if (bytecount % (bsize / 40) == 0) |
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putc ('.'); |
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#endif |
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} |
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/* |
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* Finished writing the data; deassert FPGA CS_B and WRITE_B signals. |
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*/ |
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CONFIG_FPGA_DELAY (); |
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(*fn->cs) (false, true, cookie); |
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(*fn->wr) (false, true, cookie); |
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK |
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putc ('\n'); |
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#endif |
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/* |
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* Check for successful configuration. FPGA INIT_B and DONE should |
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* both be high upon successful configuration. |
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*/ |
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ts = get_timer (0); |
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ret_val = FPGA_SUCCESS; |
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while (((*fn->done) (cookie) == FPGA_FAIL) || (*fn->init) (cookie)) { |
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if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) { |
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printf ("%s:%d: ** Timeout after %d ticks waiting for DONE to" |
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"assert and INIT to deassert\n", |
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__FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG); |
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(*fn->abort) (cookie); |
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ret_val = FPGA_FAIL; |
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break; |
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} |
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} |
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if (ret_val == FPGA_SUCCESS) { |
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK |
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printf ("Initialization of FPGA device %d complete\n", cookie); |
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#endif |
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/* |
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* Run the post configuration function if there is one. |
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*/ |
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if (*fn->post) { |
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(*fn->post) (cookie); |
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} |
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} else { |
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK |
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printf ("** Initialization of FPGA device %d FAILED\n", |
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cookie); |
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#endif |
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} |
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} else { |
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printf ("%s:%d: NULL Interface function table!\n", |
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__FUNCTION__, __LINE__); |
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} |
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return ret_val; |
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} |
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/* |
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* Read the FPGA configuration data |
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*/ |
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static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize) |
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{ |
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int ret_val = FPGA_FAIL; |
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xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; |
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if (fn) { |
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unsigned char *data = (unsigned char *) buf; |
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size_t bytecount = 0; |
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int cookie = desc->cookie; |
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printf ("Starting Dump of FPGA Device %d...\n", cookie); |
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(*fn->cs) (true, true, cookie); |
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(*fn->clk) (true, true, cookie); |
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while (bytecount < bsize) { |
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#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC |
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if (ctrlc ()) { |
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(*fn->abort) (cookie); |
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return FPGA_FAIL; |
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} |
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#endif |
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/* |
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* Cycle the clock and read the data |
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*/ |
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(*fn->clk) (false, true, cookie); |
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(*fn->clk) (true, true, cookie); |
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(*fn->rdata) (&(data[bytecount++]), cookie); |
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK |
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if (bytecount % (bsize / 40) == 0) |
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putc ('.'); |
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#endif |
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} |
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/* |
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* Deassert CS_B and cycle the clock to deselect the device. |
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*/ |
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(*fn->cs) (false, false, cookie); |
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(*fn->clk) (false, true, cookie); |
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(*fn->clk) (true, true, cookie); |
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK |
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putc ('\n'); |
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#endif |
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puts ("Done.\n"); |
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} else { |
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printf ("%s:%d: NULL Interface function table!\n", |
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__FUNCTION__, __LINE__); |
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} |
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return ret_val; |
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} |
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static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) |
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{ |
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printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); |
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return FPGA_FAIL; |
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} |
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static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) |
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{ |
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printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__); |
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return FPGA_FAIL; |
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} |
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/* vim: set ts=4 tw=78: */ |
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struct xilinx_fpga_op virtex2_op = { |
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.load = virtex2_load, |
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.dump = virtex2_dump, |
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.info = virtex2_info, |
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};
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