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293 lines
8.4 KiB
293 lines
8.4 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* (C) Copyright 2016 |
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* Dirk Eibach, Guntermann & Drunck GmbH, [email protected] |
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* |
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* (C) Copyright 2017, 2018 |
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* Mario Six, Guntermann & Drunck GmbH, [email protected] |
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*/ |
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#include <common.h> |
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#include <axi.h> |
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#include <dm.h> |
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#include <regmap.h> |
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/** |
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* struct ihs_axi_regs - Structure for the register map of a IHS AXI device |
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* @interrupt_status: Status register to indicate certain events (e.g. |
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* error during transfer, transfer complete, etc.) |
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* @interrupt_enable_control: Register to both control which statuses will be |
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* indicated in the interrupt_status register, and |
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* to change bus settings |
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* @address_lsb: Least significant 16-bit word of the address of a |
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* device to transfer data from/to |
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* @address_msb: Most significant 16-bit word of the address of a |
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* device to transfer data from/to |
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* @write_data_lsb: Least significant 16-bit word of the data to be |
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* written to a device |
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* @write_data_msb: Most significant 16-bit word of the data to be |
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* written to a device |
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* @read_data_lsb: Least significant 16-bit word of the data read |
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* from a device |
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* @read_data_msb: Most significant 16-bit word of the data read |
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* from a device |
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*/ |
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struct ihs_axi_regs { |
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u16 interrupt_status; |
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u16 interrupt_enable_control; |
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u16 address_lsb; |
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u16 address_msb; |
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u16 write_data_lsb; |
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u16 write_data_msb; |
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u16 read_data_lsb; |
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u16 read_data_msb; |
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}; |
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/** |
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* ihs_axi_set() - Convenience macro to set values in register map |
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* @map: The register map to write to |
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* @member: The member of the ihs_axi_regs structure to write |
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* @val: The value to write to the register map |
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*/ |
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#define ihs_axi_set(map, member, val) \ |
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regmap_set(map, struct ihs_axi_regs, member, val) |
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/** |
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* ihs_axi_get() - Convenience macro to read values from register map |
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* @map: The register map to read from |
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* @member: The member of the ihs_axi_regs structure to read |
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* @valp: Pointer to a buffer to receive the value read |
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*/ |
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#define ihs_axi_get(map, member, valp) \ |
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regmap_get(map, struct ihs_axi_regs, member, valp) |
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/** |
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* struct ihs_axi_priv - Private data structure of IHS AXI devices |
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* @map: Register map for the IHS AXI device |
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*/ |
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struct ihs_axi_priv { |
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struct regmap *map; |
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}; |
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/** |
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* enum status_reg - Description of bits in the interrupt_status register |
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* @STATUS_READ_COMPLETE_EVENT: A read transfer was completed |
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* @STATUS_WRITE_COMPLETE_EVENT: A write transfer was completed |
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* @STATUS_TIMEOUT_EVENT: A timeout has occurred during the transfer |
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* @STATUS_ERROR_EVENT: A error has occurred during the transfer |
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* @STATUS_AXI_INT: A AXI interrupt has occurred |
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* @STATUS_READ_DATA_AVAILABLE: Data is available to be read |
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* @STATUS_BUSY: The bus is busy |
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* @STATUS_INIT_DONE: The bus has finished initializing |
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*/ |
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enum status_reg { |
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STATUS_READ_COMPLETE_EVENT = BIT(15), |
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STATUS_WRITE_COMPLETE_EVENT = BIT(14), |
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STATUS_TIMEOUT_EVENT = BIT(13), |
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STATUS_ERROR_EVENT = BIT(12), |
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STATUS_AXI_INT = BIT(11), |
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STATUS_READ_DATA_AVAILABLE = BIT(7), |
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STATUS_BUSY = BIT(6), |
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STATUS_INIT_DONE = BIT(5), |
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}; |
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/** |
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* enum control_reg - Description of bit fields in the interrupt_enable_control |
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* register |
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* @CONTROL_READ_COMPLETE_EVENT_ENABLE: STATUS_READ_COMPLETE_EVENT will be |
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* raised in the interrupt_status register |
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* @CONTROL_WRITE_COMPLETE_EVENT_ENABLE: STATUS_WRITE_COMPLETE_EVENT will be |
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* raised in the interrupt_status register |
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* @CONTROL_TIMEOUT_EVENT_ENABLE: STATUS_TIMEOUT_EVENT will be raised in |
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* the interrupt_status register |
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* @CONTROL_ERROR_EVENT_ENABLE: STATUS_ERROR_EVENT will be raised in |
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* the interrupt_status register |
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* @CONTROL_AXI_INT_ENABLE: STATUS_AXI_INT will be raised in the |
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* interrupt_status register |
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* @CONTROL_CMD_NOP: Configure bus to send a NOP command |
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* for the next transfer |
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* @CONTROL_CMD_WRITE: Configure bus to do a write transfer |
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* @CONTROL_CMD_WRITE_POST_INC: Auto-increment address after write |
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* transfer |
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* @CONTROL_CMD_READ: Configure bus to do a read transfer |
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* @CONTROL_CMD_READ_POST_INC: Auto-increment address after read |
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* transfer |
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*/ |
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enum control_reg { |
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CONTROL_READ_COMPLETE_EVENT_ENABLE = BIT(15), |
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CONTROL_WRITE_COMPLETE_EVENT_ENABLE = BIT(14), |
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CONTROL_TIMEOUT_EVENT_ENABLE = BIT(13), |
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CONTROL_ERROR_EVENT_ENABLE = BIT(12), |
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CONTROL_AXI_INT_ENABLE = BIT(11), |
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CONTROL_CMD_NOP = 0x0, |
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CONTROL_CMD_WRITE = 0x8, |
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CONTROL_CMD_WRITE_POST_INC = 0x9, |
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CONTROL_CMD_READ = 0xa, |
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CONTROL_CMD_READ_POST_INC = 0xb, |
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}; |
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/** |
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* enum axi_cmd - Determine if transfer is read or write transfer |
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* @AXI_CMD_READ: The transfer should be a read transfer |
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* @AXI_CMD_WRITE: The transfer should be a write transfer |
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*/ |
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enum axi_cmd { |
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AXI_CMD_READ, |
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AXI_CMD_WRITE, |
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}; |
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/** |
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* ihs_axi_transfer() - Run transfer on the AXI bus |
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* @bus: The AXI bus device on which to run the transfer on |
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* @address: The address to use in the transfer (i.e. which address to |
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* read/write from/to) |
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* @cmd: Should the transfer be a read or write transfer? |
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* |
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* Return: 0 if OK, -ve on error |
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*/ |
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static int ihs_axi_transfer(struct udevice *bus, ulong address, |
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enum axi_cmd cmd) |
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{ |
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struct ihs_axi_priv *priv = dev_get_priv(bus); |
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/* Try waiting for events up to 10 times */ |
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const uint WAIT_TRIES = 10; |
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u16 wait_mask = STATUS_TIMEOUT_EVENT | |
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STATUS_ERROR_EVENT; |
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u16 complete_flag; |
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u16 status; |
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uint k; |
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if (cmd == AXI_CMD_READ) { |
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complete_flag = STATUS_READ_COMPLETE_EVENT; |
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cmd = CONTROL_CMD_READ; |
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} else { |
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complete_flag = STATUS_WRITE_COMPLETE_EVENT; |
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cmd = CONTROL_CMD_WRITE; |
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} |
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wait_mask |= complete_flag; |
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/* Lower 16 bit */ |
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ihs_axi_set(priv->map, address_lsb, address & 0xffff); |
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/* Upper 16 bit */ |
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ihs_axi_set(priv->map, address_msb, (address >> 16) & 0xffff); |
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ihs_axi_set(priv->map, interrupt_status, wait_mask); |
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ihs_axi_set(priv->map, interrupt_enable_control, cmd); |
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for (k = WAIT_TRIES; k > 0; --k) { |
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ihs_axi_get(priv->map, interrupt_status, &status); |
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if (status & wait_mask) |
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break; |
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udelay(1); |
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} |
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/* |
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* k == 0 -> Tries ran out with no event we were waiting for actually |
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* occurring. |
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*/ |
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if (!k) |
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ihs_axi_get(priv->map, interrupt_status, &status); |
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if (status & complete_flag) |
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return 0; |
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if (status & STATUS_ERROR_EVENT) { |
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debug("%s: Error occurred during transfer\n", bus->name); |
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return -EIO; |
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} |
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debug("%s: Transfer timed out\n", bus->name); |
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return -ETIMEDOUT; |
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} |
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/* |
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* API |
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*/ |
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static int ihs_axi_read(struct udevice *dev, ulong address, void *data, |
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enum axi_size_t size) |
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{ |
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struct ihs_axi_priv *priv = dev_get_priv(dev); |
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int ret; |
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u16 data_lsb, data_msb; |
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u32 *p = data; |
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if (size != AXI_SIZE_32) { |
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debug("%s: transfer size '%d' not supported\n", |
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dev->name, size); |
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return -ENOSYS; |
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} |
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ret = ihs_axi_transfer(dev, address, AXI_CMD_READ); |
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if (ret < 0) { |
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debug("%s: Error during AXI transfer (err = %d)\n", |
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dev->name, ret); |
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return ret; |
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} |
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ihs_axi_get(priv->map, read_data_lsb, &data_lsb); |
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ihs_axi_get(priv->map, read_data_msb, &data_msb); |
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/* Assemble data from two 16-bit words */ |
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*p = (data_msb << 16) | data_lsb; |
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return 0; |
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} |
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static int ihs_axi_write(struct udevice *dev, ulong address, void *data, |
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enum axi_size_t size) |
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{ |
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struct ihs_axi_priv *priv = dev_get_priv(dev); |
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int ret; |
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u32 *p = data; |
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if (size != AXI_SIZE_32) { |
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debug("%s: transfer size '%d' not supported\n", |
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dev->name, size); |
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return -ENOSYS; |
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} |
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/* Lower 16 bit */ |
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ihs_axi_set(priv->map, write_data_lsb, *p & 0xffff); |
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/* Upper 16 bit */ |
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ihs_axi_set(priv->map, write_data_msb, (*p >> 16) & 0xffff); |
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ret = ihs_axi_transfer(dev, address, AXI_CMD_WRITE); |
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if (ret < 0) { |
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debug("%s: Error during AXI transfer (err = %d)\n", |
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dev->name, ret); |
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return ret; |
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} |
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return 0; |
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} |
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static const struct udevice_id ihs_axi_ids[] = { |
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{ .compatible = "gdsys,ihs_axi" }, |
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{ /* sentinel */ } |
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}; |
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static const struct axi_ops ihs_axi_ops = { |
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.read = ihs_axi_read, |
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.write = ihs_axi_write, |
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}; |
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static int ihs_axi_probe(struct udevice *dev) |
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{ |
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struct ihs_axi_priv *priv = dev_get_priv(dev); |
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regmap_init_mem(dev_ofnode(dev), &priv->map); |
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return 0; |
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} |
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U_BOOT_DRIVER(ihs_axi_bus) = { |
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.name = "ihs_axi_bus", |
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.id = UCLASS_AXI, |
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.of_match = ihs_axi_ids, |
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.ops = &ihs_axi_ops, |
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.priv_auto_alloc_size = sizeof(struct ihs_axi_priv), |
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.probe = ihs_axi_probe, |
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};
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