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177 lines
7.4 KiB
177 lines
7.4 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#include <linux/bitops.h> |
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#include <linux/serial_core.h> |
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#include <linux/io.h> |
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#define SCI_MAJOR 204 |
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#define SCI_MINOR_START 8 |
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/* |
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* SCI register subset common for all port types. |
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* Not all registers will exist on all parts. |
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*/ |
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enum { |
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SCSMR, /* Serial Mode Register */ |
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SCBRR, /* Bit Rate Register */ |
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SCSCR, /* Serial Control Register */ |
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SCxSR, /* Serial Status Register */ |
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SCFCR, /* FIFO Control Register */ |
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SCFDR, /* FIFO Data Count Register */ |
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SCxTDR, /* Transmit (FIFO) Data Register */ |
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SCxRDR, /* Receive (FIFO) Data Register */ |
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SCLSR, /* Line Status Register */ |
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SCTFDR, /* Transmit FIFO Data Count Register */ |
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SCRFDR, /* Receive FIFO Data Count Register */ |
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SCSPTR, /* Serial Port Register */ |
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HSSRR, /* Sampling Rate Register */ |
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SCPCR, /* Serial Port Control Register */ |
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SCPDR, /* Serial Port Data Register */ |
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SCDL, /* BRG Frequency Division Register */ |
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SCCKS, /* BRG Clock Select Register */ |
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HSRTRGR, /* Rx FIFO Data Count Trigger Register */ |
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HSTTRGR, /* Tx FIFO Data Count Trigger Register */ |
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SEMR, /* Serial extended mode register */ |
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SCIx_NR_REGS, |
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}; |
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/* SCSMR (Serial Mode Register) */ |
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#define SCSMR_C_A BIT(7) /* Communication Mode */ |
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#define SCSMR_CSYNC BIT(7) /* - Clocked synchronous mode */ |
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#define SCSMR_ASYNC 0 /* - Asynchronous mode */ |
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#define SCSMR_CHR BIT(6) /* 7-bit Character Length */ |
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#define SCSMR_PE BIT(5) /* Parity Enable */ |
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#define SCSMR_ODD BIT(4) /* Odd Parity */ |
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#define SCSMR_STOP BIT(3) /* Stop Bit Length */ |
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#define SCSMR_CKS 0x0003 /* Clock Select */ |
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/* Serial Mode Register, SCIFA/SCIFB only bits */ |
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#define SCSMR_CKEDG BIT(12) /* Transmit/Receive Clock Edge Select */ |
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#define SCSMR_SRC_MASK 0x0700 /* Sampling Control */ |
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#define SCSMR_SRC_16 0x0000 /* Sampling rate 1/16 */ |
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#define SCSMR_SRC_5 0x0100 /* Sampling rate 1/5 */ |
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#define SCSMR_SRC_7 0x0200 /* Sampling rate 1/7 */ |
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#define SCSMR_SRC_11 0x0300 /* Sampling rate 1/11 */ |
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#define SCSMR_SRC_13 0x0400 /* Sampling rate 1/13 */ |
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#define SCSMR_SRC_17 0x0500 /* Sampling rate 1/17 */ |
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#define SCSMR_SRC_19 0x0600 /* Sampling rate 1/19 */ |
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#define SCSMR_SRC_27 0x0700 /* Sampling rate 1/27 */ |
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/* Serial Control Register, SCIFA/SCIFB only bits */ |
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#define SCSCR_TDRQE BIT(15) /* Tx Data Transfer Request Enable */ |
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#define SCSCR_RDRQE BIT(14) /* Rx Data Transfer Request Enable */ |
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/* Serial Control Register, HSCIF-only bits */ |
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#define HSSCR_TOT_SHIFT 14 |
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/* SCxSR (Serial Status Register) on SCI */ |
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#define SCI_TDRE BIT(7) /* Transmit Data Register Empty */ |
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#define SCI_RDRF BIT(6) /* Receive Data Register Full */ |
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#define SCI_ORER BIT(5) /* Overrun Error */ |
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#define SCI_FER BIT(4) /* Framing Error */ |
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#define SCI_PER BIT(3) /* Parity Error */ |
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#define SCI_TEND BIT(2) /* Transmit End */ |
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#define SCI_RESERVED 0x03 /* All reserved bits */ |
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#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER) |
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#define SCI_RDxF_CLEAR (u32)(~(SCI_RESERVED | SCI_RDRF)) |
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#define SCI_ERROR_CLEAR (u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER)) |
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#define SCI_TDxE_CLEAR (u32)(~(SCI_RESERVED | SCI_TEND | SCI_TDRE)) |
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#define SCI_BREAK_CLEAR (u32)(~(SCI_RESERVED | SCI_PER | SCI_FER | SCI_ORER)) |
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/* SCxSR (Serial Status Register) on SCIF, SCIFA, SCIFB, HSCIF */ |
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#define SCIF_ER BIT(7) /* Receive Error */ |
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#define SCIF_TEND BIT(6) /* Transmission End */ |
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#define SCIF_TDFE BIT(5) /* Transmit FIFO Data Empty */ |
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#define SCIF_BRK BIT(4) /* Break Detect */ |
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#define SCIF_FER BIT(3) /* Framing Error */ |
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#define SCIF_PER BIT(2) /* Parity Error */ |
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#define SCIF_RDF BIT(1) /* Receive FIFO Data Full */ |
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#define SCIF_DR BIT(0) /* Receive Data Ready */ |
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/* SCIF only (optional) */ |
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#define SCIF_PERC 0xf000 /* Number of Parity Errors */ |
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#define SCIF_FERC 0x0f00 /* Number of Framing Errors */ |
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/*SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 only */ |
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#define SCIFA_ORER BIT(9) /* Overrun Error */ |
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#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_BRK | SCIF_ER) |
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#define SCIF_RDxF_CLEAR (u32)(~(SCIF_DR | SCIF_RDF)) |
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#define SCIF_ERROR_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_ER)) |
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#define SCIF_TDxE_CLEAR (u32)(~(SCIF_TDFE)) |
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#define SCIF_BREAK_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK)) |
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/* SCFCR (FIFO Control Register) */ |
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#define SCFCR_RTRG1 BIT(7) /* Receive FIFO Data Count Trigger */ |
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#define SCFCR_RTRG0 BIT(6) |
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#define SCFCR_TTRG1 BIT(5) /* Transmit FIFO Data Count Trigger */ |
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#define SCFCR_TTRG0 BIT(4) |
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#define SCFCR_MCE BIT(3) /* Modem Control Enable */ |
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#define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */ |
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#define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */ |
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#define SCFCR_LOOP BIT(0) /* Loopback Test */ |
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/* SCLSR (Line Status Register) on (H)SCIF */ |
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#define SCLSR_TO BIT(2) /* Timeout */ |
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#define SCLSR_ORER BIT(0) /* Overrun Error */ |
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/* SCSPTR (Serial Port Register), optional */ |
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#define SCSPTR_RTSIO BIT(7) /* Serial Port RTS# Pin Input/Output */ |
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#define SCSPTR_RTSDT BIT(6) /* Serial Port RTS# Pin Data */ |
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#define SCSPTR_CTSIO BIT(5) /* Serial Port CTS# Pin Input/Output */ |
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#define SCSPTR_CTSDT BIT(4) /* Serial Port CTS# Pin Data */ |
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#define SCSPTR_SCKIO BIT(3) /* Serial Port Clock Pin Input/Output */ |
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#define SCSPTR_SCKDT BIT(2) /* Serial Port Clock Pin Data */ |
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#define SCSPTR_SPB2IO BIT(1) /* Serial Port Break Input/Output */ |
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#define SCSPTR_SPB2DT BIT(0) /* Serial Port Break Data */ |
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/* HSSRR HSCIF */ |
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#define HSCIF_SRE BIT(15) /* Sampling Rate Register Enable */ |
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#define HSCIF_SRDE BIT(14) /* Sampling Point Register Enable */ |
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#define HSCIF_SRHP_SHIFT 8 |
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#define HSCIF_SRHP_MASK 0x0f00 |
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/* SCPCR (Serial Port Control Register), SCIFA/SCIFB only */ |
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#define SCPCR_RTSC BIT(4) /* Serial Port RTS# Pin / Output Pin */ |
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#define SCPCR_CTSC BIT(3) /* Serial Port CTS# Pin / Input Pin */ |
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#define SCPCR_SCKC BIT(2) /* Serial Port SCK Pin / Output Pin */ |
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#define SCPCR_RXDC BIT(1) /* Serial Port RXD Pin / Input Pin */ |
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#define SCPCR_TXDC BIT(0) /* Serial Port TXD Pin / Output Pin */ |
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/* SCPDR (Serial Port Data Register), SCIFA/SCIFB only */ |
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#define SCPDR_RTSD BIT(4) /* Serial Port RTS# Output Pin Data */ |
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#define SCPDR_CTSD BIT(3) /* Serial Port CTS# Input Pin Data */ |
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#define SCPDR_SCKD BIT(2) /* Serial Port SCK Output Pin Data */ |
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#define SCPDR_RXDD BIT(1) /* Serial Port RXD Input Pin Data */ |
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#define SCPDR_TXDD BIT(0) /* Serial Port TXD Output Pin Data */ |
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/* |
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* BRG Clock Select Register (Some SCIF and HSCIF) |
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* The Baud Rate Generator for external clock can provide a clock source for |
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* the sampling clock. It outputs either its frequency divided clock, or the |
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* (undivided) (H)SCK external clock. |
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*/ |
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#define SCCKS_CKS BIT(15) /* Select (H)SCK (1) or divided SC_CLK (0) */ |
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#define SCCKS_XIN BIT(14) /* SC_CLK uses bus clock (1) or SCIF_CLK (0) */ |
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#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) |
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#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_DR | SCIF_RDF) |
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#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) |
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#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) |
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#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) |
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#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) |
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#define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask) |
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#define SCxSR_RDxF_CLEAR(port) \ |
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(((port)->type == PORT_SCI) ? SCI_RDxF_CLEAR : SCIF_RDxF_CLEAR) |
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#define SCxSR_ERROR_CLEAR(port) \ |
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(to_sci_port(port)->params->error_clear) |
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#define SCxSR_TDxE_CLEAR(port) \ |
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(((port)->type == PORT_SCI) ? SCI_TDxE_CLEAR : SCIF_TDxE_CLEAR) |
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#define SCxSR_BREAK_CLEAR(port) \ |
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(((port)->type == PORT_SCI) ? SCI_BREAK_CLEAR : SCIF_BREAK_CLEAR)
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