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884 lines
24 KiB
884 lines
24 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Probe module for 8250/16550-type Exar chips PCI serial ports. |
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* |
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* Based on drivers/tty/serial/8250/8250_pci.c, |
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* |
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* Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved. |
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*/ |
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#include <linux/acpi.h> |
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#include <linux/dmi.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/property.h> |
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#include <linux/serial_core.h> |
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#include <linux/serial_reg.h> |
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#include <linux/slab.h> |
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#include <linux/string.h> |
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#include <linux/tty.h> |
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#include <linux/8250_pci.h> |
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#include <linux/delay.h> |
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#include <asm/byteorder.h> |
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#include "8250.h" |
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#define PCI_DEVICE_ID_ACCESSIO_COM_2S 0x1052 |
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#define PCI_DEVICE_ID_ACCESSIO_COM_4S 0x105d |
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#define PCI_DEVICE_ID_ACCESSIO_COM_8S 0x106c |
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#define PCI_DEVICE_ID_ACCESSIO_COM232_8 0x10a8 |
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#define PCI_DEVICE_ID_ACCESSIO_COM_2SM 0x10d2 |
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#define PCI_DEVICE_ID_ACCESSIO_COM_4SM 0x10db |
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#define PCI_DEVICE_ID_ACCESSIO_COM_8SM 0x10ea |
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#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002 |
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#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004 |
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#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a |
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#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b |
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#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020 |
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#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 |
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#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 |
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#define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358 |
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#define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358 |
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#define UART_EXAR_INT0 0x80 |
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#define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */ |
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#define UART_EXAR_SLEEP 0x8b /* Sleep mode */ |
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#define UART_EXAR_DVID 0x8d /* Device identification */ |
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#define UART_EXAR_FCTR 0x08 /* Feature Control Register */ |
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#define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */ |
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#define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */ |
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#define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */ |
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#define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */ |
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#define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */ |
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#define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */ |
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#define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */ |
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#define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */ |
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#define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */ |
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#define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */ |
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#define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */ |
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#define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */ |
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#define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */ |
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#define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */ |
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#define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */ |
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#define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */ |
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#define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */ |
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#define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */ |
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#define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */ |
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#define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */ |
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#define UART_EXAR_RS485_DLY(x) ((x) << 4) |
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/* |
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* IOT2040 MPIO wiring semantics: |
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* |
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* MPIO Port Function |
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* ---- ---- -------- |
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* 0 2 Mode bit 0 |
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* 1 2 Mode bit 1 |
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* 2 2 Terminate bus |
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* 3 - <reserved> |
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* 4 3 Mode bit 0 |
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* 5 3 Mode bit 1 |
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* 6 3 Terminate bus |
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* 7 - <reserved> |
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* 8 2 Enable |
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* 9 3 Enable |
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* 10 - Red LED |
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* 11..15 - <unused> |
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*/ |
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/* IOT2040 MPIOs 0..7 */ |
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#define IOT2040_UART_MODE_RS232 0x01 |
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#define IOT2040_UART_MODE_RS485 0x02 |
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#define IOT2040_UART_MODE_RS422 0x03 |
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#define IOT2040_UART_TERMINATE_BUS 0x04 |
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#define IOT2040_UART1_MASK 0x0f |
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#define IOT2040_UART2_SHIFT 4 |
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#define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */ |
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#define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */ |
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/* IOT2040 MPIOs 8..15 */ |
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#define IOT2040_UARTS_ENABLE 0x03 |
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#define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */ |
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struct exar8250; |
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struct exar8250_platform { |
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int (*rs485_config)(struct uart_port *, struct serial_rs485 *); |
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int (*register_gpio)(struct pci_dev *, struct uart_8250_port *); |
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void (*unregister_gpio)(struct uart_8250_port *); |
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}; |
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/** |
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* struct exar8250_board - board information |
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* @num_ports: number of serial ports |
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* @reg_shift: describes UART register mapping in PCI memory |
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* @setup: quirk run at ->probe() stage |
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* @exit: quirk run at ->remove() stage |
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*/ |
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struct exar8250_board { |
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unsigned int num_ports; |
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unsigned int reg_shift; |
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int (*setup)(struct exar8250 *, struct pci_dev *, |
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struct uart_8250_port *, int); |
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void (*exit)(struct pci_dev *pcidev); |
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}; |
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struct exar8250 { |
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unsigned int nr; |
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struct exar8250_board *board; |
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void __iomem *virt; |
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int line[]; |
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}; |
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static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old) |
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{ |
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/* |
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* Exar UARTs have a SLEEP register that enables or disables each UART |
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* to enter sleep mode separately. On the XR17V35x the register |
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* is accessible to each UART at the UART_EXAR_SLEEP offset, but |
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* the UART channel may only write to the corresponding bit. |
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*/ |
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serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0); |
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} |
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/* |
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* XR17V35x UARTs have an extra fractional divisor register (DLD) |
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* Calculate divisor with extra 4-bit fractional portion |
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*/ |
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static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud, |
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unsigned int *frac) |
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{ |
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unsigned int quot_16; |
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quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud); |
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*frac = quot_16 & 0x0f; |
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return quot_16 >> 4; |
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} |
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static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud, |
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unsigned int quot, unsigned int quot_frac) |
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{ |
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serial8250_do_set_divisor(p, baud, quot, quot_frac); |
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/* Preserve bits not related to baudrate; DLD[7:4]. */ |
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quot_frac |= serial_port_in(p, 0x2) & 0xf0; |
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serial_port_out(p, 0x2, quot_frac); |
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} |
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static int xr17v35x_startup(struct uart_port *port) |
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{ |
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/* |
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* First enable access to IER [7:5], ISR [5:4], FCR [5:4], |
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* MCR [7:5] and MSR [7:0] |
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*/ |
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serial_port_out(port, UART_XR_EFR, UART_EFR_ECB); |
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/* |
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* Make sure all interrups are masked until initialization is |
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* complete and the FIFOs are cleared |
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*/ |
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serial_port_out(port, UART_IER, 0); |
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return serial8250_do_startup(port); |
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} |
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static void exar_shutdown(struct uart_port *port) |
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{ |
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unsigned char lsr; |
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bool tx_complete = false; |
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struct uart_8250_port *up = up_to_u8250p(port); |
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struct circ_buf *xmit = &port->state->xmit; |
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int i = 0; |
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do { |
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lsr = serial_in(up, UART_LSR); |
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if (lsr & (UART_LSR_TEMT | UART_LSR_THRE)) |
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tx_complete = true; |
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else |
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tx_complete = false; |
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usleep_range(1000, 1100); |
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} while (!uart_circ_empty(xmit) && !tx_complete && i++ < 1000); |
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serial8250_do_shutdown(port); |
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} |
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static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev, |
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int idx, unsigned int offset, |
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struct uart_8250_port *port) |
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{ |
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const struct exar8250_board *board = priv->board; |
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unsigned int bar = 0; |
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unsigned char status; |
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port->port.iotype = UPIO_MEM; |
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port->port.mapbase = pci_resource_start(pcidev, bar) + offset; |
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port->port.membase = priv->virt + offset; |
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port->port.regshift = board->reg_shift; |
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/* |
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* XR17V35x UARTs have an extra divisor register, DLD that gets enabled |
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* with when DLAB is set which will cause the device to incorrectly match |
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* and assign port type to PORT_16650. The EFR for this UART is found |
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* at offset 0x09. Instead check the Deice ID (DVID) register |
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* for a 2, 4 or 8 port UART. |
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*/ |
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status = readb(port->port.membase + UART_EXAR_DVID); |
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if (status == 0x82 || status == 0x84 || status == 0x88) { |
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port->port.type = PORT_XR17V35X; |
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port->port.get_divisor = xr17v35x_get_divisor; |
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port->port.set_divisor = xr17v35x_set_divisor; |
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port->port.startup = xr17v35x_startup; |
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} else { |
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port->port.type = PORT_XR17D15X; |
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} |
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port->port.pm = exar_pm; |
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port->port.shutdown = exar_shutdown; |
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return 0; |
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} |
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static int |
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pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev, |
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struct uart_8250_port *port, int idx) |
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{ |
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unsigned int offset = idx * 0x200; |
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unsigned int baud = 1843200; |
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u8 __iomem *p; |
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int err; |
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port->port.uartclk = baud * 16; |
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err = default_setup(priv, pcidev, idx, offset, port); |
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if (err) |
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return err; |
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p = port->port.membase; |
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writeb(0x00, p + UART_EXAR_8XMODE); |
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writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); |
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writeb(32, p + UART_EXAR_TXTRG); |
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writeb(32, p + UART_EXAR_RXTRG); |
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/* |
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* Setup Multipurpose Input/Output pins. |
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*/ |
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if (idx == 0) { |
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switch (pcidev->device) { |
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case PCI_DEVICE_ID_COMMTECH_4222PCI335: |
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case PCI_DEVICE_ID_COMMTECH_4224PCI335: |
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writeb(0x78, p + UART_EXAR_MPIOLVL_7_0); |
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writeb(0x00, p + UART_EXAR_MPIOINV_7_0); |
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writeb(0x00, p + UART_EXAR_MPIOSEL_7_0); |
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break; |
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case PCI_DEVICE_ID_COMMTECH_2324PCI335: |
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case PCI_DEVICE_ID_COMMTECH_2328PCI335: |
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writeb(0x00, p + UART_EXAR_MPIOLVL_7_0); |
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writeb(0xc0, p + UART_EXAR_MPIOINV_7_0); |
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writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0); |
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break; |
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} |
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writeb(0x00, p + UART_EXAR_MPIOINT_7_0); |
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writeb(0x00, p + UART_EXAR_MPIO3T_7_0); |
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writeb(0x00, p + UART_EXAR_MPIOOD_7_0); |
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} |
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return 0; |
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} |
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static int |
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pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev, |
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struct uart_8250_port *port, int idx) |
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{ |
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unsigned int offset = idx * 0x200; |
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unsigned int baud = 1843200; |
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port->port.uartclk = baud * 16; |
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return default_setup(priv, pcidev, idx, offset, port); |
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} |
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static int |
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pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev, |
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struct uart_8250_port *port, int idx) |
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{ |
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unsigned int offset = idx * 0x200; |
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unsigned int baud = 921600; |
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port->port.uartclk = baud * 16; |
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return default_setup(priv, pcidev, idx, offset, port); |
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} |
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static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p) |
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{ |
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/* |
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* The Commtech adapters required the MPIOs to be driven low. The Exar |
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* devices will export them as GPIOs, so we pre-configure them safely |
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* as inputs. |
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*/ |
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u8 dir = 0x00; |
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if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) && |
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(pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) { |
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// Configure GPIO as inputs for Commtech adapters |
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dir = 0xff; |
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} else { |
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// Configure GPIO as outputs for SeaLevel adapters |
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dir = 0x00; |
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} |
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writeb(0x00, p + UART_EXAR_MPIOINT_7_0); |
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writeb(0x00, p + UART_EXAR_MPIOLVL_7_0); |
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writeb(0x00, p + UART_EXAR_MPIO3T_7_0); |
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writeb(0x00, p + UART_EXAR_MPIOINV_7_0); |
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writeb(dir, p + UART_EXAR_MPIOSEL_7_0); |
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writeb(0x00, p + UART_EXAR_MPIOOD_7_0); |
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writeb(0x00, p + UART_EXAR_MPIOINT_15_8); |
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writeb(0x00, p + UART_EXAR_MPIOLVL_15_8); |
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writeb(0x00, p + UART_EXAR_MPIO3T_15_8); |
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writeb(0x00, p + UART_EXAR_MPIOINV_15_8); |
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writeb(dir, p + UART_EXAR_MPIOSEL_15_8); |
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writeb(0x00, p + UART_EXAR_MPIOOD_15_8); |
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} |
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static struct platform_device *__xr17v35x_register_gpio(struct pci_dev *pcidev, |
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const struct software_node *node) |
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{ |
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struct platform_device *pdev; |
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pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO); |
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if (!pdev) |
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return NULL; |
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pdev->dev.parent = &pcidev->dev; |
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ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev)); |
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if (device_add_software_node(&pdev->dev, node) < 0 || |
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platform_device_add(pdev) < 0) { |
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platform_device_put(pdev); |
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return NULL; |
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} |
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return pdev; |
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} |
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static void __xr17v35x_unregister_gpio(struct platform_device *pdev) |
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{ |
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device_remove_software_node(&pdev->dev); |
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platform_device_unregister(pdev); |
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} |
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static const struct property_entry exar_gpio_properties[] = { |
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PROPERTY_ENTRY_U32("exar,first-pin", 0), |
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PROPERTY_ENTRY_U32("ngpios", 16), |
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{ } |
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}; |
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static const struct software_node exar_gpio_node = { |
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.properties = exar_gpio_properties, |
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}; |
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static int xr17v35x_register_gpio(struct pci_dev *pcidev, struct uart_8250_port *port) |
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{ |
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if (pcidev->vendor == PCI_VENDOR_ID_EXAR) |
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port->port.private_data = |
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__xr17v35x_register_gpio(pcidev, &exar_gpio_node); |
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return 0; |
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} |
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static void xr17v35x_unregister_gpio(struct uart_8250_port *port) |
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{ |
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if (!port->port.private_data) |
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return; |
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__xr17v35x_unregister_gpio(port->port.private_data); |
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port->port.private_data = NULL; |
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} |
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static int generic_rs485_config(struct uart_port *port, |
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struct serial_rs485 *rs485) |
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{ |
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bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED); |
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u8 __iomem *p = port->membase; |
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u8 value; |
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value = readb(p + UART_EXAR_FCTR); |
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if (is_rs485) |
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value |= UART_FCTR_EXAR_485; |
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else |
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value &= ~UART_FCTR_EXAR_485; |
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writeb(value, p + UART_EXAR_FCTR); |
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if (is_rs485) |
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writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR); |
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port->rs485 = *rs485; |
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return 0; |
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} |
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static const struct exar8250_platform exar8250_default_platform = { |
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.register_gpio = xr17v35x_register_gpio, |
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.unregister_gpio = xr17v35x_unregister_gpio, |
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.rs485_config = generic_rs485_config, |
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}; |
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static int iot2040_rs485_config(struct uart_port *port, |
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struct serial_rs485 *rs485) |
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{ |
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bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED); |
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u8 __iomem *p = port->membase; |
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u8 mask = IOT2040_UART1_MASK; |
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u8 mode, value; |
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if (is_rs485) { |
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if (rs485->flags & SER_RS485_RX_DURING_TX) |
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mode = IOT2040_UART_MODE_RS422; |
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else |
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mode = IOT2040_UART_MODE_RS485; |
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if (rs485->flags & SER_RS485_TERMINATE_BUS) |
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mode |= IOT2040_UART_TERMINATE_BUS; |
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} else { |
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mode = IOT2040_UART_MODE_RS232; |
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} |
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if (port->line == 3) { |
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mask <<= IOT2040_UART2_SHIFT; |
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mode <<= IOT2040_UART2_SHIFT; |
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} |
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value = readb(p + UART_EXAR_MPIOLVL_7_0); |
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value &= ~mask; |
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value |= mode; |
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writeb(value, p + UART_EXAR_MPIOLVL_7_0); |
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return generic_rs485_config(port, rs485); |
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} |
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static const struct property_entry iot2040_gpio_properties[] = { |
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PROPERTY_ENTRY_U32("exar,first-pin", 10), |
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PROPERTY_ENTRY_U32("ngpios", 1), |
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{ } |
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}; |
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static const struct software_node iot2040_gpio_node = { |
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.properties = iot2040_gpio_properties, |
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}; |
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static int iot2040_register_gpio(struct pci_dev *pcidev, |
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struct uart_8250_port *port) |
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{ |
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u8 __iomem *p = port->port.membase; |
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writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0); |
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writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0); |
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writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8); |
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writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8); |
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port->port.private_data = |
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__xr17v35x_register_gpio(pcidev, &iot2040_gpio_node); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct exar8250_platform iot2040_platform = { |
|
.rs485_config = iot2040_rs485_config, |
|
.register_gpio = iot2040_register_gpio, |
|
.unregister_gpio = xr17v35x_unregister_gpio, |
|
}; |
|
|
|
/* |
|
* For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device, |
|
* IOT2020 doesn't have. Therefore it is sufficient to match on the common |
|
* board name after the device was found. |
|
*/ |
|
static const struct dmi_system_id exar_platforms[] = { |
|
{ |
|
.matches = { |
|
DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), |
|
}, |
|
.driver_data = (void *)&iot2040_platform, |
|
}, |
|
{} |
|
}; |
|
|
|
static const struct exar8250_platform *exar_get_platform(void) |
|
{ |
|
const struct dmi_system_id *dmi_match; |
|
|
|
dmi_match = dmi_first_match(exar_platforms); |
|
if (dmi_match) |
|
return dmi_match->driver_data; |
|
|
|
return &exar8250_default_platform; |
|
} |
|
|
|
static int |
|
pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev, |
|
struct uart_8250_port *port, int idx) |
|
{ |
|
const struct exar8250_platform *platform = exar_get_platform(); |
|
unsigned int offset = idx * 0x400; |
|
unsigned int baud = 7812500; |
|
u8 __iomem *p; |
|
int ret; |
|
|
|
port->port.uartclk = baud * 16; |
|
port->port.rs485_config = platform->rs485_config; |
|
|
|
/* |
|
* Setup the UART clock for the devices on expansion slot to |
|
* half the clock speed of the main chip (which is 125MHz) |
|
*/ |
|
if (idx >= 8) |
|
port->port.uartclk /= 2; |
|
|
|
ret = default_setup(priv, pcidev, idx, offset, port); |
|
if (ret) |
|
return ret; |
|
|
|
p = port->port.membase; |
|
|
|
writeb(0x00, p + UART_EXAR_8XMODE); |
|
writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); |
|
writeb(128, p + UART_EXAR_TXTRG); |
|
writeb(128, p + UART_EXAR_RXTRG); |
|
|
|
if (idx == 0) { |
|
/* Setup Multipurpose Input/Output pins. */ |
|
setup_gpio(pcidev, p); |
|
|
|
ret = platform->register_gpio(pcidev, port); |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
static void pci_xr17v35x_exit(struct pci_dev *pcidev) |
|
{ |
|
const struct exar8250_platform *platform = exar_get_platform(); |
|
struct exar8250 *priv = pci_get_drvdata(pcidev); |
|
struct uart_8250_port *port = serial8250_get_port(priv->line[0]); |
|
|
|
platform->unregister_gpio(port); |
|
} |
|
|
|
static inline void exar_misc_clear(struct exar8250 *priv) |
|
{ |
|
/* Clear all PCI interrupts by reading INT0. No effect on IIR */ |
|
readb(priv->virt + UART_EXAR_INT0); |
|
|
|
/* Clear INT0 for Expansion Interface slave ports, too */ |
|
if (priv->board->num_ports > 8) |
|
readb(priv->virt + 0x2000 + UART_EXAR_INT0); |
|
} |
|
|
|
/* |
|
* These Exar UARTs have an extra interrupt indicator that could fire for a |
|
* few interrupts that are not presented/cleared through IIR. One of which is |
|
* a wakeup interrupt when coming out of sleep. These interrupts are only |
|
* cleared by reading global INT0 or INT1 registers as interrupts are |
|
* associated with channel 0. The INT[3:0] registers _are_ accessible from each |
|
* channel's address space, but for the sake of bus efficiency we register a |
|
* dedicated handler at the PCI device level to handle them. |
|
*/ |
|
static irqreturn_t exar_misc_handler(int irq, void *data) |
|
{ |
|
exar_misc_clear(data); |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static int |
|
exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent) |
|
{ |
|
unsigned int nr_ports, i, bar = 0, maxnr; |
|
struct exar8250_board *board; |
|
struct uart_8250_port uart; |
|
struct exar8250 *priv; |
|
int rc; |
|
|
|
board = (struct exar8250_board *)ent->driver_data; |
|
if (!board) |
|
return -EINVAL; |
|
|
|
rc = pcim_enable_device(pcidev); |
|
if (rc) |
|
return rc; |
|
|
|
maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3); |
|
|
|
nr_ports = board->num_ports ? board->num_ports : pcidev->device & 0x0f; |
|
|
|
priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL); |
|
if (!priv) |
|
return -ENOMEM; |
|
|
|
priv->board = board; |
|
priv->virt = pcim_iomap(pcidev, bar, 0); |
|
if (!priv->virt) |
|
return -ENOMEM; |
|
|
|
pci_set_master(pcidev); |
|
|
|
rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES); |
|
if (rc < 0) |
|
return rc; |
|
|
|
memset(&uart, 0, sizeof(uart)); |
|
uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT; |
|
uart.port.irq = pci_irq_vector(pcidev, 0); |
|
uart.port.dev = &pcidev->dev; |
|
|
|
rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler, |
|
IRQF_SHARED, "exar_uart", priv); |
|
if (rc) |
|
return rc; |
|
|
|
/* Clear interrupts */ |
|
exar_misc_clear(priv); |
|
|
|
for (i = 0; i < nr_ports && i < maxnr; i++) { |
|
rc = board->setup(priv, pcidev, &uart, i); |
|
if (rc) { |
|
dev_err(&pcidev->dev, "Failed to setup port %u\n", i); |
|
break; |
|
} |
|
|
|
dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", |
|
uart.port.iobase, uart.port.irq, uart.port.iotype); |
|
|
|
priv->line[i] = serial8250_register_8250_port(&uart); |
|
if (priv->line[i] < 0) { |
|
dev_err(&pcidev->dev, |
|
"Couldn't register serial port %lx, irq %d, type %d, error %d\n", |
|
uart.port.iobase, uart.port.irq, |
|
uart.port.iotype, priv->line[i]); |
|
break; |
|
} |
|
} |
|
priv->nr = i; |
|
pci_set_drvdata(pcidev, priv); |
|
return 0; |
|
} |
|
|
|
static void exar_pci_remove(struct pci_dev *pcidev) |
|
{ |
|
struct exar8250 *priv = pci_get_drvdata(pcidev); |
|
unsigned int i; |
|
|
|
for (i = 0; i < priv->nr; i++) |
|
serial8250_unregister_port(priv->line[i]); |
|
|
|
if (priv->board->exit) |
|
priv->board->exit(pcidev); |
|
} |
|
|
|
static int __maybe_unused exar_suspend(struct device *dev) |
|
{ |
|
struct pci_dev *pcidev = to_pci_dev(dev); |
|
struct exar8250 *priv = pci_get_drvdata(pcidev); |
|
unsigned int i; |
|
|
|
for (i = 0; i < priv->nr; i++) |
|
if (priv->line[i] >= 0) |
|
serial8250_suspend_port(priv->line[i]); |
|
|
|
/* Ensure that every init quirk is properly torn down */ |
|
if (priv->board->exit) |
|
priv->board->exit(pcidev); |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused exar_resume(struct device *dev) |
|
{ |
|
struct exar8250 *priv = dev_get_drvdata(dev); |
|
unsigned int i; |
|
|
|
exar_misc_clear(priv); |
|
|
|
for (i = 0; i < priv->nr; i++) |
|
if (priv->line[i] >= 0) |
|
serial8250_resume_port(priv->line[i]); |
|
|
|
return 0; |
|
} |
|
|
|
static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume); |
|
|
|
static const struct exar8250_board acces_com_2x = { |
|
.num_ports = 2, |
|
.setup = pci_xr17c154_setup, |
|
}; |
|
|
|
static const struct exar8250_board acces_com_4x = { |
|
.num_ports = 4, |
|
.setup = pci_xr17c154_setup, |
|
}; |
|
|
|
static const struct exar8250_board acces_com_8x = { |
|
.num_ports = 8, |
|
.setup = pci_xr17c154_setup, |
|
}; |
|
|
|
|
|
static const struct exar8250_board pbn_fastcom335_2 = { |
|
.num_ports = 2, |
|
.setup = pci_fastcom335_setup, |
|
}; |
|
|
|
static const struct exar8250_board pbn_fastcom335_4 = { |
|
.num_ports = 4, |
|
.setup = pci_fastcom335_setup, |
|
}; |
|
|
|
static const struct exar8250_board pbn_fastcom335_8 = { |
|
.num_ports = 8, |
|
.setup = pci_fastcom335_setup, |
|
}; |
|
|
|
static const struct exar8250_board pbn_connect = { |
|
.setup = pci_connect_tech_setup, |
|
}; |
|
|
|
static const struct exar8250_board pbn_exar_ibm_saturn = { |
|
.num_ports = 1, |
|
.setup = pci_xr17c154_setup, |
|
}; |
|
|
|
static const struct exar8250_board pbn_exar_XR17C15x = { |
|
.setup = pci_xr17c154_setup, |
|
}; |
|
|
|
static const struct exar8250_board pbn_exar_XR17V35x = { |
|
.setup = pci_xr17v35x_setup, |
|
.exit = pci_xr17v35x_exit, |
|
}; |
|
|
|
static const struct exar8250_board pbn_fastcom35x_2 = { |
|
.num_ports = 2, |
|
.setup = pci_xr17v35x_setup, |
|
.exit = pci_xr17v35x_exit, |
|
}; |
|
|
|
static const struct exar8250_board pbn_fastcom35x_4 = { |
|
.num_ports = 4, |
|
.setup = pci_xr17v35x_setup, |
|
.exit = pci_xr17v35x_exit, |
|
}; |
|
|
|
static const struct exar8250_board pbn_fastcom35x_8 = { |
|
.num_ports = 8, |
|
.setup = pci_xr17v35x_setup, |
|
.exit = pci_xr17v35x_exit, |
|
}; |
|
|
|
static const struct exar8250_board pbn_exar_XR17V4358 = { |
|
.num_ports = 12, |
|
.setup = pci_xr17v35x_setup, |
|
.exit = pci_xr17v35x_exit, |
|
}; |
|
|
|
static const struct exar8250_board pbn_exar_XR17V8358 = { |
|
.num_ports = 16, |
|
.setup = pci_xr17v35x_setup, |
|
.exit = pci_xr17v35x_exit, |
|
}; |
|
|
|
#define CONNECT_DEVICE(devid, sdevid, bd) { \ |
|
PCI_DEVICE_SUB( \ |
|
PCI_VENDOR_ID_EXAR, \ |
|
PCI_DEVICE_ID_EXAR_##devid, \ |
|
PCI_SUBVENDOR_ID_CONNECT_TECH, \ |
|
PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \ |
|
(kernel_ulong_t)&bd \ |
|
} |
|
|
|
#define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) } |
|
|
|
#define IBM_DEVICE(devid, sdevid, bd) { \ |
|
PCI_DEVICE_SUB( \ |
|
PCI_VENDOR_ID_EXAR, \ |
|
PCI_DEVICE_ID_EXAR_##devid, \ |
|
PCI_VENDOR_ID_IBM, \ |
|
PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \ |
|
(kernel_ulong_t)&bd \ |
|
} |
|
|
|
static const struct pci_device_id exar_pci_tbl[] = { |
|
EXAR_DEVICE(ACCESSIO, COM_2S, acces_com_2x), |
|
EXAR_DEVICE(ACCESSIO, COM_4S, acces_com_4x), |
|
EXAR_DEVICE(ACCESSIO, COM_8S, acces_com_8x), |
|
EXAR_DEVICE(ACCESSIO, COM232_8, acces_com_8x), |
|
EXAR_DEVICE(ACCESSIO, COM_2SM, acces_com_2x), |
|
EXAR_DEVICE(ACCESSIO, COM_4SM, acces_com_4x), |
|
EXAR_DEVICE(ACCESSIO, COM_8SM, acces_com_8x), |
|
|
|
CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect), |
|
CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect), |
|
CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect), |
|
CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect), |
|
CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect), |
|
CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect), |
|
CONNECT_DEVICE(XR17C152, UART_2, pbn_connect), |
|
CONNECT_DEVICE(XR17C154, UART_4, pbn_connect), |
|
CONNECT_DEVICE(XR17C158, UART_8, pbn_connect), |
|
CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect), |
|
CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect), |
|
CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect), |
|
|
|
IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn), |
|
|
|
/* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */ |
|
EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x), |
|
EXAR_DEVICE(EXAR, XR17C154, pbn_exar_XR17C15x), |
|
EXAR_DEVICE(EXAR, XR17C158, pbn_exar_XR17C15x), |
|
|
|
/* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */ |
|
EXAR_DEVICE(EXAR, XR17V352, pbn_exar_XR17V35x), |
|
EXAR_DEVICE(EXAR, XR17V354, pbn_exar_XR17V35x), |
|
EXAR_DEVICE(EXAR, XR17V358, pbn_exar_XR17V35x), |
|
EXAR_DEVICE(EXAR, XR17V4358, pbn_exar_XR17V4358), |
|
EXAR_DEVICE(EXAR, XR17V8358, pbn_exar_XR17V8358), |
|
EXAR_DEVICE(COMMTECH, 4222PCIE, pbn_fastcom35x_2), |
|
EXAR_DEVICE(COMMTECH, 4224PCIE, pbn_fastcom35x_4), |
|
EXAR_DEVICE(COMMTECH, 4228PCIE, pbn_fastcom35x_8), |
|
|
|
EXAR_DEVICE(COMMTECH, 4222PCI335, pbn_fastcom335_2), |
|
EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4), |
|
EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4), |
|
EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8), |
|
{ 0, } |
|
}; |
|
MODULE_DEVICE_TABLE(pci, exar_pci_tbl); |
|
|
|
static struct pci_driver exar_pci_driver = { |
|
.name = "exar_serial", |
|
.probe = exar_pci_probe, |
|
.remove = exar_pci_remove, |
|
.driver = { |
|
.pm = &exar_pci_pm, |
|
}, |
|
.id_table = exar_pci_tbl, |
|
}; |
|
module_pci_driver(exar_pci_driver); |
|
|
|
MODULE_LICENSE("GPL"); |
|
MODULE_DESCRIPTION("Exar Serial Driver"); |
|
MODULE_AUTHOR("Sudip Mukherjee <[email protected]>");
|
|
|