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542 lines
13 KiB
542 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// |
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// Copyright (c) 2021 MediaTek Inc. |
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#include <linux/clk.h> |
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#include <linux/iopoll.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/property.h> |
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#include <linux/spmi.h> |
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#define SWINF_IDLE 0x00 |
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#define SWINF_WFVLDCLR 0x06 |
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#define GET_SWINF(x) (((x) >> 1) & 0x7) |
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#define PMIF_CMD_REG_0 0 |
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#define PMIF_CMD_REG 1 |
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#define PMIF_CMD_EXT_REG 2 |
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#define PMIF_CMD_EXT_REG_LONG 3 |
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#define PMIF_DELAY_US 10 |
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#define PMIF_TIMEOUT_US (10 * 1000) |
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#define PMIF_CHAN_OFFSET 0x5 |
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#define PMIF_MAX_CLKS 3 |
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#define SPMI_OP_ST_BUSY 1 |
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struct ch_reg { |
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u32 ch_sta; |
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u32 wdata; |
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u32 rdata; |
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u32 ch_send; |
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u32 ch_rdy; |
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}; |
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struct pmif_data { |
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const u32 *regs; |
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const u32 *spmimst_regs; |
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u32 soc_chan; |
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}; |
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struct pmif { |
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void __iomem *base; |
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void __iomem *spmimst_base; |
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struct ch_reg chan; |
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struct clk_bulk_data clks[PMIF_MAX_CLKS]; |
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size_t nclks; |
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const struct pmif_data *data; |
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}; |
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static const char * const pmif_clock_names[] = { |
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"pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux", |
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}; |
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enum pmif_regs { |
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PMIF_INIT_DONE, |
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PMIF_INF_EN, |
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PMIF_ARB_EN, |
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PMIF_CMDISSUE_EN, |
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PMIF_TIMER_CTRL, |
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PMIF_SPI_MODE_CTRL, |
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PMIF_IRQ_EVENT_EN_0, |
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PMIF_IRQ_FLAG_0, |
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PMIF_IRQ_CLR_0, |
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PMIF_IRQ_EVENT_EN_1, |
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PMIF_IRQ_FLAG_1, |
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PMIF_IRQ_CLR_1, |
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PMIF_IRQ_EVENT_EN_2, |
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PMIF_IRQ_FLAG_2, |
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PMIF_IRQ_CLR_2, |
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PMIF_IRQ_EVENT_EN_3, |
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PMIF_IRQ_FLAG_3, |
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PMIF_IRQ_CLR_3, |
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PMIF_IRQ_EVENT_EN_4, |
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PMIF_IRQ_FLAG_4, |
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PMIF_IRQ_CLR_4, |
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PMIF_WDT_EVENT_EN_0, |
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PMIF_WDT_FLAG_0, |
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PMIF_WDT_EVENT_EN_1, |
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PMIF_WDT_FLAG_1, |
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PMIF_SWINF_0_STA, |
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PMIF_SWINF_0_WDATA_31_0, |
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PMIF_SWINF_0_RDATA_31_0, |
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PMIF_SWINF_0_ACC, |
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PMIF_SWINF_0_VLD_CLR, |
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PMIF_SWINF_1_STA, |
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PMIF_SWINF_1_WDATA_31_0, |
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PMIF_SWINF_1_RDATA_31_0, |
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PMIF_SWINF_1_ACC, |
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PMIF_SWINF_1_VLD_CLR, |
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PMIF_SWINF_2_STA, |
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PMIF_SWINF_2_WDATA_31_0, |
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PMIF_SWINF_2_RDATA_31_0, |
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PMIF_SWINF_2_ACC, |
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PMIF_SWINF_2_VLD_CLR, |
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PMIF_SWINF_3_STA, |
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PMIF_SWINF_3_WDATA_31_0, |
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PMIF_SWINF_3_RDATA_31_0, |
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PMIF_SWINF_3_ACC, |
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PMIF_SWINF_3_VLD_CLR, |
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}; |
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static const u32 mt6873_regs[] = { |
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[PMIF_INIT_DONE] = 0x0000, |
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[PMIF_INF_EN] = 0x0024, |
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[PMIF_ARB_EN] = 0x0150, |
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[PMIF_CMDISSUE_EN] = 0x03B4, |
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[PMIF_TIMER_CTRL] = 0x03E0, |
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[PMIF_SPI_MODE_CTRL] = 0x0400, |
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[PMIF_IRQ_EVENT_EN_0] = 0x0418, |
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[PMIF_IRQ_FLAG_0] = 0x0420, |
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[PMIF_IRQ_CLR_0] = 0x0424, |
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[PMIF_IRQ_EVENT_EN_1] = 0x0428, |
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[PMIF_IRQ_FLAG_1] = 0x0430, |
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[PMIF_IRQ_CLR_1] = 0x0434, |
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[PMIF_IRQ_EVENT_EN_2] = 0x0438, |
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[PMIF_IRQ_FLAG_2] = 0x0440, |
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[PMIF_IRQ_CLR_2] = 0x0444, |
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[PMIF_IRQ_EVENT_EN_3] = 0x0448, |
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[PMIF_IRQ_FLAG_3] = 0x0450, |
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[PMIF_IRQ_CLR_3] = 0x0454, |
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[PMIF_IRQ_EVENT_EN_4] = 0x0458, |
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[PMIF_IRQ_FLAG_4] = 0x0460, |
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[PMIF_IRQ_CLR_4] = 0x0464, |
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[PMIF_WDT_EVENT_EN_0] = 0x046C, |
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[PMIF_WDT_FLAG_0] = 0x0470, |
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[PMIF_WDT_EVENT_EN_1] = 0x0474, |
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[PMIF_WDT_FLAG_1] = 0x0478, |
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[PMIF_SWINF_0_ACC] = 0x0C00, |
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[PMIF_SWINF_0_WDATA_31_0] = 0x0C04, |
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[PMIF_SWINF_0_RDATA_31_0] = 0x0C14, |
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[PMIF_SWINF_0_VLD_CLR] = 0x0C24, |
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[PMIF_SWINF_0_STA] = 0x0C28, |
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[PMIF_SWINF_1_ACC] = 0x0C40, |
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[PMIF_SWINF_1_WDATA_31_0] = 0x0C44, |
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[PMIF_SWINF_1_RDATA_31_0] = 0x0C54, |
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[PMIF_SWINF_1_VLD_CLR] = 0x0C64, |
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[PMIF_SWINF_1_STA] = 0x0C68, |
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[PMIF_SWINF_2_ACC] = 0x0C80, |
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[PMIF_SWINF_2_WDATA_31_0] = 0x0C84, |
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[PMIF_SWINF_2_RDATA_31_0] = 0x0C94, |
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[PMIF_SWINF_2_VLD_CLR] = 0x0CA4, |
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[PMIF_SWINF_2_STA] = 0x0CA8, |
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[PMIF_SWINF_3_ACC] = 0x0CC0, |
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[PMIF_SWINF_3_WDATA_31_0] = 0x0CC4, |
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[PMIF_SWINF_3_RDATA_31_0] = 0x0CD4, |
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[PMIF_SWINF_3_VLD_CLR] = 0x0CE4, |
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[PMIF_SWINF_3_STA] = 0x0CE8, |
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}; |
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static const u32 mt8195_regs[] = { |
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[PMIF_INIT_DONE] = 0x0000, |
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[PMIF_INF_EN] = 0x0024, |
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[PMIF_ARB_EN] = 0x0150, |
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[PMIF_CMDISSUE_EN] = 0x03B8, |
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[PMIF_TIMER_CTRL] = 0x03E4, |
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[PMIF_SPI_MODE_CTRL] = 0x0408, |
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[PMIF_IRQ_EVENT_EN_0] = 0x0420, |
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[PMIF_IRQ_FLAG_0] = 0x0428, |
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[PMIF_IRQ_CLR_0] = 0x042C, |
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[PMIF_IRQ_EVENT_EN_1] = 0x0430, |
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[PMIF_IRQ_FLAG_1] = 0x0438, |
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[PMIF_IRQ_CLR_1] = 0x043C, |
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[PMIF_IRQ_EVENT_EN_2] = 0x0440, |
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[PMIF_IRQ_FLAG_2] = 0x0448, |
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[PMIF_IRQ_CLR_2] = 0x044C, |
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[PMIF_IRQ_EVENT_EN_3] = 0x0450, |
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[PMIF_IRQ_FLAG_3] = 0x0458, |
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[PMIF_IRQ_CLR_3] = 0x045C, |
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[PMIF_IRQ_EVENT_EN_4] = 0x0460, |
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[PMIF_IRQ_FLAG_4] = 0x0468, |
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[PMIF_IRQ_CLR_4] = 0x046C, |
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[PMIF_WDT_EVENT_EN_0] = 0x0474, |
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[PMIF_WDT_FLAG_0] = 0x0478, |
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[PMIF_WDT_EVENT_EN_1] = 0x047C, |
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[PMIF_WDT_FLAG_1] = 0x0480, |
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[PMIF_SWINF_0_ACC] = 0x0800, |
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[PMIF_SWINF_0_WDATA_31_0] = 0x0804, |
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[PMIF_SWINF_0_RDATA_31_0] = 0x0814, |
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[PMIF_SWINF_0_VLD_CLR] = 0x0824, |
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[PMIF_SWINF_0_STA] = 0x0828, |
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[PMIF_SWINF_1_ACC] = 0x0840, |
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[PMIF_SWINF_1_WDATA_31_0] = 0x0844, |
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[PMIF_SWINF_1_RDATA_31_0] = 0x0854, |
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[PMIF_SWINF_1_VLD_CLR] = 0x0864, |
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[PMIF_SWINF_1_STA] = 0x0868, |
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[PMIF_SWINF_2_ACC] = 0x0880, |
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[PMIF_SWINF_2_WDATA_31_0] = 0x0884, |
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[PMIF_SWINF_2_RDATA_31_0] = 0x0894, |
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[PMIF_SWINF_2_VLD_CLR] = 0x08A4, |
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[PMIF_SWINF_2_STA] = 0x08A8, |
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[PMIF_SWINF_3_ACC] = 0x08C0, |
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[PMIF_SWINF_3_WDATA_31_0] = 0x08C4, |
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[PMIF_SWINF_3_RDATA_31_0] = 0x08D4, |
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[PMIF_SWINF_3_VLD_CLR] = 0x08E4, |
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[PMIF_SWINF_3_STA] = 0x08E8, |
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}; |
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enum spmi_regs { |
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SPMI_OP_ST_CTRL, |
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SPMI_GRP_ID_EN, |
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SPMI_OP_ST_STA, |
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SPMI_MST_SAMPL, |
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SPMI_MST_REQ_EN, |
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SPMI_REC_CTRL, |
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SPMI_REC0, |
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SPMI_REC1, |
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SPMI_REC2, |
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SPMI_REC3, |
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SPMI_REC4, |
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SPMI_MST_DBG, |
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/* MT8195 spmi regs */ |
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SPMI_MST_RCS_CTRL, |
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SPMI_SLV_3_0_EINT, |
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SPMI_SLV_7_4_EINT, |
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SPMI_SLV_B_8_EINT, |
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SPMI_SLV_F_C_EINT, |
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SPMI_REC_CMD_DEC, |
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SPMI_DEC_DBG, |
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}; |
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static const u32 mt6873_spmi_regs[] = { |
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[SPMI_OP_ST_CTRL] = 0x0000, |
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[SPMI_GRP_ID_EN] = 0x0004, |
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[SPMI_OP_ST_STA] = 0x0008, |
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[SPMI_MST_SAMPL] = 0x000c, |
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[SPMI_MST_REQ_EN] = 0x0010, |
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[SPMI_REC_CTRL] = 0x0040, |
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[SPMI_REC0] = 0x0044, |
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[SPMI_REC1] = 0x0048, |
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[SPMI_REC2] = 0x004c, |
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[SPMI_REC3] = 0x0050, |
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[SPMI_REC4] = 0x0054, |
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[SPMI_MST_DBG] = 0x00fc, |
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}; |
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static const u32 mt8195_spmi_regs[] = { |
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[SPMI_OP_ST_CTRL] = 0x0000, |
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[SPMI_GRP_ID_EN] = 0x0004, |
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[SPMI_OP_ST_STA] = 0x0008, |
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[SPMI_MST_SAMPL] = 0x000C, |
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[SPMI_MST_REQ_EN] = 0x0010, |
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[SPMI_MST_RCS_CTRL] = 0x0014, |
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[SPMI_SLV_3_0_EINT] = 0x0020, |
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[SPMI_SLV_7_4_EINT] = 0x0024, |
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[SPMI_SLV_B_8_EINT] = 0x0028, |
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[SPMI_SLV_F_C_EINT] = 0x002C, |
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[SPMI_REC_CTRL] = 0x0040, |
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[SPMI_REC0] = 0x0044, |
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[SPMI_REC1] = 0x0048, |
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[SPMI_REC2] = 0x004C, |
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[SPMI_REC3] = 0x0050, |
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[SPMI_REC4] = 0x0054, |
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[SPMI_REC_CMD_DEC] = 0x005C, |
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[SPMI_DEC_DBG] = 0x00F8, |
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[SPMI_MST_DBG] = 0x00FC, |
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}; |
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static u32 pmif_readl(struct pmif *arb, enum pmif_regs reg) |
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{ |
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return readl(arb->base + arb->data->regs[reg]); |
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} |
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static void pmif_writel(struct pmif *arb, u32 val, enum pmif_regs reg) |
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{ |
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writel(val, arb->base + arb->data->regs[reg]); |
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} |
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static void mtk_spmi_writel(struct pmif *arb, u32 val, enum spmi_regs reg) |
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{ |
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writel(val, arb->spmimst_base + arb->data->spmimst_regs[reg]); |
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} |
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static bool pmif_is_fsm_vldclr(struct pmif *arb) |
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{ |
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u32 reg_rdata; |
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reg_rdata = pmif_readl(arb, arb->chan.ch_sta); |
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return GET_SWINF(reg_rdata) == SWINF_WFVLDCLR; |
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} |
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static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) |
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{ |
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struct pmif *arb = spmi_controller_get_drvdata(ctrl); |
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u32 rdata, cmd; |
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int ret; |
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/* Check the opcode */ |
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if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP) |
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return -EINVAL; |
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cmd = opc - SPMI_CMD_RESET; |
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mtk_spmi_writel(arb, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL); |
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ret = readl_poll_timeout_atomic(arb->spmimst_base + arb->data->spmimst_regs[SPMI_OP_ST_STA], |
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rdata, (rdata & SPMI_OP_ST_BUSY) == SPMI_OP_ST_BUSY, |
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PMIF_DELAY_US, PMIF_TIMEOUT_US); |
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if (ret < 0) |
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dev_err(&ctrl->dev, "timeout, err = %d\n", ret); |
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return ret; |
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} |
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static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, |
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u16 addr, u8 *buf, size_t len) |
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{ |
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struct pmif *arb = spmi_controller_get_drvdata(ctrl); |
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struct ch_reg *inf_reg; |
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int ret; |
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u32 data, cmd; |
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/* Check for argument validation. */ |
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if (sid & ~0xf) { |
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dev_err(&ctrl->dev, "exceed the max slv id\n"); |
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return -EINVAL; |
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} |
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if (len > 4) { |
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dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len); |
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return -EINVAL; |
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} |
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if (opc >= 0x60 && opc <= 0x7f) |
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opc = PMIF_CMD_REG; |
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else if ((opc >= 0x20 && opc <= 0x2f) || (opc >= 0x38 && opc <= 0x3f)) |
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opc = PMIF_CMD_EXT_REG_LONG; |
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else |
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return -EINVAL; |
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/* Wait for Software Interface FSM state to be IDLE. */ |
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inf_reg = &arb->chan; |
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ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta], |
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data, GET_SWINF(data) == SWINF_IDLE, |
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PMIF_DELAY_US, PMIF_TIMEOUT_US); |
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if (ret < 0) { |
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/* set channel ready if the data has transferred */ |
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if (pmif_is_fsm_vldclr(arb)) |
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pmif_writel(arb, 1, inf_reg->ch_rdy); |
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dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n"); |
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return ret; |
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} |
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/* Send the command. */ |
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cmd = (opc << 30) | (sid << 24) | ((len - 1) << 16) | addr; |
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pmif_writel(arb, cmd, inf_reg->ch_send); |
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/* |
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* Wait for Software Interface FSM state to be WFVLDCLR, |
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* read the data and clear the valid flag. |
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*/ |
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ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta], |
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data, GET_SWINF(data) == SWINF_WFVLDCLR, |
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PMIF_DELAY_US, PMIF_TIMEOUT_US); |
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if (ret < 0) { |
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dev_err(&ctrl->dev, "failed to wait for SWINF_WFVLDCLR\n"); |
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return ret; |
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} |
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data = pmif_readl(arb, inf_reg->rdata); |
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memcpy(buf, &data, len); |
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pmif_writel(arb, 1, inf_reg->ch_rdy); |
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return 0; |
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} |
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static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, |
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u16 addr, const u8 *buf, size_t len) |
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{ |
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struct pmif *arb = spmi_controller_get_drvdata(ctrl); |
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struct ch_reg *inf_reg; |
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int ret; |
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u32 data, cmd; |
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if (len > 4) { |
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dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len); |
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return -EINVAL; |
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} |
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/* Check the opcode */ |
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if (opc >= 0x40 && opc <= 0x5F) |
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opc = PMIF_CMD_REG; |
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else if ((opc <= 0xF) || (opc >= 0x30 && opc <= 0x37)) |
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opc = PMIF_CMD_EXT_REG_LONG; |
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else if (opc >= 0x80) |
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opc = PMIF_CMD_REG_0; |
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else |
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return -EINVAL; |
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/* Wait for Software Interface FSM state to be IDLE. */ |
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inf_reg = &arb->chan; |
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ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta], |
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data, GET_SWINF(data) == SWINF_IDLE, |
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PMIF_DELAY_US, PMIF_TIMEOUT_US); |
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if (ret < 0) { |
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/* set channel ready if the data has transferred */ |
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if (pmif_is_fsm_vldclr(arb)) |
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pmif_writel(arb, 1, inf_reg->ch_rdy); |
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dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n"); |
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return ret; |
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} |
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/* Set the write data. */ |
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memcpy(&data, buf, len); |
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pmif_writel(arb, data, inf_reg->wdata); |
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|
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/* Send the command. */ |
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cmd = (opc << 30) | BIT(29) | (sid << 24) | ((len - 1) << 16) | addr; |
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pmif_writel(arb, cmd, inf_reg->ch_send); |
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return 0; |
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} |
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static const struct pmif_data mt6873_pmif_arb = { |
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.regs = mt6873_regs, |
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.spmimst_regs = mt6873_spmi_regs, |
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.soc_chan = 2, |
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}; |
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static const struct pmif_data mt8195_pmif_arb = { |
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.regs = mt8195_regs, |
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.spmimst_regs = mt8195_spmi_regs, |
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.soc_chan = 2, |
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}; |
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static int mtk_spmi_probe(struct platform_device *pdev) |
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{ |
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struct pmif *arb; |
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struct spmi_controller *ctrl; |
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int err, i; |
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u32 chan_offset; |
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ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*arb)); |
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if (!ctrl) |
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return -ENOMEM; |
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arb = spmi_controller_get_drvdata(ctrl); |
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arb->data = device_get_match_data(&pdev->dev); |
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if (!arb->data) { |
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err = -EINVAL; |
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dev_err(&pdev->dev, "Cannot get drv_data\n"); |
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goto err_put_ctrl; |
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} |
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arb->base = devm_platform_ioremap_resource_byname(pdev, "pmif"); |
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if (IS_ERR(arb->base)) { |
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err = PTR_ERR(arb->base); |
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goto err_put_ctrl; |
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} |
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arb->spmimst_base = devm_platform_ioremap_resource_byname(pdev, "spmimst"); |
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if (IS_ERR(arb->spmimst_base)) { |
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err = PTR_ERR(arb->spmimst_base); |
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goto err_put_ctrl; |
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} |
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arb->nclks = ARRAY_SIZE(pmif_clock_names); |
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for (i = 0; i < arb->nclks; i++) |
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arb->clks[i].id = pmif_clock_names[i]; |
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err = devm_clk_bulk_get(&pdev->dev, arb->nclks, arb->clks); |
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if (err) { |
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dev_err(&pdev->dev, "Failed to get clocks: %d\n", err); |
|
goto err_put_ctrl; |
|
} |
|
|
|
err = clk_bulk_prepare_enable(arb->nclks, arb->clks); |
|
if (err) { |
|
dev_err(&pdev->dev, "Failed to enable clocks: %d\n", err); |
|
goto err_put_ctrl; |
|
} |
|
|
|
ctrl->cmd = pmif_arb_cmd; |
|
ctrl->read_cmd = pmif_spmi_read_cmd; |
|
ctrl->write_cmd = pmif_spmi_write_cmd; |
|
|
|
chan_offset = PMIF_CHAN_OFFSET * arb->data->soc_chan; |
|
arb->chan.ch_sta = PMIF_SWINF_0_STA + chan_offset; |
|
arb->chan.wdata = PMIF_SWINF_0_WDATA_31_0 + chan_offset; |
|
arb->chan.rdata = PMIF_SWINF_0_RDATA_31_0 + chan_offset; |
|
arb->chan.ch_send = PMIF_SWINF_0_ACC + chan_offset; |
|
arb->chan.ch_rdy = PMIF_SWINF_0_VLD_CLR + chan_offset; |
|
|
|
platform_set_drvdata(pdev, ctrl); |
|
|
|
err = spmi_controller_add(ctrl); |
|
if (err) |
|
goto err_domain_remove; |
|
|
|
return 0; |
|
|
|
err_domain_remove: |
|
clk_bulk_disable_unprepare(arb->nclks, arb->clks); |
|
err_put_ctrl: |
|
spmi_controller_put(ctrl); |
|
return err; |
|
} |
|
|
|
static int mtk_spmi_remove(struct platform_device *pdev) |
|
{ |
|
struct spmi_controller *ctrl = platform_get_drvdata(pdev); |
|
struct pmif *arb = spmi_controller_get_drvdata(ctrl); |
|
|
|
clk_bulk_disable_unprepare(arb->nclks, arb->clks); |
|
spmi_controller_remove(ctrl); |
|
spmi_controller_put(ctrl); |
|
return 0; |
|
} |
|
|
|
static const struct of_device_id mtk_spmi_match_table[] = { |
|
{ |
|
.compatible = "mediatek,mt6873-spmi", |
|
.data = &mt6873_pmif_arb, |
|
}, { |
|
.compatible = "mediatek,mt8195-spmi", |
|
.data = &mt8195_pmif_arb, |
|
}, { |
|
/* sentinel */ |
|
}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, mtk_spmi_match_table); |
|
|
|
static struct platform_driver mtk_spmi_driver = { |
|
.driver = { |
|
.name = "spmi-mtk", |
|
.of_match_table = of_match_ptr(mtk_spmi_match_table), |
|
}, |
|
.probe = mtk_spmi_probe, |
|
.remove = mtk_spmi_remove, |
|
}; |
|
module_platform_driver(mtk_spmi_driver); |
|
|
|
MODULE_AUTHOR("Hsin-Hsiung Wang <[email protected]>"); |
|
MODULE_DESCRIPTION("MediaTek SPMI Driver"); |
|
MODULE_LICENSE("GPL");
|
|
|